JP2001144392A - Printed wiring board - Google Patents
Printed wiring boardInfo
- Publication number
- JP2001144392A JP2001144392A JP32735299A JP32735299A JP2001144392A JP 2001144392 A JP2001144392 A JP 2001144392A JP 32735299 A JP32735299 A JP 32735299A JP 32735299 A JP32735299 A JP 32735299A JP 2001144392 A JP2001144392 A JP 2001144392A
- Authority
- JP
- Japan
- Prior art keywords
- plating layer
- wiring
- layer
- nickel
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Chemically Coating (AREA)
- Other Surface Treatments For Metallic Materials (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子や容量
素子、抵抗器等の電子部品が搭載される配線基板に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board on which electronic components such as a semiconductor element, a capacitor, and a resistor are mounted.
【０００２】[0002]
【従来の技術】従来、半導体素子や容量素子、抵抗器等
の電子部品が搭載される配線基板は、一般に、酸化アル
ミニウム質焼結体やガラスセラミックス焼結体から成る
絶縁基体と、該絶縁基体の上面から下面にかけて形成さ
れたタングステン、モリブデン、銅等の金属材料から成
る複数個の配線層とから構成されており、絶縁基体の上
面に半導体素子や容量素子、抵抗器等の電子部品を搭載
するとともに該電子部品の各電極を配線層に錫―鉛半田
等の低融点ロウ材を介して電気的に接続するようになっ
ている。2. Description of the Related Art Conventionally, a wiring board on which electronic components such as a semiconductor element, a capacitor element, and a resistor are mounted generally includes an insulating base made of an aluminum oxide sintered body or a glass ceramic sintered body, and an insulating base made of the same. It consists of a plurality of wiring layers made of metal material such as tungsten, molybdenum, copper, etc. formed from the upper surface to the lower surface of the substrate, and electronic components such as semiconductor elements, capacitive elements, resistors, etc. are mounted on the upper surface of the insulating base In addition, each electrode of the electronic component is electrically connected to a wiring layer via a low-melting-point brazing material such as tin-lead solder.
【０００３】かかる配線基板は、絶縁基体の下面に導出
されている配線層の一部を外部電気回路基板の配線導体
に低融点ロウ材を介し接続することによって外部電気回
路基板上に実装され、同時に配線基板に搭載されている
電子部品の各電極が所定の外部電気回路に電気的に接続
されることとなる。Such a wiring board is mounted on an external electric circuit board by connecting a part of a wiring layer led out to the lower surface of an insulating base to a wiring conductor of the external electric circuit board via a low melting point brazing material, At the same time, each electrode of the electronic component mounted on the wiring board is electrically connected to a predetermined external electric circuit.
【０００４】また、前記配線基板は配線層の露出表面に
ニッケルめっき層と金めっき層が順次被着されており、
該ニッケルめっき層は配線層と金めっき層とを強固に接
合するとともに配線層が酸化するのを有効に防止する作
用をなし、また金めっき層は配線層に対する低融点ロウ
材の接合を良好とするとともにニッケルめっき層が酸化
するのを有効に防止する作用をなしている。Further, the wiring board has a nickel plating layer and a gold plating layer sequentially deposited on an exposed surface of the wiring layer,
The nickel plating layer has a function of firmly joining the wiring layer and the gold plating layer and effectively preventing the wiring layer from being oxidized, and the gold plating layer has good bonding of the low melting point brazing material to the wiring layer. At the same time, it effectively prevents the nickel plating layer from being oxidized.
【０００５】なお、前記ニッケルめっき層は一般に還元
剤として次亜リン酸塩を使用したニッケルめっき液を用
いることによって配線層の表面に被着形成されており、
そのため形成されたニッケルめっき層はリン（Ｐ）が５
重量％程度含有されたニッケル−リンの多結晶構造とな
っている。The nickel plating layer is generally formed on the surface of the wiring layer by using a nickel plating solution using hypophosphite as a reducing agent.
Therefore, the formed nickel plating layer contains 5 phosphorus (P).
It has a polycrystalline structure of nickel-phosphorus containing about wt%.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記従
来の配線基板では、配線層の表面にニッケル−リンの多
結晶構造を有するニッケルめっき層が被着されており、
該ニッケル−リンの多結晶構造を有するニッケルめっき
層は磁性を有していることから、配線基板にミリ波帯、
マイクロ波帯の高周波信号を使用する半導体素子を搭載
させ、配線層に高周波信号を伝播させた場合、前記磁性
に起因する表皮抵抗の増加により高周波信号に大きな損
失が発生し、半導体素子に高周波信号を正確に入力する
のができなくなって半導体素子を常に正確に作動させる
ことができないという欠点を有していた。However, in the above-mentioned conventional wiring board, a nickel plating layer having a polycrystalline structure of nickel-phosphorus is coated on the surface of the wiring layer,
Since the nickel-plated layer having a nickel-phosphorus polycrystalline structure has magnetism, the wiring substrate has a millimeter wave band,
When a semiconductor element using a microwave band high-frequency signal is mounted and a high-frequency signal is propagated through a wiring layer, a large loss occurs in the high-frequency signal due to an increase in skin resistance caused by the magnetism, and the high-frequency signal is applied to the semiconductor element. Cannot be input accurately, and the semiconductor element cannot always be operated accurately.
【０００７】本発明は上記欠点に鑑み案出されたもの
で、その目的は配線層に高周波信号を伝播させた際、配
線層で高周波信号に大きな損失が発生するのを有効に防
止し、配線層を介して半導体素子に高周波信号を確実に
入力して半導体素子を常に正確に作動させることができ
る配線基板を提供することにある。The present invention has been made in view of the above-mentioned drawbacks, and has as its object to effectively prevent a large loss of a high-frequency signal in a wiring layer when the high-frequency signal is propagated through the wiring layer. An object of the present invention is to provide a wiring board that can reliably input a high-frequency signal to a semiconductor element via a layer and always operate the semiconductor element accurately.
【０００８】[0008]
【課題を解決するための手段】本発明の配線基板は、絶
縁基体と、該絶縁基体の表面に被着形成された配線層と
から成る配線基板であって、前記配線層の表面にニッケ
ル−リンのアモルファス合金から成るニッケルめっき層
と金めっき層を順次被着させたことを特徴とするもので
ある。A wiring board according to the present invention is a wiring board comprising an insulating base and a wiring layer formed on the surface of the insulating base. The present invention is characterized in that a nickel plating layer and a gold plating layer made of an amorphous alloy of phosphorus are sequentially deposited.
【０００９】また本発明の配線基板は、前記ニッケルめ
っき層のリンの含有率が８．０乃至１５．０重量％であ
ることを特徴とするものである。In the wiring board according to the present invention, the nickel plating layer has a phosphorus content of 8.0 to 15.0% by weight.
【００１０】本発明の配線基板は、配線層の表面にニッ
ケル−リンのアモルファス合金から成るニッケルめっき
層と金めっき層を被着させたものであり、ニッケル−リ
ンのアモルファス合金から成るニッケルめっき層は非磁
性であることから、配線基板にミリ波帯、マイクロ波帯
の高周波信号を使用する半導体素子を搭載させ、配線層
に高周波信号を伝播させたとしても高周波信号に大きな
損失が発生することはなく、その結果、半導体素子に高
周波信号を正確に入力することが可能となるとともに半
導体素子を常に正確に作動させることができる。The wiring board according to the present invention is obtained by applying a nickel plating layer made of a nickel-phosphorous amorphous alloy and a gold plating layer on the surface of a wiring layer, and a nickel plating layer made of a nickel-phosphorous amorphous alloy. Is non-magnetic, so even if a semiconductor element that uses high-frequency signals in the millimeter-wave band or microwave band is mounted on the wiring board and the high-frequency signals are propagated through the wiring layer, large losses will occur in the high-frequency signals. However, as a result, a high-frequency signal can be accurately input to the semiconductor element, and the semiconductor element can always be operated accurately.
【００１１】[0011]
【発明の実施の形態】次に本発明を添付図面に示す実施
例に基づいて詳細に説明する。図１は、本発明の配線基
板を使用した半導体素子収納用パッケージの一実施例を
示し、１は絶縁基体、２は配線層である。この絶縁基体
1と配線層２とで半導体素子３を搭載する配線基板４が
構成される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to the embodiments shown in the accompanying drawings. FIG. 1 shows an embodiment of a package for housing a semiconductor element using a wiring board of the present invention, wherein 1 is an insulating base, and 2 is a wiring layer. This insulating substrate
1 and the wiring layer 2 constitute a wiring board 4 on which the semiconductor element 3 is mounted.
【００１２】前記絶縁基体1は、例えば、ガラスセラミ
ックス焼結体、酸化アルミニウム質焼結体、ムライト質
焼結体、窒化アルミニウム質焼結体、炭化珪素質焼結体
等の電気絶縁材料から成り、その上面に半導体素子３を
搭載する搭載部１ａを有し、該搭載部１ａ表面には半導
体素子３がガラスや樹脂、ロウ材等の接着剤を介して接
着固定される。The insulating substrate 1 is made of an electrically insulating material such as a glass ceramic sintered body, an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, and a silicon carbide sintered body. The semiconductor device 3 has a mounting portion 1a on which the semiconductor element 3 is mounted, and the semiconductor element 3 is bonded and fixed to the surface of the mounting portion 1a via an adhesive such as glass, resin, or brazing material.
【００１３】前記絶縁基体１は、例えば、ガラスセラミ
ックス焼結体から成る場合には、酸化マグネシウム、酸
化アルミニウム、酸化珪素、酸化亜鉛、酸化ホウ素等の
原料粉末に適当な有機バインダ・溶剤を添加混合して泥
漿状となすことによって複数枚のガラスセラミックグリ
ーンシートを得、しかる後、所定のガラスセラミックグ
リーンシートの各々に適当な打ち抜き加工を施すととも
にこれらを積層し、約１０００℃で焼成することによっ
て製作される。When the insulating substrate 1 is made of, for example, a glass ceramic sintered body, an appropriate organic binder / solvent is added to a raw material powder such as magnesium oxide, aluminum oxide, silicon oxide, zinc oxide, and boron oxide. Then, a plurality of glass ceramic green sheets are obtained by forming a slurry, and thereafter, a predetermined punching process is performed on each of the predetermined glass ceramic green sheets, and they are laminated and fired at about 1000 ° C. Be produced.
【００１４】また前記絶縁基体１は、搭載部１ａ周辺か
ら上面外周部にかけて複数個の配線層２が被着形成され
ており、該配線層２の搭載部１ａ周辺部位には半導体素
子３の電極がボンディングワイヤ５を介して電気的に接
続され、また絶縁基体１の上面外周部に導出された部位
は外部電気回路の配線導体に低融点ロウ材等の導電性接
続材を介して接続される。A plurality of wiring layers 2 are formed on the insulating base 1 from the periphery of the mounting portion 1a to the outer peripheral portion of the upper surface. Are electrically connected via bonding wires 5, and a portion led out to the outer peripheral portion of the upper surface of the insulating base 1 is connected to a wiring conductor of an external electric circuit via a conductive connecting material such as a low melting point brazing material. .
【００１５】前記配線層２は、銅、銀等の非磁性の金属
粉末から成り、銅、銀等の金属粉末に適当な有機バイン
ダや溶剤を添加混合して得た金属ペーストを絶縁基体１
となるガラスセラミックグリーンシートに予め従来周知
のスクリーン印刷法により印刷塗布しておくことによっ
て、絶縁基体１の搭載部１ａ周辺から外周部にかけて被
着される。The wiring layer 2 is made of a non-magnetic metal powder such as copper or silver. A metal paste obtained by adding a suitable organic binder or a solvent to a metal powder such as copper or silver is mixed with an insulating substrate 1.
The glass ceramic green sheet is printed and applied in advance by a well-known screen printing method, so that the insulating substrate 1 is attached from the periphery to the outer periphery of the mounting portion 1a.
【００１６】更に、前記配線層２の表面には、図２に示
すようにニッケル−リンのアモルファス合金から成るニ
ッケルめっき層６と金めっき層７とが順次被着されてい
る。Further, on the surface of the wiring layer 2, a nickel plating layer 6 made of an amorphous alloy of nickel-phosphorus and a gold plating layer 7 are sequentially deposited as shown in FIG.
【００１７】前記ニッケルめっき層６は、配線層２およ
び金めっき層７のいずれとも密着性が良好であることか
ら、配線層２に金めっき層７を強固に被着させる下地め
っき層として作用する。Since the nickel plating layer 6 has good adhesion to both the wiring layer 2 and the gold plating layer 7, the nickel plating layer 6 acts as a base plating layer for firmly attaching the gold plating layer 7 to the wiring layer 2. .
【００１８】前記ニッケルめっき層６は、ニッケル−リ
ンのアモルファス合金により形成されており、該ニッケ
ル−リンアモルファス合金は非磁性であることから、配
線基板４に搭載された半導体素子３がミリ波帯、マイク
ロ波帯の高周波信号を使用し、配線層２に高周波信号が
伝播されたとしても、この高周波信号に大きな損失が生
じることはなく、半導体素子３に高周波信号が確実に入
力されて半導体素子３を正確に作動させることができ
る。The nickel plating layer 6 is formed of a nickel-phosphorus amorphous alloy, and since the nickel-phosphorus amorphous alloy is non-magnetic, the semiconductor element 3 mounted on the wiring board 4 can be used in a millimeter wave band. Even if a high-frequency signal in the microwave band is used and the high-frequency signal is propagated to the wiring layer 2, no large loss occurs in the high-frequency signal, and the high-frequency signal is reliably input to the semiconductor element 3. 3 can be operated accurately.
【００１９】前記ニッケル−リンアモルファス合金から
成るニッケルめっき層６は、ニッケルにリンを従来より
多い８．０乃至１５．０重量％含有させることによって
形成され、具体的には、クエン酸ナトリウム、コハク酸
ナトリウム、リンゴ酸ナトリウム等の有機酸と硫酸ニッ
ケル８０〜２５０グラム／リットルと次亜リン酸ナトリ
ウム２００〜４００グラム／リットル（従来の倍以上）
から成る無電解めっき浴を準備するとともに該無電解め
っき浴の浴温を８０〜９５℃にし、浴中に配線基板４を
所定時間浸漬しておくことにより所定厚みに配線層２の
露出表面に被着形成される。The nickel plating layer 6 made of the nickel-phosphorus amorphous alloy is formed by adding nickel to nickel at 8.0 to 15.0% by weight, which is higher than that of the conventional nickel plating layer. Organic acids such as sodium citrate and sodium malate, nickel sulfate 80-250 g / l and sodium hypophosphite 200-400 g / l (more than double the conventional amount)
Is prepared, the bath temperature of the electroless plating bath is set to 80 to 95 ° C., and the wiring board 4 is immersed in the bath for a predetermined time so that the exposed surface of the wiring layer 2 has a predetermined thickness. Is formed.
【００２０】なお、前記ニッケルめっき層６はその内部
に含有されるリンの量が８重量％未満であるとニッケル
めっき層６が磁性を有し、配線層２を伝播する高周波信
号に大きな損失を招来させてしまい、また１５重量％を
超えるとニッケルめっき層６を形成する際、リンが単独
に、優先的に析出してニッケル−リンのアモルファス合
金を形成することができなくなる。従って、前記ニッケ
ル−リンのアモルファス合金から成るニッケルめっき層
６は内部に含有されるリンの量が８〜１５重量％の範囲
に特定され、好適には１０〜１５重量％の範囲がよい。If the amount of phosphorus contained in the nickel plating layer 6 is less than 8% by weight, the nickel plating layer 6 has magnetism and causes a large loss in a high-frequency signal propagating through the wiring layer 2. If the content exceeds 15% by weight, when the nickel plating layer 6 is formed, phosphorus alone and preferentially precipitates, making it impossible to form a nickel-phosphorus amorphous alloy. Therefore, in the nickel plating layer 6 made of the nickel-phosphorus amorphous alloy, the amount of phosphorus contained therein is specified in the range of 8 to 15% by weight, and preferably in the range of 10 to 15% by weight.
【００２１】また、前記配線層２の表面に被着されるニ
ッケルめっき層６は、その厚みが１μｍ未満であると配
線層２の表面をニッケルめっき層６で完全に被覆するこ
とができず、金めっき層７の配線層２に対する被着強度
が小さくなる傾向があり、また８μｍを超えるとニッケ
ルめっき層６を形成する際に発生する応力によって配線
層２に対するニッケルめっき層６の被着強度が低下し、
ニッケルめっき層２が配線層２より剥離してしまう危険
性がある。従って、前記ニッケルめっき層６は、その厚
さを１μｍ〜８μｍの範囲としておくことが好ましい。If the thickness of the nickel plating layer 6 attached to the surface of the wiring layer 2 is less than 1 μm, the surface of the wiring layer 2 cannot be completely covered with the nickel plating layer 6. The adhesion strength of the gold plating layer 7 to the wiring layer 2 tends to decrease, and if it exceeds 8 μm, the adhesion strength of the nickel plating layer 6 to the wiring layer 2 is reduced by the stress generated when the nickel plating layer 6 is formed. Drop,
There is a risk that the nickel plating layer 2 will peel off from the wiring layer 2. Therefore, it is preferable that the nickel plating layer 6 has a thickness in a range of 1 μm to 8 μm.
【００２２】更に前記ニッケルめっき層６の表面には金
めっき層７が被着形成されており、該金めっき層７は、
配線層２およびニッケルめっき層６の酸化腐食を防止す
るとともに、配線層２における低融点ロウ材の濡れ性や
ボンディングワイヤの接合性を良好とする作用をなし、
同時に配線層２に高周波信号を伝播させる際の主導体と
して作用する。Further, a gold plating layer 7 is formed on the surface of the nickel plating layer 6, and the gold plating layer 7
The effect of preventing oxidation corrosion of the wiring layer 2 and the nickel plating layer 6 and improving the wettability of the low melting point brazing material and the bonding property of the bonding wire in the wiring layer 2 is achieved.
At the same time, it acts as a main conductor when transmitting a high-frequency signal to the wiring layer 2.
【００２３】前記金めっき層７は、例えば、金化合物で
あるシアン化金カリウムおよび錯化剤であるエチレンジ
アミン四酢酸を主成分とし、シアン化カリウム、リン酸
二水素カリウム等を添加して成る置換型の金めっき液
と、金化合物であるシアン化金カリウムおよび還元剤で
ある水素化ホウ素ナトリウムとを主成分とする還元型の
金めっき液とを準備し、これに前記ニッケルめっき層６
を被着させた配線層２の露出面を前記置換型の金めっき
液、還元型の金めっき液の順に所定時間浸漬させること
によって、ニッケルめっき層６上に所定厚みに被着され
る。The gold plating layer 7 is, for example, a substitutional type composed mainly of gold potassium cyanide as a gold compound and ethylenediaminetetraacetic acid as a complexing agent, and added with potassium cyanide, potassium dihydrogen phosphate and the like. A gold plating solution and a reduction-type gold plating solution containing gold potassium cyanide as a gold compound and sodium borohydride as a reducing agent as main components are prepared, and the nickel plating layer 6 is added thereto.
The exposed surface of the wiring layer 2 to which is applied is immersed for a predetermined time in the order of the replacement-type gold plating solution and the reduction-type gold plating solution for a predetermined thickness on the nickel plating layer 6.
【００２４】前記金めっき層７は、その厚さが１μｍ未
満となると、配線層２の電気抵抗が増大し、高周波信号
を伝播させたときの損失が大きくなったり、配線層２へ
のボンディングワイヤ５の接合性が低くなったりするお
それがある。従って、前記金めっき層７は、その厚さを
１μｍ以上としておくことが好ましく、経済性を考慮す
れば１μｍ〜３μｍの範囲としておくことが好ましい。When the thickness of the gold plating layer 7 is less than 1 μm, the electric resistance of the wiring layer 2 increases, the loss when transmitting a high-frequency signal increases, and the bonding wire to the wiring layer 2 increases. There is a possibility that the bonding property of No. 5 may decrease. Therefore, the thickness of the gold plating layer 7 is preferably set to 1 μm or more, and is preferably set to 1 μm to 3 μm in consideration of economy.
【００２５】かくして本発明の配線基板によれば、絶縁
基体１の半導体素子搭載部１ａ上に半導体素子３をガラ
スや樹脂、ロウ材等の接着剤を介して接着固定するとと
もにこの半導体素子３の各電極を配線層２にボンディン
グワイヤ５を介して電気的に接続し、しかる後、絶縁基
体１の上面に金属やセラミックスから成る椀状の蓋体８
をガラスや樹脂、ロウ材等の封止材を介して接合させ、
絶縁基体１と蓋体８とから成る容器内部に半導体素子３
を気密に収容することによって製品としての半導体装置
が完成する。Thus, according to the wiring board of the present invention, the semiconductor element 3 is bonded and fixed on the semiconductor element mounting portion 1a of the insulating base 1 via an adhesive such as glass, resin, brazing material or the like. Each electrode is electrically connected to the wiring layer 2 via a bonding wire 5, and then a bowl-shaped lid 8 made of metal or ceramic is formed on the upper surface of the insulating base 1.
Through a sealing material such as glass, resin, brazing material,
The semiconductor element 3 is placed inside a container comprising the insulating base 1 and the lid 8.
The semiconductor device as a product is completed by housing the airtightly.
【００２６】なお、本発明の配線基板は上述の実施の形
態に限定されるものではなく、本発明の要旨を逸脱しな
い範囲であれば種々の変更は可能であり、例えば、上述
の実施例では本発明の配線基板を半導体素子を収容する
半導体素子収納用パッケージに適用した場合を例に挙げ
て説明したが、これを高周波半導体素子が搭載される混
成集積回路基板に適用した場合であってもよい。It should be noted that the wiring board of the present invention is not limited to the above-described embodiment, and various changes can be made without departing from the gist of the present invention. Although the case where the wiring board of the present invention is applied to a semiconductor element housing package for housing a semiconductor element has been described as an example, even when this is applied to a hybrid integrated circuit board on which a high-frequency semiconductor element is mounted, Good.
【００２７】[0027]
【発明の効果】本発明の配線基板は、配線層の表面にニ
ッケル−リンのアモルファス合金から成るニッケルめっ
き層と金めっき層を被着させたものであり、ニッケル−
リンのアモルファス合金から成るニッケルめっき層は非
磁性であることから、配線基板にミリ波帯、マイクロ波
帯の高周波信号を使用する半導体素子を搭載させ、配線
層に高周波信号を伝播させたしても高周波信号に大きな
損失が発生することはなく、その結果、半導体素子に高
周波信号を正確に入力することが可能となるとともに半
導体素子を常に正確に作動させることができる。The wiring board according to the present invention has a nickel plating layer made of an amorphous alloy of nickel-phosphorus and a gold plating layer deposited on the surface of the wiring layer.
Since the nickel plating layer made of an amorphous alloy of phosphorus is nonmagnetic, a semiconductor element that uses high-frequency signals in the millimeter-wave band and microwave band is mounted on the wiring board, and the high-frequency signals are propagated through the wiring layer. Also, a large loss does not occur in the high-frequency signal, and as a result, the high-frequency signal can be accurately input to the semiconductor element and the semiconductor element can always be operated accurately.
【図１】本発明の配線基板を半導体素子収納用パッケー
ジに適用した場合の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment in which a wiring board of the present invention is applied to a package for housing a semiconductor element.
【図２】図１に示す配線基板の要部拡大断面図である。FIG. 2 is an enlarged sectional view of a main part of the wiring board shown in FIG.
１・・・・絶縁基体 １ａ・・・半導体素子搭載部 ２・・・・配線層 ３・・・・半導体素子 ４・・・・配線基板 ５・・・・ボンディングワイヤ ６・・・・ニッケルめっき層 ７・・・・金めっき層 ８・・・・蓋体 DESCRIPTION OF SYMBOLS 1 ... Insulating base 1a ... Semiconductor element mounting part 2 ... Wiring layer 3 ... Semiconductor element 4 ... Wiring board 5 ... Bonding wire 6 ... Nickel plating Layer 7: Gold plating layer 8: Lid
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 4E351 AA07 BB01 BB23 BB24 BB31 BB33 BB35 CC06 CC12 DD06 DD19 DD21 GG07 4K022 AA02 AA42 BA03 BA14 BA16 BA32 DA01 4K044 AA06 AB10 BA06 BA08 BB03 BB17 BC14 CA15 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4E351 AA07 BB01 BB23 BB24 BB31 BB33 BB35 CC06 CC12 DD06 DD19 DD21 GG07 4K022 AA02 AA42 BA03 BA14 BA16 BA32 DA01 4K044 AA06 AB10 BA06 BA08 BB03 BB17 BC14 CA15
Claims (2)
された配線層とから成る配線基板であって、前記配線層
の表面にニッケル−リンのアモルファス合金から成るニ
ッケルめっき層と金めっき層が順次被着されていること
を特徴とする配線基板。1. A wiring board comprising an insulating base and a wiring layer formed on the surface of the insulating base, wherein a nickel plating layer made of a nickel-phosphorus amorphous alloy is formed on the surface of the wiring layer. A wiring board, wherein a plating layer is sequentially applied.
８．０乃至１５．０重量％であることを特徴とする請求
項１に記載の配線基板。2. The wiring board according to claim 1, wherein the nickel plating layer has a phosphorus content of 8.0 to 15.0% by weight.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32735299A JP2001144392A (en) | 1999-11-17 | 1999-11-17 | Printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32735299A JP2001144392A (en) | 1999-11-17 | 1999-11-17 | Printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001144392A true JP2001144392A (en) | 2001-05-25 |
Family
ID=18198195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32735299A Pending JP2001144392A (en) | 1999-11-17 | 1999-11-17 | Printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001144392A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005286323A (en) * | 2004-03-05 | 2005-10-13 | Ngk Spark Plug Co Ltd | Wiring substrate, wiring substrate with solder member, and manufacturing method of the same |
| JP2010040679A (en) * | 2008-08-01 | 2010-02-18 | Kyushu Hitachi Maxell Ltd | Semiconductor device and its production process |
| JP2014135509A (en) * | 2014-03-19 | 2014-07-24 | Hitachi Maxell Ltd | Intermediate molded product for semiconductor device and semiconductor device |
| WO2018097017A1 (en) | 2016-11-25 | 2018-05-31 | 古河電気工業株式会社 | Transmission line |
-
1999
- 1999-11-17 JP JP32735299A patent/JP2001144392A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005286323A (en) * | 2004-03-05 | 2005-10-13 | Ngk Spark Plug Co Ltd | Wiring substrate, wiring substrate with solder member, and manufacturing method of the same |
| JP2010040679A (en) * | 2008-08-01 | 2010-02-18 | Kyushu Hitachi Maxell Ltd | Semiconductor device and its production process |
| JP2014135509A (en) * | 2014-03-19 | 2014-07-24 | Hitachi Maxell Ltd | Intermediate molded product for semiconductor device and semiconductor device |
| WO2018097017A1 (en) | 2016-11-25 | 2018-05-31 | 古河電気工業株式会社 | Transmission line |
| EP3534456A4 (en) * | 2016-11-25 | 2020-05-20 | Furukawa Electric Co., Ltd. | Transmission line |
| US11575190B2 (en) | 2016-11-25 | 2023-02-07 | Furukawa Electric Co., Ltd. | Transmission path for transmitting high-frequency signals greater than 14ghz, where the transmission path includes a nickel-phosphorous layer with phosphorous concentrations between 0 mass% to 8 mass% |
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