JP3645744B2 - Ceramic wiring board - Google Patents

Ceramic wiring board Download PDF

Info

Publication number
JP3645744B2
JP3645744B2 JP13478299A JP13478299A JP3645744B2 JP 3645744 B2 JP3645744 B2 JP 3645744B2 JP 13478299 A JP13478299 A JP 13478299A JP 13478299 A JP13478299 A JP 13478299A JP 3645744 B2 JP3645744 B2 JP 3645744B2
Authority
JP
Japan
Prior art keywords
conductor layer
semiconductor element
layer
wiring board
insulating base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP13478299A
Other languages
Japanese (ja)
Other versions
JP2000323622A (en
Inventor
一博 松尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP13478299A priority Critical patent/JP3645744B2/en
Publication of JP2000323622A publication Critical patent/JP2000323622A/en
Application granted granted Critical
Publication of JP3645744B2 publication Critical patent/JP3645744B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate

Description

【0001】
【発明の属する技術分野】
本発明は半導体素子を収容するための半導体素子収納用パッケージや混成集積回路基板等に用いられるセラミック配線基板に関し、より詳細には半導体素子がフリップチップ方式により搭載接続されるセラミック配線基板に関するものである。
【0002】
【従来の技術】
近年、半導体素子収納用パッケージや混成集積回路基板等に用いられるセラミック配線基板への半導体素子の搭載方法としては、半導体素子等の電子部品の高密度化、小型化に対応するためセラミック配線基板の表面に露出する貫通導体層に半導体素子の電極を半田等の電気的接続手段を介し直接接続する、所謂、フリップチップ方式のボンディングが多用されつつある。
【0003】
このフリップチップ方式のボンディングが採用される半導体素子収納用パッケージや混成集積回路基板等に用いられるセラミック配線基板は、一般に酸化アルミニウム質焼結体から成る絶縁基体と、該絶縁基体内に形成され、一端が絶縁基体の表面に露出するタングステン、モリブデン等の高融点金属から成る貫通導体層とから構成されており、貫通導体層の絶縁基体表面に露出する露出面に半導体素子等の電子部品の電極を半田ボール等から成る電気的接続手段を介し取着接続させることによって半導体素子等の電子部品はセラミック配線基板上に搭載されるとともに電子部品の各電極が貫通導体層に接続される。
【0004】
なお、前記貫通導体層の露出面には、通常、その酸化腐食を防ぐとともに半田ボール等から成る電気的接続手段に対する濡れ性を良好なものとするために、ニッケル、金等の耐食性に優れ、且つ半田等のろう材に対して濡れ性の良い金属層がめっき法により被着されている。
【0005】
またかかるセラミック配線基板は、一般に、セラミックスの積層技術及びスクリーン印刷等の厚膜形成技術を採用することによって製作されており、具体的には以下の方法によって製作される。
【0006】
即ち、
(1)まず、酸化アルミニウム(Al2 3 )、酸化珪素(SiO2 )酸化マグネシウム(MgO)、酸化カルシウム(CaO)等から成るセラミックス原料粉末に有機溶剤、溶媒を添加混合して泥漿物を作り、次にこれを従来周知のドクターブレード法やカレンダーロール法等によりシート状に成形して複数枚のセラミックグリーンシート(セラミック生シート)を形成するとともに所定位置に打ち抜き加工等により貫通孔を形成する。
【0007】
(2)次に、前記貫通孔内に、タングステン、モリブデン等の金属の粉末に有機溶剤、溶媒を添加混合して得た導電ペーストをスクリーン印刷法等により印刷充填する。
【0008】
(3)そして最後に、これらのセラミックグリーンシートを、前記貫通孔に印刷充填した導電ペーストの一端が露出するようにして上下に積層するとともに、還元雰囲気中、約1600℃の温度で焼成し、セラミックグリーンシートと導電ペーストとを焼結一体化することによってセラミック配線基板が完成する。
【0009】
この場合、セラミックグリーンシートと導電ペーストの焼結開始温度が相違すると焼結に伴なう収縮の開始時期がセラミックグリーンシートと導電ペーストとの間で相違して絶縁基体と貫通導体層との間に応力が発生し、絶縁基体にクラック等が生じてしまうため導電ペーストは、通常、その焼結開始温度がセラミックグリーンシートの焼結開始温度に近似したものが用いられる。
【0010】
しかしながら、近時、半導体素子の大型化、信号の伝播速度の高速化が急激に進み、該半導体素子を上記従来のセラミック配線基板に搭載した場合、以下に述べる欠点を有したものとなる。
【0011】
即ち、
(1)半導体素子を構成するシリコンと絶縁基体を構成する酸化アルミニウム質焼結体の熱膨張係数がそれぞれ3.0×10-6/℃〜3.5×10-6/℃、6.0×10-6/℃〜7.5×10-6/℃であり、大きく相違することから両者に半導体素子を作動させた際等に発生する熱が印加されると両者間に大きな熱応力が発生し、該熱応力によって半田ボール等の電気的接続手段や半導体素子が破損したり、絶縁基体より剥離して半導体装置としての機能を喪失させてしまう。
【0012】
(2)絶縁基体を構成する酸化アルミニウム質焼結体はその誘電率が9〜10(室温1MHz)と高いため、絶縁基体に設けた貫通導体層を伝わる信号の伝播速度が遅く、そのため信号の高速伝播を要求する半導体素子はその搭載が不可となる。
【0013】
そこで上記欠点を解消するために、絶縁基体を酸化アルミニウム質焼結体に代えて半導体素子を構成するシリコンの熱膨張係数(3.0×10-6/℃〜3.5×10-6/℃)と近似した熱膨張係数4.0×10-6/℃〜4.5×10-6/℃を有し、且つ誘電率が6.3と低いムライト質焼結体で形成することが考えられる。
【0014】
【発明が解決しようとする課題】
しかしながら、絶縁基体をムライト質焼結体で形成した場合、貫通導体層となる導電ペーストは、その焼結開始温度をムライト質焼結体となるセラミックグリーンシートと近似させるためにモリブデンを主成分とする金属粉末を用いる必要があり、このモリブデンで貫通導体層を形成した場合、該モリブデンは酸化されやすい金属であり、露出表面に酸化物が極めて容易に形成されてしまい、貫通導体層の露出表面に酸化物が形成されると貫通導体層の露出表面にニッケル等のめっき層を密着性良く形成することができなくなり、その結果、貫通導体層に電子部品の各電極を半田ボール等からなる電気的接続手段を介して強固に電気的に接続させることができないという欠点を有していた。
【0015】
本発明は、上記問題に鑑み案出されたもので、その目的は、絶縁基体がムライト質焼結体で形成され、かつ貫通導体層の露出面にめっき層を密着性良く形成することができるセラミック配線基板を提供することにある。
【0016】
【課題を解決するための手段】
本発明は、絶縁基体と、該絶縁基体内に形成され、一端が絶縁基体の表面に露出し、露出面に半導体素子の電極が電気的接続手段を介して接続される貫通導体層とから成るセラミック配線基板であって、前記絶縁基体はムライト質焼結体から成り、かつ前記貫通導体層はモリブデンを主成分とする金属材で形成されているとともに露出面がタングステンから成る、断面形状が中央部が厚く周辺部が薄い被覆層で被覆されていることを特徴とするものである。
【0017】
本発明のセラミック配線基板によれば、貫通導体層の露出面を酸化し難いタングステンから成る被覆層で被覆したことから、貫通導体層の露出表面に半田等のろう材に対して濡れ性が良いニッケル等のめっき層を確実、強固に被着させることができ、その結果、貫通導体層に電子部品の各電極を半田ボール等からなる電機的接続手段を介して強固に電気的に接続させることができる。
【0018】
また本発明のセラミック配線基板によれば、貫通導体層の全領域を、焼結開始温度が絶縁基体となるセラミックグリーンシートの焼結開始温度に近似するモリブデンを主成分とする金属材で形成したことから、絶縁基体と貫通導体層との間に大きな応力が発生することはなく、該応力によって絶縁基体にクラック等が発生することもない。
【0019】
【発明の実施の形態】
次に本発明を添付図面に基付き詳細に説明する。
図1及び図2は本発明のセラミック配線基板を半導体素子収納用パッケージの絶縁基体に適用した場合の一実施例を示し、図中、1はセラミック配線基板からなる絶縁基体、2は蓋体である。この絶縁基体1と蓋体2とで半導体素子を収容するための容器4が構成される。
【0020】
前記絶縁基体1は半導体素子3を支持する支持部材として作用し、上面の略中央部に半導体素子3が搭載実装される。
【0021】
前記絶縁基体1はムライト質焼結体から成り、該ムライト質焼結体は熱膨張係数が4.0×10-6/℃〜4.5×10-6/℃であり、半導体素子3を構成するシリコンの熱膨張係数(3.0×10-6/℃〜3.5×10-6/℃)に近似することから、絶縁基体1上に半導体素子3を搭載実装した後、両者に半導体素子3を作動させた際等に発生する熱が印加されたとしても両者間には大きな熱応力が発生することはなく、該熱応力によって半導体素子3が破損したり、半導体素子3が絶縁基体1より剥離したりすることはない。
【0022】
前記ムライト質焼結体から成る絶縁基体1は、例えば、ムライト、酸化カルシウム、酸化マグネシウム等の原料粉末に適当な有機バインダー、溶剤等を添加混合して泥漿物を作るとともに該泥漿物をドクターブレード法やカレンダーロール法を採用することによってセラミックグリーンシート(セラミック生シート)と成し、しかる後、前記セラミックグリーンシートに適当な打ち抜き加工を施すとともにこれを複数枚積層し、約1600℃の温度で焼成することによって製作される。
【0023】
また前記絶縁基体1はその上面で半導体素子3が搭載実装される領域から内部及び側面を介し底面にかけて複数の貫通導体層5が形成されており、該貫通導体層5のうち絶縁基体1の上面に露出する領域には半導体素子3の各電極が半田ボール等の電気的接続手段8を介して接続され、また絶縁基体1の下面に導出する部位には外部リード端子7が銀ロウ等のロウ材を介してロウ付けされている。
【0024】
前記貫通導体層5は、半導体素子3の各電極を外部電気回路に接続される外部リード端子7に接続するための導電路として作用し、半導体素子3の各電極を絶縁基体1の上面に露出する貫通導体層5の露出表面に半田ボール等の電気的接続手段8を介して接続すれば半導体素子3の各電極は貫通導体層5を介して絶縁基体1の下面において貫通導体層5にロウ付けされている外部リード端子7に電気的に接続され、外部リード端子7を外部電気回路に接続すれば半導体素子3の各電極は貫通導体層5及び外部リード端子7を介して外部電気回路に電気的に接続されることとなる。
【0025】
なお、前記貫通導体層5は絶縁基体1を形成するムライト質焼結体の誘電率が6.3(室温1MHz)と低いため、貫通導体層5における電気信号の伝播速度を速いものとなすことができ、これによって貫通導体層5を介して半導体素子3と外部電気回路との間で電気信号を高速で出し入れすることが可能となる。
【0026】
また前記貫通導体層5はモリブデンを主成分とする金属材で形成されているとともに露出面がタングステンから成る被覆層5aで被覆されており、かかる貫通導体層5及び被覆層5aは、例えば、まず、同じ位置に貫通孔が形成された焼成により絶縁基体1となる複数枚のセラミックグリーンシートを準備し、次に前記複数枚のセラミックグリーンシートの各貫通孔内に、モリブデン粉末を主成分とし、酸化アルミニウム、酸化マグネシウム等の粉末及び有機溶剤、溶媒を添加混合して得たモリブデンを主成分とする導電ペーストを印刷充填するとともに、これらのセラミックグリーンシートを上下に積層し、最後に貫通孔に印刷充填したモリブデンを主成分とする導電ペーストの露出面に、タングステン粉末に有機溶剤、溶媒を添加混合して得た導電ペーストをスクリーン印刷法により印刷塗布して被覆するとともにこれを高温で焼成することによって製作される。
【0027】
前記貫通導体層5はまたモリブデンを主成分とする金属材で形成されているとともに露出面が酸化し難いタングステンから成る被覆層5aで被覆されているため貫通導体層5及び被覆層5aの露出面に酸化物が形成されることはなく、被覆層5aの表面に後述する半田等のろう材に対して濡れ性が良いニッケルや金等のめっき層を確実、強固に被着させることができる。
【0028】
更に前記貫通導体層5は、その全領域が、絶縁基体1となるセラミックグリーンシートの焼結開始温度に近似した焼結開始温度を有するモリブデンを主成分とする金属材で形成されていることから絶縁基体1と貫通導体層5との間に大きな応力が発生することはなく、該応力によって絶縁基体1にクラック等が発生することもない。
【0029】
なお前記被覆層5aは、その厚さが1000μmを超える厚いものとなると、タングステン粉末の焼結体が硬く脆いことからカケやハガレ等の欠損を生じ易くなる傾向があり、また50μm未満の薄いものとなると被覆層5a内のピンホール(空孔)を介して貫通導体層5の露出表面が酸化しやすくなる傾向がある。従って、前記被覆層5aは、その厚みを50μm〜1000μmの範囲としておくことが好ましい。
【0030】
更に前記被覆層5aは、その断面形状を中央部が厚く周辺部が薄い、所謂、カマボコ状としてお、熱応力等の応力が周辺部、特に外周端部に集中することがなく、貫通導体層5に対する接合強度をより一層強いものとすることができる。従って、前記被覆層5aは、その断面形状をカマボコ状としておくこととする
【0031】
前記貫通導体層5の露出面を被覆している被覆層5aは更に図2に示す如く、その露出する表面にニッケルめっき層9や金めっき層10が被着されており、該ニッケルめっき層9や金めっき層10は半田ボール等から成る電気的接続手段8の貫通導体層5に対する濡れ性を改善し、貫通導体層5に半田ボール等から成る電気的接続手段8を強固に被着させる作用をなす。
【0032】
前記ニッケルめっき層9は、例えば、無電解めっき法によって形成され、具体的には、硫酸ニッケル20〜40グラム/リットル、コハク酸ナトリウム40〜60グラム/リットル、ホウ酸25〜35グラム/リットル、塩化アンモニウム25〜35グラム/リットル、ジメチルアミンボラン2.5〜4.5グラム/リットル等から成る無電解ニッケルめっき液を準備するとともに、貫通導体層5の露出面を脱脂、酸処理した後、触媒剤を含有する溶液に浸漬して活性処理をし、しかる後、貫通導体層5の露出面を60〜65℃に設定された前記無電解ニッケルめっき液中に30〜60分間浸漬させることによって貫通導体層5の露出面に所定厚み(2μm〜8μm)に被着され、また金めっき層10は、例えば、水酸化カリウム20〜40グラム/リットル、エチレンジアミン四酢酸30〜50グラム/リットル、リン酸二水素カリウム15〜45グラム/リットル、シアン化カリウム0.01〜0.1グラム/リットル、シアン化金カリウム1〜4グラム/リットル等から成る金めっき液(液温:85〜95℃)を準備し、これに前記表面にニッケルめっき層9が被着されている貫通導体層5の露出面を5〜15分間浸漬させることによってニッケルめっき層9上に所定厚み(0.02μm〜0.3μm)に被着される。
【0033】
前記ニッケルめっき層9はその厚みが2μm未満となると貫通導体層5の露出面に金めっき層10を強固に被着させるのが困難となる傾向にあり、また8μmを越えるとニッケルめっき層9を形成する際に大きな応力が発生するとともにこれがニッケルめっき層9の内部に内在し、該内在応力によって貫通導体層5の露出面とニッケルめっき層9との密着の信頼性が低下してしまう危険性がある。従って、前記ニッケルめっき層9はその厚みを2μm〜8μmの範囲としておくことが好ましい。
【0034】
また前記金めっき層10はその厚みが0.02μm未満となると下地のニッケルめっき層9を完全に被覆することができず、半田ボール等から成る電気的接続手段8の貫通導体層5に対する接合強度が低下してしまう危険性があり、また0.3μmを超えると金めっき層10の一部が半田ボール等から成る電気的接続手段8の内部に拡散して電気的接続手段8の機械的強度を低下させてしまう危険性がある。従って、前記金めっき層10はその厚みを0.02μm〜0.3μmの範囲としておくことが好ましい。
【0035】
更に前記ニッケルめっき層9はその表面の粗さを中心線平均粗さ(Ra)で0.5μm≦Ra≦1.5μmの範囲とし、表面を適度に粗しておくとニッケルめっき層9と金めっき層10との密着面積が広いものとして両者の密着強度を極めて強いものとなすことができる。従って、前記ニッケルめっき層9はその表面の粗さを中心線平均粗さ(Ra)で0.5μm≦Ra≦1.5μmの範囲に粗しておくことが好ましい。
【0036】
前記ニッケルめっき層9の表面を中心線平均粗さ(Ra)で0.5μm≦Ra≦1.5μmの範囲に粗す方法としては、ニッケルめっき層9の表面に#1500程度のメディアを2.0kg/cm2 〜4.0kg/cm2 の圧力で吹き付けする、所謂、ブラスト処理を施すことによって行われる。
【0037】
また一方、前記絶縁基体1の下面に導出されている貫通導体層5には外部リード端子7が銀ロウ等のロウ材を介して取着されており、該外部リード端子7は半導体素子3の各電極を外部電気回路に電気的に接続させる作用をなす。
【0038】
前記外部リード端子7は鉄−ニッケル−コバルト合金や鉄−ニッケル合金等の金属材料から成り、例えば、鉄−ニッケル−コバルト合金や鉄−ニッケル合金等のインゴット(塊)に圧延加工法や打ち抜き加工法等、従来周知の金属加工法を施すことによって所定の形状に形成される。
【0039】
また前記外部リード端子7はその露出する表面に良導電性で、かつ耐食性に優れるニッケル、金等の金属をめっき法により1μm〜20μmの厚みに被着させておくと、外部リード端子7の酸化腐食を有効に防止することができるとともに外部電気回路との接続を良好となすことができる。従って、前記外部リード端子7はその露出する表面にニッケル、金等をめっき法により1μm〜20μmの厚みに被着させておくことが好ましい。
【0040】
更に前記外部リード端子7が取着された絶縁基体1はその上面外周部に椀状をなす蓋体2がガラス、樹脂、ロウ材等から成る封止材を介して接合され、これによって絶縁基体1と蓋体2とから成る容器4内部に半導体素子3が気密に封止される。
【0041】
前記蓋体2は容器4の内部に半導体素子3を気密に収容する作用をなし、銅や鉄−ニッケル−コバルト合金や鉄−ニッケル−合金等の金属材料、あるいは酸化アルミニウム質焼結体等のセラミックス焼結体で形成されている。
【0042】
かくして上述の半導体素子収納用パッケージによれば、絶縁基体1上面に半導体素子3を、該半導体素子3の各電極を被覆層5aの表面に半田ボール等から成る電気的接続手段8を介して接続させることによって搭載実装し、しかる後、前記絶縁基体1の上面に椀状の蓋体2をガラス、樹脂、ロウ材等から成る封止材を介して接合させ、絶縁基体1と蓋体2とから成る容器4内部に半導体素子3を気密に収容することによって最終製品としての半導体装置となる。
【0043】
なお、本発明は上述した実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能であり、例えば、上述の実施例では本発明のセラミック配線基板を半導体素子を収容する半導体素子収納用パッケージに適用した場合を例に挙げて説明したが、これを半導体素子が搭載される混成集積回路基板に適用した場合であってもよい。
【0044】
【発明の効果】
本発明のセラミック配線基板によれば、絶縁基体をムライト質焼結体で形成したことから、半導体素子と絶縁基体との熱膨張係数が近似し、両者の熱膨張係数の差に起因する熱応力を小さく抑えて半導体装置としての機能を長期にわたって維持することが可能となり、かつ、絶縁基体の誘電率を約6.3と低いものとして信号の高速伝播を要求する半導体素子の搭載が可能となった。
【0045】
また、本発明のセラミック配線基板によれば、貫通導体層をモリブデンを主成分とする金属材で形成するとともに露出面を酸化し難いタングステンから成る被覆層で被覆したことから、貫通導体層を被覆する被覆層の表面に、半田等のろう材に対して濡れ性が良いニッケル等のめっき層を確実、強固に被着させることができ、その結果、貫通導体層に電子部品の各電極を半田ボール等から成る電気的接続手段を介して強固に電気的に接続させることが可能となった。
【0046】
更にまた、本発明のセラミック配線基板によれば、貫通導体層の全領域を、焼結開始温度が絶縁基体となるセラミックグリーンシートの焼結開始温度に近似するモリブデンを主成分とする金属材で形成したことから絶縁基体と貫通導体層との間に大きな応力が発生することはなく、該応力によって絶縁基体にクラック等が発生することもない。
【図面の簡単な説明】
【図1】本発明のセラミック配線基板を半導体素子収納用パッケージの絶縁基体に適用した場合の一実施例を示す断面図である。
【図2】図1の要部拡大断面図である。
【符号の説明】
1・・・絶縁基体
2・・・蓋体
3・・・半導体素子
5・・・貫通導体層
5a・・被覆層
7・・・外部リード端子
8・・・電気的接続手段
9・・・ニッケルめっき層
10・・金めっき層
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a ceramic wiring board used for a semiconductor element housing package for housing a semiconductor element, a hybrid integrated circuit board, and the like, and more particularly to a ceramic wiring board on which a semiconductor element is mounted and connected by a flip chip method. is there.
[0002]
[Prior art]
In recent years, a method for mounting a semiconductor element on a ceramic wiring board used for a package for housing a semiconductor element, a hybrid integrated circuit board, or the like is as follows. So-called flip chip bonding, in which an electrode of a semiconductor element is directly connected to a through conductor layer exposed on the surface via an electrical connection means such as solder, is being used frequently.
[0003]
A ceramic wiring board used for a semiconductor element storage package or a hybrid integrated circuit board that employs this flip-chip bonding is generally formed of an insulating base made of an aluminum oxide sintered body, and the insulating base. An electrode of an electronic component such as a semiconductor element is formed on the exposed surface of the penetrating conductor layer exposed on the surface of the insulating substrate. The penetrating conductor layer is made of a refractory metal such as tungsten or molybdenum that has one end exposed on the surface of the insulating substrate. Are connected to each other through an electrical connection means made of solder balls or the like, so that an electronic component such as a semiconductor element is mounted on the ceramic wiring board and each electrode of the electronic component is connected to the through conductor layer.
[0004]
The exposed surface of the through conductor layer is usually excellent in corrosion resistance of nickel, gold, etc. in order to prevent its oxidative corrosion and to improve the wettability with respect to the electrical connection means composed of solder balls or the like. In addition, a metal layer having good wettability with respect to a brazing material such as solder is applied by a plating method.
[0005]
Further, such a ceramic wiring board is generally manufactured by employing a ceramic layering technique and a thick film forming technique such as screen printing. Specifically, the ceramic wiring board is manufactured by the following method.
[0006]
That is,
(1) First, an organic solvent and a solvent are added to a ceramic raw material powder composed of aluminum oxide (Al 2 O 3 ), silicon oxide (SiO 2 ), magnesium oxide (MgO), calcium oxide (CaO), etc. Next, this is formed into a sheet shape by a conventionally known doctor blade method or calendar roll method to form a plurality of ceramic green sheets (ceramic green sheets) and through holes are formed at predetermined positions by punching or the like To do.
[0007]
(2) Next, a conductive paste obtained by adding and mixing an organic solvent and a solvent into a metal powder such as tungsten or molybdenum is printed and filled in the through hole by a screen printing method or the like.
[0008]
(3) Finally, these ceramic green sheets are stacked one above the other so that one end of the conductive paste printed and filled in the through holes is exposed, and fired at a temperature of about 1600 ° C. in a reducing atmosphere. A ceramic wiring board is completed by sintering and integrating the ceramic green sheet and the conductive paste.
[0009]
In this case, if the sintering start temperatures of the ceramic green sheet and the conductive paste are different, the contraction start time associated with the sintering is different between the ceramic green sheet and the conductive paste, and the insulation substrate and the through conductor layer are between. As a result, stress is generated and cracks and the like are generated in the insulating substrate, and therefore, a conductive paste whose sintering start temperature approximates the sintering start temperature of the ceramic green sheet is usually used.
[0010]
However, recently, the increase in the size of the semiconductor element and the increase in the signal propagation speed have rapidly advanced, and when the semiconductor element is mounted on the above-described conventional ceramic wiring board, it has the following drawbacks.
[0011]
That is,
(1) thermal expansion coefficient of the sintered aluminum oxide contained in the silicon and the insulating substrate of the semiconductor device, each 3.0 × 10 -6 /℃~3.5×10 -6 /℃,6.0 × a 10 -6 /℃~7.5×10 -6 / ℃, a large thermal stress between them when the heat generated is applied to the like when operated a semiconductor element on both since it differs greatly Due to the thermal stress, the electrical connection means such as solder balls and the semiconductor element are damaged or peeled off from the insulating substrate, thereby losing the function as the semiconductor device.
[0012]
(2) Since the dielectric constant of the aluminum oxide sintered body constituting the insulating base is as high as 9 to 10 (room temperature 1 MHz), the propagation speed of the signal transmitted through the through conductor layer provided on the insulating base is slow, and therefore the signal A semiconductor element requiring high-speed propagation cannot be mounted.
[0013]
Therefore in order to solve the above drawbacks, the thermal expansion coefficient of the silicon constituting the semiconductor device instead of the insulating substrate to the sintered aluminum oxide (3.0 × 10 -6 /℃~3.5×10 -6 / ° C.) and having a thermal expansion coefficient of 4.0 × 10 -6 /℃~4.5×10 -6 / ℃ approximated, and dielectric constant can be formed at a 6.3 low mullite sintered body Conceivable.
[0014]
[Problems to be solved by the invention]
However, when the insulating substrate is formed of a mullite sintered body, the conductive paste serving as the through conductor layer contains molybdenum as a main component in order to approximate the sintering start temperature of the ceramic green sheet serving as the mullite sintered body. When the through conductor layer is formed of this molybdenum, the molybdenum is a metal that is easily oxidized, and an oxide is very easily formed on the exposed surface. If an oxide is formed on the surface of the through conductor layer, a plated layer of nickel or the like cannot be formed on the exposed surface of the through conductor layer with good adhesion. As a result, each electrode of the electronic component is formed on the through conductor layer with solder balls or the like. There is a disadvantage that it cannot be firmly and electrically connected via the mechanical connection means.
[0015]
The present invention has been devised in view of the above problems, and an object of the present invention is to form an insulating substrate with a mullite sintered body and to form a plating layer on the exposed surface of the through conductor layer with good adhesion. It is to provide a ceramic wiring board.
[0016]
[Means for Solving the Problems]
The present invention comprises an insulating substrate, and a through conductor layer formed in the insulating substrate, one end of which is exposed on the surface of the insulating substrate, and an electrode of a semiconductor element is connected to the exposed surface via an electrical connection means. a ceramic wiring substrate, the insulating substrate is made of mullite sintered body, and together with the through conductor layer is formed of a metal material mainly composed of molybdenum, the exposed surface is made of tungsten, the cross-sectional shape The central part is thick and the peripheral part is covered with a thin coating layer.
[0017]
According to the ceramic wiring board of the present invention, since the exposed surface of the through conductor layer is coated with a coating layer made of tungsten that is difficult to oxidize, the exposed surface of the through conductor layer has good wettability with respect to a brazing material such as solder. A plated layer of nickel or the like can be reliably and firmly applied, and as a result, each electrode of the electronic component can be firmly and electrically connected to the through conductor layer via an electrical connection means such as a solder ball. Can do.
[0018]
Further, according to the ceramic wiring board of the present invention, the entire region of the through conductor layer is formed of a metal material whose main component is molybdenum whose sintering start temperature approximates the sintering start temperature of the ceramic green sheet serving as the insulating base. Therefore, no great stress is generated between the insulating base and the through conductor layer, and no crack or the like is generated in the insulating base due to the stress.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
The present invention will now be described in detail with reference to the accompanying drawings.
1 and 2 show an embodiment in which the ceramic wiring board of the present invention is applied to an insulating base of a package for housing a semiconductor element. In the figure, 1 is an insulating base made of a ceramic wiring board, and 2 is a lid. is there. The insulating substrate 1 and the lid body 2 constitute a container 4 for housing a semiconductor element.
[0020]
The insulating substrate 1 acts as a support member for supporting the semiconductor element 3, and the semiconductor element 3 is mounted and mounted at a substantially central portion of the upper surface.
[0021]
The insulating substrate 1 is made of mullite sintered body, it said mullite sintered material is the thermal expansion coefficient of 4.0 × 10 -6 /℃~4.5×10 -6 / ℃ , the semiconductor device 3 since that approximates the thermal expansion coefficient of silicon constituting (3.0 × 10 -6 /℃~3.5×10 -6 / ℃), after mounting a semiconductor element mounted 3 on an insulating substrate 1, to both Even if heat generated when the semiconductor element 3 is operated or the like is applied, no large thermal stress is generated between the two, and the semiconductor element 3 is damaged by the thermal stress or the semiconductor element 3 is insulated. There is no peeling from the substrate 1.
[0022]
The insulating substrate 1 made of the mullite sintered body is made of, for example, an appropriate organic binder, a solvent and the like added to a raw material powder such as mullite, calcium oxide, and magnesium oxide to form a slurry, and the slurry is a doctor blade. The ceramic green sheet (ceramic green sheet) is formed by adopting the method and the calender roll method. After that, the ceramic green sheet is appropriately punched and laminated, and the temperature is about 1600 ° C. Manufactured by firing.
[0023]
The insulating base 1 has a plurality of through conductor layers 5 formed on the upper surface thereof from the region where the semiconductor element 3 is mounted and mounted to the bottom surface through the inside and side surfaces. Each electrode of the semiconductor element 3 is connected to the exposed area via an electrical connection means 8 such as a solder ball, and the external lead terminal 7 is connected to a solder lead or the like on the lower surface of the insulating substrate 1. It is brazed through the material.
[0024]
The through conductor layer 5 acts as a conductive path for connecting each electrode of the semiconductor element 3 to an external lead terminal 7 connected to an external electric circuit, and exposes each electrode of the semiconductor element 3 on the upper surface of the insulating substrate 1. Each electrode of the semiconductor element 3 is connected to the through conductor layer 5 on the lower surface of the insulating substrate 1 through the through conductor layer 5 if it is connected to the exposed surface of the through conductor layer 5 through the electrical connection means 8 such as a solder ball. When the external lead terminal 7 is electrically connected to the attached external lead terminal 7 and the external lead terminal 7 is connected to the external electrical circuit, each electrode of the semiconductor element 3 is connected to the external electrical circuit via the through conductor layer 5 and the external lead terminal 7. It will be electrically connected.
[0025]
In addition, since the through conductor layer 5 has a low dielectric constant of 6.3 (room temperature 1 MHz) of the mullite sintered body forming the insulating substrate 1, the propagation speed of the electric signal in the through conductor layer 5 is increased. As a result, an electric signal can be input / output between the semiconductor element 3 and the external electric circuit through the through conductor layer 5 at a high speed.
[0026]
The through conductor layer 5 is formed of a metal material mainly composed of molybdenum, and the exposed surface is covered with a coating layer 5a made of tungsten. The through conductor layer 5 and the coating layer 5a are, for example, Preparing a plurality of ceramic green sheets to be the insulating base 1 by firing with through holes formed at the same position, and then, in each through hole of the plurality of ceramic green sheets, with molybdenum powder as a main component, Printed and filled with conductive paste mainly composed of molybdenum obtained by adding powder and organic solvent and solvent such as aluminum oxide and magnesium oxide, and laminating these ceramic green sheets up and down, and finally into the through hole Add organic solvent and solvent to tungsten powder and mix on the exposed surface of the conductive paste mainly composed of printed molybdenum. With resulting conductive paste is coated by printing applied by screen printing is produced by firing the high temperature.
[0027]
The through conductor layer 5 is also formed of a metal material mainly composed of molybdenum, and the exposed surface is covered with a coating layer 5a made of tungsten, which is difficult to oxidize. Therefore, the exposed surface of the through conductor layer 5 and the coating layer 5a No oxide is formed on the surface of the coating layer 5a, and a plated layer such as nickel or gold having good wettability with respect to a brazing material such as solder, which will be described later, can be reliably and firmly deposited on the surface of the coating layer 5a.
[0028]
Further, the through conductor layer 5 is entirely formed of a metal material mainly composed of molybdenum having a sintering start temperature approximate to the sintering start temperature of the ceramic green sheet to be the insulating base 1. A large stress is not generated between the insulating substrate 1 and the through conductor layer 5, and a crack or the like is not generated in the insulating substrate 1 due to the stress.
[0029]
If the thickness of the coating layer 5a is greater than 1000 μm, the tungsten powder sintered body is hard and brittle and tends to cause defects such as chipping and peeling, and is thin and less than 50 μm. Then, the exposed surface of the through conductor layer 5 tends to be oxidized through the pinhole (hole) in the coating layer 5a. Therefore, the coating layer 5a preferably has a thickness in the range of 50 μm to 1000 μm.
[0030]
Further, the coating layer 5a, the cross-sectional shape is thin peripheral portion thicker center portion, so-called Ri it as semicylindrical shape, stress periphery of such thermal stress, without having to particularly concentrate on the outer peripheral edge, through conductors The bonding strength to the layer 5 can be made even stronger. Therefore, the coating layer 5a, it is assumed that to keep the cross-sectional shape as the hog-backed shape.
[0031]
As shown in FIG. 2, the covering layer 5a covering the exposed surface of the through conductor layer 5 is further coated with a nickel plating layer 9 or a gold plating layer 10 on the exposed surface. The metal plating layer 10 improves the wettability of the electrical connection means 8 made of solder balls or the like with respect to the through conductor layer 5 and firmly attaches the electrical connection means 8 made of solder balls or the like to the through conductor layer 5. Make.
[0032]
The nickel plating layer 9 is formed by, for example, an electroless plating method. Specifically, nickel sulfate 20 to 40 g / liter, sodium succinate 40 to 60 g / liter, boric acid 25 to 35 g / liter, After preparing an electroless nickel plating solution composed of ammonium chloride 25-35 g / liter, dimethylamine borane 2.5-4.5 g / liter, and the like, the exposed surface of the through conductor layer 5 is degreased and acid-treated, By immersing in a solution containing a catalyst agent to perform an activation treatment, and then immersing the exposed surface of the through conductor layer 5 in the electroless nickel plating solution set at 60 to 65 ° C. for 30 to 60 minutes. The exposed surface of the through conductor layer 5 is deposited to a predetermined thickness (2 μm to 8 μm), and the gold plating layer 10 is, for example, 20 to 40 g potassium hydroxide. From ram / liter, ethylenediaminetetraacetic acid 30-50 gram / liter, potassium dihydrogen phosphate 15-45 gram / liter, potassium cyanide 0.01-0.1 gram / liter, potassium gold cyanide 1-4 gram / liter, etc. A gold plating solution (liquid temperature: 85 to 95 ° C.) is prepared, and nickel plating is performed by immersing the exposed surface of the through conductor layer 5 on which the nickel plating layer 9 is deposited on the surface for 5 to 15 minutes. A predetermined thickness (0.02 μm to 0.3 μm) is deposited on the layer 9.
[0033]
When the thickness of the nickel plating layer 9 is less than 2 μm, it tends to be difficult to firmly adhere the gold plating layer 10 to the exposed surface of the through conductor layer 5, and when the thickness exceeds 8 μm, the nickel plating layer 9 is formed. There is a risk that a large stress is generated during the formation and this is inherent in the nickel plating layer 9, and the reliability of the adhesion between the exposed surface of the through conductor layer 5 and the nickel plating layer 9 decreases due to the internal stress. There is. Therefore, the nickel plating layer 9 preferably has a thickness in the range of 2 μm to 8 μm.
[0034]
Further, when the thickness of the gold plating layer 10 is less than 0.02 μm, the underlying nickel plating layer 9 cannot be completely covered, and the bonding strength of the electrical connection means 8 made of solder balls or the like to the through conductor layer 5. Further, when the thickness exceeds 0.3 μm, a part of the gold plating layer 10 diffuses into the electrical connection means 8 made of solder balls or the like, and the mechanical strength of the electrical connection means 8 is increased. There is a risk of lowering. Therefore, it is preferable that the gold plating layer 10 has a thickness in the range of 0.02 μm to 0.3 μm.
[0035]
Furthermore, the nickel plating layer 9 has a surface roughness in the range of 0.5 μm ≦ Ra ≦ 1.5 μm in terms of centerline average roughness (Ra). Since the adhesion area with the plating layer 10 is wide, the adhesion strength between them can be made extremely strong. Therefore, it is preferable that the surface of the nickel plating layer 9 is roughened in the range of 0.5 μm ≦ Ra ≦ 1.5 μm in terms of centerline average roughness (Ra).
[0036]
As a method of roughening the surface of the nickel plating layer 9 in the range of 0.5 μm ≦ Ra ≦ 1.5 μm in terms of center line average roughness (Ra), a medium of about # 1500 is applied to the surface of the nickel plating layer 9. to spray at a pressure of 0kg / cm 2 ~4.0kg / cm 2 , it is carried out by so-called blasting performed.
[0037]
On the other hand, an external lead terminal 7 is attached to the through conductor layer 5 led out on the lower surface of the insulating base 1 via a brazing material such as silver solder, and the external lead terminal 7 is connected to the semiconductor element 3. Each electrode is electrically connected to an external electric circuit.
[0038]
The external lead terminal 7 is made of a metal material such as iron-nickel-cobalt alloy or iron-nickel alloy. For example, an ingot (lumb) such as iron-nickel-cobalt alloy or iron-nickel alloy is rolled or punched. It is formed in a predetermined shape by applying a conventionally known metal processing method such as a method.
[0039]
The external lead terminal 7 is oxidized when the exposed surface is coated with a metal such as nickel or gold having good conductivity and corrosion resistance to a thickness of 1 μm to 20 μm by plating. Corrosion can be effectively prevented and connection with an external electric circuit can be made good. Therefore, it is preferable that nickel, gold or the like is deposited on the exposed surface of the external lead terminal 7 to a thickness of 1 μm to 20 μm by plating.
[0040]
Further, the insulating base 1 to which the external lead terminals 7 are attached is joined with a lid 2 having a bowl shape on the outer periphery of the upper surface via a sealing material made of glass, resin, brazing material, etc. The semiconductor element 3 is hermetically sealed inside the container 4 composed of 1 and the lid 2.
[0041]
The lid 2 has a function of hermetically housing the semiconductor element 3 in the container 4, and is made of a metal material such as copper, iron-nickel-cobalt alloy, iron-nickel-alloy, or an aluminum oxide sintered body. It is formed of a ceramic sintered body.
[0042]
Thus, according to the package for housing a semiconductor element described above, the semiconductor element 3 is connected to the upper surface of the insulating base 1, and each electrode of the semiconductor element 3 is connected to the surface of the coating layer 5a via the electrical connection means 8 made of solder balls or the like. After that, a lid-like lid 2 is joined to the upper surface of the insulating base 1 via a sealing material made of glass, resin, brazing material, etc., and the insulating base 1 and the lid 2 A semiconductor device as a final product is obtained by airtightly housing the semiconductor element 3 in the container 4 made of
[0043]
The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. For example, in the above-described embodiments, the ceramic wiring board of the present invention can be changed. Although the case where the present invention is applied to a semiconductor element housing package for housing semiconductor elements has been described as an example, it may be applied to a hybrid integrated circuit board on which semiconductor elements are mounted.
[0044]
【The invention's effect】
According to the ceramic wiring board of the present invention, since the insulating base is formed of a mullite sintered body, the thermal expansion coefficients of the semiconductor element and the insulating base approximate to each other, and the thermal stress caused by the difference between the thermal expansion coefficients of the two. It is possible to maintain the function as a semiconductor device for a long period of time while keeping the dielectric constant small, and it is possible to mount a semiconductor element that requires high-speed signal propagation as the dielectric constant of the insulating base is as low as about 6.3. It was.
[0045]
In addition, according to the ceramic wiring board of the present invention, the through conductor layer is formed of a metal material mainly composed of molybdenum, and the exposed surface is covered with a coating layer made of tungsten that is difficult to oxidize. On the surface of the coating layer to be applied, a plating layer of nickel or the like having good wettability with respect to the soldering material such as solder can be reliably and firmly applied. As a result, each electrode of the electronic component is soldered to the through conductor layer. It has become possible to make a strong electrical connection through electrical connection means such as balls.
[0046]
Furthermore, according to the ceramic wiring board of the present invention, the entire region of the through conductor layer is made of a metal material mainly composed of molybdenum whose sintering start temperature approximates the sintering start temperature of the ceramic green sheet serving as the insulating base. Since it is formed, a large stress is not generated between the insulating base and the through conductor layer, and a crack or the like is not generated in the insulating base due to the stress.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an embodiment in which the ceramic wiring board of the present invention is applied to an insulating substrate of a package for housing semiconductor elements.
FIG. 2 is an enlarged cross-sectional view of a main part of FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Insulation base | substrate 2 ... Cover body 3 ... Semiconductor element 5 ... Penetration conductor layer 5a ... Cover layer 7 ... External lead terminal 8 ... Electrical connection means 9 ... Nickel Plating layer 10 ・ ・ Gold plating layer

Claims (1)

絶縁基体と、該絶縁基体内に形成され、一端が絶縁基体の表面に露出し、露出面に半導体素子の電極が電気的接続手段を介して接続される貫通導体層とから成るセラミック配線基板であって、前記絶縁基体はムライト質焼結体から成り、かつ前記貫通導体層はモリブデンを主成分とする金属材で形成されているとともに露出面がタングステンから成る、断面形状が中央部が厚く周辺部が薄い被覆層で被覆されていることを特徴とするセラミック配線基板。A ceramic wiring board comprising an insulating base, a through conductor layer formed in the insulating base, one end of which is exposed on the surface of the insulating base, and an electrode of the semiconductor element is connected to the exposed surface through an electrical connection means. there, the insulating substrate is made of mullite sintered body, and together with the through conductor layer is formed of a metal material mainly composed of molybdenum, the exposed surface is made of tungsten, the cross-sectional shape thicker central portion A ceramic wiring board characterized in that a peripheral portion is covered with a thin covering layer.
JP13478299A 1999-05-14 1999-05-14 Ceramic wiring board Expired - Fee Related JP3645744B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13478299A JP3645744B2 (en) 1999-05-14 1999-05-14 Ceramic wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13478299A JP3645744B2 (en) 1999-05-14 1999-05-14 Ceramic wiring board

Publications (2)

Publication Number Publication Date
JP2000323622A JP2000323622A (en) 2000-11-24
JP3645744B2 true JP3645744B2 (en) 2005-05-11

Family

ID=15136437

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13478299A Expired - Fee Related JP3645744B2 (en) 1999-05-14 1999-05-14 Ceramic wiring board

Country Status (1)

Country Link
JP (1) JP3645744B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114026968B (en) 2019-12-26 2022-08-30 Ngk电子器件株式会社 Wiring board

Also Published As

Publication number Publication date
JP2000323622A (en) 2000-11-24

Similar Documents

Publication Publication Date Title
JP3645744B2 (en) Ceramic wiring board
JP2009224651A (en) Wiring board and manufacturing process therefor
JP3495773B2 (en) Circuit board
JP3583018B2 (en) Ceramic wiring board
JP2000286353A (en) Semiconductor device housing package
JP3420469B2 (en) Wiring board
JP2001185838A (en) Ceramic wiring board
JP3987649B2 (en) Package for storing semiconductor elements
JP4683768B2 (en) Wiring board
JP3808376B2 (en) Wiring board
JP4105928B2 (en) Wiring board with lead pins
JP2003234552A (en) Wiring board
JP4191860B2 (en) Ceramic circuit board
JP2000244087A (en) Wiring board
JP2003007923A (en) Wiring board
JP4364033B2 (en) Wiring board with lead pins
JP3740407B2 (en) Wiring board
JP2004140103A (en) Wiring board
JP2746813B2 (en) Package for storing semiconductor elements
JP4109391B2 (en) Wiring board
JP2002217336A (en) Wiring board
JPH0794839A (en) Circuit board
JPH08125098A (en) Semiconductor device and manufacture thereof
JP2690643B2 (en) Wiring board
JP2842707B2 (en) Circuit board

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20040708

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040810

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20041007

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20050125

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20050204

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees