JP2001185838A - Ceramic wiring board - Google Patents

Ceramic wiring board

Info

Publication number
JP2001185838A
JP2001185838A JP36501999A JP36501999A JP2001185838A JP 2001185838 A JP2001185838 A JP 2001185838A JP 36501999 A JP36501999 A JP 36501999A JP 36501999 A JP36501999 A JP 36501999A JP 2001185838 A JP2001185838 A JP 2001185838A
Authority
JP
Japan
Prior art keywords
wiring
wiring conductor
conductor
plating layer
ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP36501999A
Other languages
Japanese (ja)
Inventor
Yasuhiro Sasaki
康博 佐々木
Masaji Imabetsupu
正次 今別府
Shinya Terao
慎也 寺尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP36501999A priority Critical patent/JP2001185838A/en
Publication of JP2001185838A publication Critical patent/JP2001185838A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a ceramic wiring board which is improved in adhesion with the wiring conductor of a metal plated layer and eliminates bulging or the like of the metal plated layer, when an electronic component or the like is mounted on the surface of the wiring conductor formed with the metal plated layer by soldering. SOLUTION: A wiring conductor 2 with Cu or Al as the main conductor is attached and formed on the surface of a ceramic insulated substrate 1, the surface of the wiring conductor 2 is coated and formed with a metal plated layer 3 composed of a metal such as Ni improved in solder wetting, and an electronic component 7 is mounted on this metal plated layer 3 with solder 6. Concerning such a wiring board, the average centerline roughness (Ra) of the wiring conductor 2 coated and formed with the metal plated layer 3 is 1 to 3 μm and the thickness of the metal plated layer 3 is 1 to 4 μm.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子が収容
搭載される半導体素子収納用パッケージや、表面に半導
体素子の他に、コンデンサや抵抗体等の電子部品が搭載
される混成集積回路基板や、パワーモジュール基板等と
して用いられるセラミック絶縁基板の表面に配線導体を
有する配線基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device housing package in which a semiconductor device is housed and mounted, a hybrid integrated circuit board on which electronic components such as a capacitor and a resistor are mounted in addition to the semiconductor device on the surface. The present invention relates to a wiring substrate having a wiring conductor on a surface of a ceramic insulating substrate used as a power module substrate or the like.

【0002】[0002]

【従来の技術】従来、半導体素子収納用パッケージや混
成集積回路基板等に用いられる多層配線基板は、一般に
アルミナ質焼結体等の電気絶縁性のセラミック焼結体か
ら成る絶縁基板を用い、その上面の略中央部に設けた凹
部周辺から下面に、あるいはその内部及び表面に、タン
グステン(W)、モリブデン(Mo)、マンガン(M
n)等の高融点金属から成る複数の配線導体を配設する
と共に、各配線導体を絶縁基板内に設けた前記同様の高
融点金属から成るビアホール導体で接続した構造を成し
ている。さらに低抵抗配線が必要となる回路には、表層
にCuペーストを印刷し、融点より低い温度で焼成しC
uからなる配線導体を形成する。
2. Description of the Related Art Conventionally, a multilayer wiring board used for a package for housing a semiconductor element, a hybrid integrated circuit board or the like generally uses an insulating board made of an electrically insulating ceramic sintered body such as an alumina sintered body. Tungsten (W), molybdenum (Mo), manganese (M) are formed from the periphery of the concave portion provided in the approximate center of the upper surface to the lower surface, or inside and on the surface.
n) and a plurality of wiring conductors made of a high melting point metal are arranged, and each wiring conductor is connected to a via hole conductor made of the same high melting point metal provided in the insulating substrate. For circuits requiring low-resistance wiring, print a Cu paste on the surface layer and bake at a temperature lower than the melting point.
A wiring conductor made of u is formed.

【0003】また、セラミック絶縁基板がガラスセラミ
ックス等、焼成温度が1000℃前後の場合、内層配
線、表層配線共に、未焼成のシート成形体表面にCuペ
ーストによって配線パターンを印刷形成し、絶縁基板と
同時焼成して形成することが行なわれている。
If the ceramic insulating substrate is made of glass ceramic or the like and the firing temperature is around 1000 ° C., a wiring pattern is printed and formed on the surface of the unsintered sheet compact with Cu paste for both the inner wiring and the surface wiring. It is performed by simultaneous firing.

【0004】また、高熱伝導性が要求されるパワーモジ
ュール基板等では、絶縁基板の表面にCu板やAl板な
どの高熱伝導性導体板を銀ろう系、Alろう系等のろう
材を用いて接着して配線導体を形成することも行なわれ
ている。
On the other hand, in the case of a power module substrate or the like that requires high thermal conductivity, a high thermal conductive conductor plate such as a Cu plate or an Al plate is formed on the surface of an insulating substrate by using a brazing material such as a silver brazing alloy or an Al brazing alloy. It is also performed to form a wiring conductor by bonding.

【0005】また、上記のような各種セラミック配線基
板における配線導体の表面に種々の電子部品を実装搭載
する場合には、配線導体表面に、半田との濡れ性に優れ
た金属層をめっき等により形成して、そのめっき層上に
各種電子部品を半田によって実装される。
In the case where various electronic components are mounted on the surface of the wiring conductor in the above various ceramic wiring boards, a metal layer having excellent wettability with solder is formed on the surface of the wiring conductor by plating or the like. After that, various electronic components are mounted on the plating layer by soldering.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、配線導
体に半田濡れ性の優れた金属層をめっきで形成しただけ
では、電子部品実装等の熱処理を行った際に、めっき層
と配線導体との接合強度が弱くなったり、まためっき膨
れが発生して、接合強度、半田濡れ性に悪影響を及ぼす
ため、電子部品等の電気的接続や熱伝導性が悪化すると
いう問題があった。特に、半田との濡れ性を改善し半田
等にボイド等の発生を抑制するためにメッキ層の厚みを
1μm以上とする場合、特に顕著であった。
However, if only a metal layer having excellent solder wettability is formed on a wiring conductor by plating, the bonding between the plating layer and the wiring conductor may be caused when heat treatment such as electronic component mounting is performed. Since the strength is weakened and plating swelling occurs, which adversely affects the bonding strength and solder wettability, there has been a problem that electrical connection and thermal conductivity of electronic components and the like are deteriorated. In particular, when the thickness of the plating layer was set to 1 μm or more in order to improve the wettability with the solder and to suppress the occurrence of voids and the like in the solder and the like, it was particularly remarkable.

【0007】従って、本発明は、前記課題を解消せんと
して成されたもので、その目的は、めっき層が形成され
た配線導体の表面に電子部品等を半田実装した際に、め
っき層の配線導体と密着性に優れ、めっき層の膨れ等の
ない、電気的接続や熱伝導性が良好なセラミック配線基
板を提供することにある。
SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problem, and an object of the present invention is to provide a method for wiring a plating layer when an electronic component or the like is solder-mounted on a surface of a wiring conductor on which the plating layer is formed. An object of the present invention is to provide a ceramic wiring board which has excellent adhesion to a conductor, has no swelling of a plating layer, and has good electrical connection and thermal conductivity.

【0008】[0008]

【課題を解決するための手段】本発明によれば、セラミ
ック絶縁基板の表面に、CuまたはAlを主導体とする
配線導体が被着形成され、該配線導体の表面に半田濡れ
性に優れた金属からなるめっき層を被覆形成してなり、
このめっき層上に半田によって電子部品が実装搭載され
るセラミック配線基板において、前記めっき層を被覆形
成する前記配線導体の中心線平均粗さ(Ra)を1〜3
μm、めっき層の厚みを1〜4μmとすることによっ
て、めっき層の配線導体への密着性が高まり、上記の目
的が達成されることを見いだした。
According to the present invention, a wiring conductor having Cu or Al as a main conductor is formed on the surface of a ceramic insulating substrate, and the surface of the wiring conductor has excellent solder wettability. It is formed by coating a metal plating layer,
In a ceramic wiring board on which an electronic component is mounted and mounted on the plating layer by soldering, the center line average roughness (Ra) of the wiring conductor that covers and forms the plating layer is 1 to 3.
It has been found that by setting the thickness of the plating layer to 1 to 4 μm, the adhesion of the plating layer to the wiring conductor is increased, and the above object is achieved.

【0009】なお、かかる配線基板においては、前記半
田濡れ性に優れた金属として、Niを用いることがのぞ
ましく、さらに、セラミック絶縁基板としては、Al2
3、AlN、Si34の群から選ばれる少なくとも1
種を主体とするセラミックスからなることがのぞまし
い。
[0009] Incidentally, in such a wiring board, as an excellent metal to the solder wettability, it is desirable to use Ni, further, as a ceramic insulating substrate, Al 2
At least one selected from the group consisting of O 3 , AlN, and Si 3 N 4
It is desirable that it be composed of seed-based ceramics.

【0010】[0010]

【発明の実施の形態】以下、本発明のセラミック配線基
板を図面に基づき詳細に説明する。図1は、本発明のセ
ラミック配線基板の一例である多層配線基板の概略断面
図であり、図2、基板表面の配線導体表面に電子部品を
実装した時の要部拡大断面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a ceramic wiring board according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic cross-sectional view of a multilayer wiring board as an example of the ceramic wiring board of the present invention, and FIG. 2 is an enlarged cross-sectional view of a main part when an electronic component is mounted on a wiring conductor surface on the board surface.

【0011】図1の多層配線基板は、複数のセラミック
絶縁層1a〜1dが積層された絶縁基板1の表面に、C
u又はAlを主導体とする配線導体2が設けられ、この
配線導体2の電子部品が実装される部分には半田濡れ性
の優れた金属からなるめっき層3が形成されている。ま
た、この配線導体2は、絶縁基板1の内部に形成された
ビアホール導体4あるいは内部配線導体5を経由して、
絶縁基板1の他方の表面に導出されている。そして、こ
のめっき層3の表面には、半田6によって半導体素子、
コンデンサ素子、抵抗素子、パワーMOSFETなどの
パワー素子などの電子部品7が実装されている。
The multilayer wiring board shown in FIG. 1 has a structure in which a plurality of ceramic insulating layers 1a to 1d are laminated on a surface of an insulating substrate 1.
A wiring conductor 2 having u or Al as a main conductor is provided, and a plating layer 3 made of a metal having excellent solder wettability is formed on a portion of the wiring conductor 2 where electronic components are mounted. The wiring conductor 2 is formed via the via-hole conductor 4 or the internal wiring conductor 5 formed inside the insulating substrate 1.
It is led to the other surface of the insulating substrate 1. Then, a semiconductor element,
Electronic components 7 such as a capacitor element, a resistance element, and a power element such as a power MOSFET are mounted.

【0012】本発明によれば、かかる配線基板におい
て、配線導体2のめっき層3を形成する表面を、中心線
平均粗さ(Ra)(以下、単に表面粗さというう場合も
ある。)で1〜3μmに粗面化することによって、めっ
き層3と配線導体2との接合面積を広くすることができ
る結果、めっき層3の金属が配線導体2表面へのアンカ
ー効果による物理的結合によって、反応等による化学結
合の電気特性の劣化を伴わず、接合強度を強固にするこ
とができる。
According to the present invention, in such a wiring board, the surface of the wiring conductor 2 on which the plating layer 3 is formed has a center line average roughness (Ra) (hereinafter sometimes simply referred to as surface roughness). By roughening the surface to 1 to 3 μm, the bonding area between the plating layer 3 and the wiring conductor 2 can be increased. As a result, the metal of the plating layer 3 is physically bonded to the surface of the wiring conductor 2 by an anchor effect. The joining strength can be increased without deteriorating the electrical characteristics of the chemical bond due to a reaction or the like.

【0013】中心線平均粗さ(Ra)を上記の範囲に限
定したのは、前記Raが1μmより小さいと接合強度の
向上効果が十分でなく、またRaが3μmよりも大きい
と、配線導体2表面にめっき層3を均一に形成すること
ができず、めっき層3の半田濡れ性が悪化して、電子部
品7をめっき層3表面に半田実装した際に、半田6内部
に空隙(ボイド)が発生し、半田実装の信頼性が低下す
るためである。また、めっき層を均一に形成する上では
Rmaxは8〜30μmであることが望ましく、Rma
xが8μmよりも小さいと接着性が不十分であり、30
μmを超えるとめっき層が均一に形成することが難しく
なる。
The reason why the center line average roughness (Ra) is limited to the above range is that if the Ra is less than 1 μm, the effect of improving the bonding strength is not sufficient, and if the Ra is more than 3 μm, the wiring conductor 2 The plating layer 3 cannot be formed uniformly on the surface, and the solder wettability of the plating layer 3 deteriorates. When the electronic component 7 is mounted on the surface of the plating layer 3 by soldering, a void is formed inside the solder 6. This causes the reliability of solder mounting to decrease. Further, in order to form the plating layer uniformly, it is desirable that Rmax is 8 to 30 μm.
If x is less than 8 μm, the adhesion is insufficient, and 30
If it exceeds μm, it becomes difficult to form a plating layer uniformly.

【0014】なお、このめっき層3が形成される配線導
体2表面の中心線表面粗さ(Ra)は、めっき層3と配
線導体2との断面の観察から、めっき層3と配線導体2
との界面ラインを求め、界面ラインの凹凸から求めるこ
とができる。
The center line surface roughness (Ra) of the surface of the wiring conductor 2 on which the plating layer 3 is formed is determined by observing the cross section of the plating layer 3 and the wiring conductor 2.
Can be determined from the unevenness of the interface line.

【0015】また、本発明によれば、めっき層3の厚み
は1〜4μm、特に2〜3μmであることが重要であ
り、1μm以上にすることにより、半田濡れ性に優れ接
合強度が向上し、4μm以下とすることによってめっき
膨れを小さくすることができる。
According to the present invention, it is important that the thickness of the plating layer 3 is 1 to 4 μm, especially 2 to 3 μm. By setting the thickness to 1 μm or more, the solder wettability is excellent and the bonding strength is improved. When the thickness is 4 μm or less, plating swelling can be reduced.

【0016】また、配線導体2上にめっき層3として形
成される半田濡れ性に優れた金属としては、Cu、N
i、Snの群から選ばれる少なくとも1種が用いられる
が、めっきプロセスの安易性でNiが最も望ましい。
The metal having excellent solder wettability formed as the plating layer 3 on the wiring conductor 2 includes Cu, N
At least one selected from the group consisting of i and Sn is used, but Ni is most preferable because of easiness of the plating process.

【0017】また、前記絶縁基板は、一般に多層配線基
板に適用されるアルミナ(Al23)や窒化アルミニウ
ム(AlN)、窒化珪素(Si34)等を主成分とする
セラミック焼結体であればいずれにも適用できるが、高
熱伝導性が要求されるパワーモジュール基板ではAlN
が望ましい。多層配線基板なら、とりわけアルミナ質焼
結体から成るものが望ましい。
The insulating substrate is a ceramic sintered body mainly composed of alumina (Al 2 O 3 ), aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), etc., which is generally used for a multilayer wiring board. Can be applied to any of them. However, in a power module substrate requiring high thermal conductivity, AlN
Is desirable. In the case of a multilayer wiring board, it is particularly desirable to use a board made of an alumina sintered body.

【0018】例えば、アルミナセラミックスを絶縁基板
とする配線基板は、アルミナ(Al 23)粉末に、シリ
カ(SiO2)、マグネシア(MgO)、カルシア(C
aO)等の原料粉末に周知の有機性バインダーと有機溶
剤、可塑剤、分散剤等を添加混合して調製した泥漿を、
周知のドクターブレード法やカレンダーロール法等のシ
ート成形法によりセラミックグリーンシートを作成す
る。そして、適宜、このグリーンシートにビアホールを
形成後、導体ペーストを充填したり、グリーンシート表
面に導体ペーストをメタライズ配線パターンにスクリー
ン印刷した後、それらを複数枚積層し、約1500〜1
700℃の温度で焼成することにより得られる。
For example, an alumina ceramic is used as an insulating substrate.
The wiring substrate is made of alumina (Al TwoOThree) To powder,
Mosquito (SiOTwo), Magnesia (MgO), calcia (C
aO) and other raw material powders with known organic binders and organic solvents
Agent, plasticizer, slurry prepared by adding and mixing a dispersant, etc.,
Well-known systems such as the doctor blade method and calendar roll method
Making ceramic green sheets by sheet molding
You. And, if necessary, add a via hole to this green sheet.
After forming, fill with conductive paste or use green sheet
Conductor paste on the surface to metallized wiring pattern
After printing, a plurality of them are laminated, and
It is obtained by firing at a temperature of 700 ° C.

【0019】AlNセラミックスを絶縁基板とする配線
基板は、AlN粉末に、Y23などの周期律表第3a族
酸化物、CaOなどのアルカリ土類金属酸化物などの焼
結助剤を添加し、上記と同様にして調製した泥漿を用い
てグリーンシートを作成し、適宜ビアホール導体やメタ
ライズ配線パターンを形成し、1600〜1850℃で
焼成することにより得られる。
In a wiring board using AlN ceramics as an insulating substrate, a sintering aid such as an oxide of Group 3a of the periodic table such as Y 2 O 3 or an alkaline earth metal oxide such as CaO is added to AlN powder. Then, a green sheet is prepared using the slurry prepared in the same manner as described above, and a via-hole conductor or a metallized wiring pattern is appropriately formed, followed by firing at 1600 to 1850 ° C.

【0020】また、窒化珪素セラミックスを絶縁基板と
する配線基板は、Si34粉末に、Y23などの周期律
表第3a族酸化物、MgOなどのアルカリ土類金属酸化
物、Al23、SiO2などの焼結助剤を添加し、この
混合物をプレス成形、あるいは上記と同様にして調製し
た泥漿を用いてグリーンシートを作製し、適宜ビアホー
ル導体やメタライズ配線パターンを形成し、1600〜
1950℃で焼成することにより得られる。
In addition, a wiring board using silicon nitride ceramics as an insulating substrate is made by adding Si 3 N 4 powder to a Group 3a oxide of the periodic table such as Y 2 O 3 , an alkaline earth metal oxide such as MgO, Al A sintering aid such as 2 O 3 or SiO 2 is added, and the mixture is press-molded, or a green sheet is prepared using a slurry prepared in the same manner as described above, and a via-hole conductor or a metallized wiring pattern is formed as appropriate. , 1600-
It is obtained by firing at 1950 ° C.

【0021】また、ビアホール導体はタングステン
(W)やモリブデン(Mo)、レニウム(Re)、コバ
ルト(Co)の群から選ばれる少なくとも1種の高融点
金属を主成分とするものが挙げられ、特に絶縁基板との
熱膨張率の整合性及びコストの点からはW,Moが好適
である。また、このビアホール導体は、表面実装された
パワーMOSFET等からの発熱性電子部品から発生す
る熱を熱伝導により反対側の表面に形成された配線導体
2と接続することで、ヒートシンクの効果を奏すること
もできる。
The via-hole conductor is mainly composed of at least one refractory metal selected from the group consisting of tungsten (W), molybdenum (Mo), rhenium (Re), and cobalt (Co). W and Mo are preferred from the viewpoint of the matching of the coefficient of thermal expansion with the insulating substrate and the cost. The via-hole conductor has a heat sink effect by connecting heat generated from a heat-generating electronic component from a surface-mounted power MOSFET or the like to the wiring conductor 2 formed on the opposite surface by heat conduction. You can also.

【0022】更に、本発明の多層配線基板に大電流を必
要とするパワーMOSFET等を表面実装する際、パワ
ーMOSFET用配線にも大電流用の配線導体を形成し
ておくと共に、前述のようにパワーMOSFETが表面
実装される部分にサーマルビアを兼用したビアホール導
体を多数設け、配線導体のヒートシンク作用と併用して
熱放散性を向上させることが望ましい。
Further, when a power MOSFET or the like requiring a large current is surface-mounted on the multilayer wiring board of the present invention, a wiring conductor for a large current is also formed on the power MOSFET wiring, and as described above. It is desirable to provide a large number of via-hole conductors that also serve as thermal vias in the portion where the power MOSFET is surface-mounted, and to improve the heat dissipation property in combination with the heat sink function of the wiring conductor.

【0023】一方、CuまたはAlを主導体とする配線
導体は、CuやAlを含むペーストを印刷塗布して、C
uの場合、900〜1000℃、Alの場合、550〜
600℃で焼き付け処理して形成して形成できる。
On the other hand, for a wiring conductor having Cu or Al as a main conductor, a paste containing Cu or Al is printed and applied to form a C
For u, 900-1000 ° C., for Al, 550-
It can be formed by baking at 600 ° C.

【0024】さらに10A以上の大電流を流す場合に
は、例えば厚さが0.1mm以上のCu板やAl板、あ
るいは粉末冶金法に従ってCuやAl粉末を所定の配線
導体形状にプレス成形法などによって成形した後、熱処
理(Cuの場合、950〜1000℃、Alの場合、5
50〜600℃)して作製された金属焼結体を、Cuの
場合、AgCuTiなどの活性金属を含むロウ材によっ
て、またAlの場合にはAlSiロウ材等で接合して形
成することができる。
Further, when a large current of 10 A or more is passed, for example, a Cu plate or an Al plate having a thickness of 0.1 mm or more, or a press forming method of Cu or Al powder into a predetermined wiring conductor shape by powder metallurgy. Heat treatment (950 to 1000 ° C. for Cu, 5 for Al)
(50 to 600 ° C.), the metal sintered body can be formed by bonding with a brazing material containing an active metal such as AgCuTi in the case of Cu, or with an AlSi brazing material in the case of Al. .

【0025】なお、絶縁基板1の内部に形成される内部
配線導体5やビアホール導体4は絶縁基板1と同時焼成
して形成されるが、絶縁基板表面には同時焼成によって
形成された表面配線導体が形成されていてもよい。
The internal wiring conductors 5 and via-hole conductors 4 formed inside the insulating substrate 1 are formed by simultaneous firing with the insulating substrate 1, and the surface wiring conductors formed by simultaneous firing are formed on the surface of the insulating substrate. May be formed.

【0026】本発明によれば、上記のようにして形成さ
れた配線導体2の表面の中心線平均表面粗さ(Ra)が
1〜3μmとすることが必要である。このような表面を
形成するには、CuやAlを主導体とする配線導体2を
導体ペースト塗布後、焼成して形成する場合には、導体
ペースト中のCuやAlの金属粉末の粒径を大きくする
ほど、焼成後の配線導体の表面粗さを大きくすることが
できる。
According to the present invention, the center line average surface roughness (Ra) of the surface of the wiring conductor 2 formed as described above needs to be 1 to 3 μm. In order to form such a surface, when the wiring conductor 2 having Cu or Al as a main conductor is formed by applying a conductive paste and then sintering, the particle size of the metal powder of Cu or Al in the conductive paste is reduced. As the size is increased, the surface roughness of the fired wiring conductor can be increased.

【0027】また、粉末冶金法によって金属粉末を所定
形状に成形後、焼成する方法でも、用いる金属粉末の粒
径を制御することによって焼き上がりの表面粗さを任意
に制御できる。
Also, in a method in which the metal powder is formed into a predetermined shape by powder metallurgy and then fired, the surface roughness of the baked metal can be arbitrarily controlled by controlling the particle size of the metal powder used.

【0028】さらに他の方法としては、Cu板、Al板
に酸やアルカリを塗布してエッチングして表面を粗化す
ることも可能である。
As still another method, it is possible to roughen the surface by applying an acid or alkali to a Cu plate or an Al plate and etching it.

【0029】上記のようにして形成された配線導体の表
面にCu、Ni、Snの群から選ばれる少なくとも1種
の金属からなるめっき層を1〜4μmの厚みで形成す
る。なお、このめっき層は単一層でも前記群からの組み
合わせによる多層化したものであってもよいが、その場
合でも全体厚みは1〜4μmとすることが望ましい。
On the surface of the wiring conductor formed as described above, a plating layer made of at least one metal selected from the group consisting of Cu, Ni and Sn is formed with a thickness of 1 to 4 μm. The plating layer may be a single layer or a multi-layer formed by a combination of the above-mentioned groups. Even in such a case, the total thickness is desirably 1 to 4 μm.

【0030】[0030]

【実施例】次に、以下のようにして本発明のセラミック
配線基板を評価した。なお、絶縁基板としてAlN質セ
ラミックスを用いた。まず、AlN粉末に、CaO0.
5重量%、Y235重量%を添加したAlN組成物にア
クリル系の有機性バインダーと可塑剤、溶剤を添加混合
して泥漿を調整し、該泥漿をドクターブレード法により
厚さ約300μmのシート状に成形した。次いで、前記
セラミックグリーンシート表面の配線形成部にWを主成
分とする印刷用ペーストを用いて厚さ20μmの所定の
配線パターンを印刷形成すると共に、スルーホールにも
所定のペーストを充填した。このセラミックグリーンシ
ートを複数枚積層後、1750℃で焼成し、厚さ2mm
の配線基板を作製した。
Next, the ceramic wiring board of the present invention was evaluated as follows. Note that AlN ceramics was used as the insulating substrate. First, CaO0.
A slurry is prepared by adding and mixing an acrylic organic binder, a plasticizer, and a solvent to the AlN composition containing 5% by weight and 5% by weight of Y 2 O 3 , and the slurry is about 300 μm thick by a doctor blade method. Into a sheet. Next, a predetermined wiring pattern having a thickness of 20 μm was printed on a wiring forming portion on the surface of the ceramic green sheet using a printing paste containing W as a main component, and the predetermined paste was filled in the through holes. After laminating a plurality of these ceramic green sheets, they are fired at 1750 ° C. to have a thickness of 2 mm.
Was manufactured.

【0031】厚さが0.5mmのCu板の表面をエッチ
ング処理して種々の表面粗さに加工した。これを絶縁基
板表面の所定部にAgCuTiロウ材で接合し、10m
m□の配線導体を形成した。その後、Niめっき層を無
電解めっき法によって0.5〜5μmの厚みでNiめっ
き層を形成した。
The surface of the Cu plate having a thickness of 0.5 mm was etched to be processed into various surface roughnesses. This is bonded to a predetermined portion of the insulating substrate surface with an AgCuTi brazing material,
An m □ wiring conductor was formed. Thereafter, the Ni plating layer was formed to a thickness of 0.5 to 5 μm by an electroless plating method.

【0032】上記の方法で作製した配線基板について以
下の評価を行なった。 (めっき膨れ量)配線基板を還元雰囲気中で400℃で
熱処理した後のめっき層のめっき面積10mm□当りの
ふくれ面積を評価した。 (接合強度)めっき層上に直径が0.6mmの銅線をS
n60Pb40%半田にて接合した後、銅線を垂直に引
張り、めっき層が剥がれる時の強度を接合強度として評
価した。 (ボイド量)また接合強度の評価をした配線基板の他の
配線導体ににSn60Pb40%半田で7mm□のSi
チップを実装して、X線透過装置でチップ下のボイド率
(半田実装面積7mm□当りのボイド面積)を評価し
た。各評価結果においては、サンプル数(配線導体数)
10個の平均値をグラフにプロットした。
The following evaluation was performed on the wiring board manufactured by the above method. (Plating swelling amount) The blister area per 10 mm square of the plating area of the plating layer after the wiring substrate was heat-treated at 400 ° C in a reducing atmosphere was evaluated. (Joint strength) A copper wire having a diameter of 0.6 mm
After bonding with n60Pb 40% solder, the copper wire was pulled vertically, and the strength when the plating layer was peeled was evaluated as the bonding strength. (Void amount) In addition, the other wiring conductor of the wiring board for which the bonding strength was evaluated was coated with 7 mm square Si with 40% Sn60Pb solder.
The chip was mounted, and the void ratio under the chip (void area per 7 mm square of solder mounting area) was evaluated by an X-ray transmission apparatus. In each evaluation result, the number of samples (number of wiring conductors)
The average of the ten values was plotted on a graph.

【0033】図3は、接合強度と表面粗さRaおよびめ
っき厚みとの関係を示したものである。図3よりめっき
厚み0.5〜5μmともに、配線導体の表面粗さを1μ
m以上とすることによって接合強度を4kgf/5mm
□以上にすることができ、1μm以上では接合強度の変
化はあまり見られなかった。
FIG. 3 shows the relationship between bonding strength, surface roughness Ra and plating thickness. As shown in FIG. 3, the surface roughness of the wiring conductor was 1 μm for both plating thicknesses of 0.5 to 5 μm.
m, the joining strength is 4 kgf / 5 mm.
□ or more, and at 1 μm or more, little change in bonding strength was observed.

【0034】図4は、めっき厚みとボイド率および表面
粗さRaとの関係を示したものである。図4より、表面
粗さRaが4μmの場合、めっき厚みを変えてもボイド
率が高く、最も低い値でも、めっき厚み3μmで10%
であった。また、めっき厚み0.5μmでは、表面粗さ
に関係なく、ボイド率が10%以上であった。表面粗さ
Ra1〜3μmでめっき厚み1〜4μmの条件で、ボイ
ド率は5%前後に減少した。
FIG. 4 shows the relationship between the plating thickness, the void ratio and the surface roughness Ra. FIG. 4 shows that when the surface roughness Ra is 4 μm, the void ratio is high even when the plating thickness is changed, and the lowest value is 10% when the plating thickness is 3 μm.
Met. When the plating thickness was 0.5 μm, the void ratio was 10% or more regardless of the surface roughness. Under the conditions of a surface roughness Ra of 1 to 3 μm and a plating thickness of 1 to 4 μm, the void ratio was reduced to about 5%.

【0035】図5は、めっき膨れ量とめっき厚みおよび
表面粗さRaとの関係を示したものである。図5より配
線導体の表面粗さに関係なく、めっき厚みが0.5〜2
μmではめっき膨れは全くないが、めっき厚み3〜4μ
mで発生しはじめ、めっき厚みが5μmになると、めっ
きふくれが10%以上に急激に増加した。この傾向は図
4に示すボイド率の傾向と一致し、めっき膨れはボイド
率に影響を及ぼすことがわかる。
FIG. 5 shows the relationship between the plating swollen amount, the plating thickness and the surface roughness Ra. FIG. 5 shows that the plating thickness is 0.5 to 2 irrespective of the surface roughness of the wiring conductor.
There is no plating swelling at μm, but plating thickness 3-4μ
m, and when the plating thickness became 5 μm, the plating swelling sharply increased to 10% or more. This tendency coincides with the tendency of the void ratio shown in FIG. 4, and it can be seen that the plating swelling affects the void ratio.

【0036】これらの結果より、配線導体の表面粗さR
aで1〜3μmであること、めっき厚みは1〜4μmが
好適であることが確認された。
From these results, the surface roughness R of the wiring conductor was obtained.
It was confirmed that a was 1 to 3 μm and the plating thickness was preferably 1 to 4 μm.

【0037】また、配線導体として、Alの金属焼結体
を用いる以外は上記と全く同様にして配線基板を作製
し、同様の評価を行なった結果、ほとんど図3〜図5と
ほとんど同様の結果を得た。
A wiring board was prepared in the same manner as described above except that a sintered metal of Al was used as the wiring conductor, and the same evaluation was performed. As a result, almost the same results as in FIGS. 3 to 5 were obtained. I got

【0038】[0038]

【発明の効果】本発明の配線基板によれば、めっき層が
接触する配線導体の表面粗さを、中心線平均粗さ(R
a)で1〜3μm、最大高さ(Rmax)で8〜30μ
mの粗面にし、さらにめっき厚みを1〜4μmにしたこ
とからめっき層と配線導体との接合強度を強固にするこ
とができ、さらにめっき膨れが少なく、半田濡れ性に優
れるため、電気的接続や熱伝導性が良好な半田実装が可
能となる配線基板を得ることができる。よって大電流化
に適応し得る信頼性に優れた、例えば車載環境のような
厳しい環境下においても故障することなく稼働させるこ
とが可能となる。
According to the wiring board of the present invention, the surface roughness of the wiring conductor with which the plating layer comes into contact is reduced by the center line average roughness (R
a) 1 to 3 μm, maximum height (Rmax) 8 to 30 μm
m, and the plating thickness is 1 to 4 μm, so that the bonding strength between the plating layer and the wiring conductor can be strengthened. Further, plating swelling is small and solder wettability is excellent. And a wiring board which can be solder-mounted with good thermal conductivity can be obtained. Therefore, it is possible to operate without failure even in a severe environment such as an in-vehicle environment, which is excellent in reliability that can be adapted to a large current.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のセラミック配線基板の一実施例を示す
多層配線基板の概略断面図である。
FIG. 1 is a schematic sectional view of a multilayer wiring board showing one embodiment of a ceramic wiring board of the present invention.

【図2】配線導体表面に電子部品を実装した時の要部拡
大断面図である。
FIG. 2 is an enlarged sectional view of a main part when an electronic component is mounted on the surface of a wiring conductor.

【図3】配線導体とめっき層の接合強度と、配線導体の
表面粗さ、めっき厚みの関係を示すグラフである。
FIG. 3 is a graph showing a relationship between bonding strength between a wiring conductor and a plating layer, surface roughness of the wiring conductor, and plating thickness.

【図4】ボイド率、配線導体の表面粗さ、めっき厚みの
関係を示すグラフである。
FIG. 4 is a graph showing a relationship among a void ratio, a surface roughness of a wiring conductor, and a plating thickness.

【図5】めっき膨れ量、配線導体の表面粗さ、めっき厚
みの関係を示すグラフである。
FIG. 5 is a graph showing a relationship between a plating swelling amount, a surface roughness of a wiring conductor, and a plating thickness.

【符号の説明】[Explanation of symbols]

1 絶縁基板 2 配線導体 3 めっき層 4 ビアホール導体 5 内部配線導体 6 半田 7 電子部品 DESCRIPTION OF SYMBOLS 1 Insulating board 2 Wiring conductor 3 Plating layer 4 Via hole conductor 5 Internal wiring conductor 6 Solder 7 Electronic component

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】セラミック絶縁基板の表面に、Cuまたは
Alを主導体とする配線導体が被着形成され、該配線導
体の表面に半田濡れ性に優れた金属からなるめっき層を
被覆形成してなり、このめっき層上に半田によって電子
部品が実装搭載される配線基板において、前記めっき層
を被覆形成する前記配線導体の中心線平均粗さ(Ra)
が1〜3μmであり、且つめっき層の厚みが1〜4μm
であることを特徴とするセラミック配線基板
A wiring conductor having Cu or Al as a main conductor is formed on a surface of a ceramic insulating substrate, and a plating layer made of a metal having excellent solder wettability is formed on the surface of the wiring conductor. In a wiring board on which an electronic component is mounted and mounted on the plating layer by soldering, the center line average roughness (Ra) of the wiring conductor covering the plating layer is formed.
Is 1 to 3 μm, and the thickness of the plating layer is 1 to 4 μm
Ceramic wiring board characterized by the following:
【請求項2】前記半田濡れ性に優れた金属が、Niから
なることを特徴とする請求項1記載のセラミック配線基
板。
2. The ceramic wiring board according to claim 1, wherein the metal having excellent solder wettability is made of Ni.
【請求項3】前記セラミック絶縁基板が、Al23、A
lN、Si34の群から選ばれる少なくとも1種を主体
とするセラミックスからなることを特徴とする請求項1
記載のセラミック配線基板。
3. The ceramic insulating substrate according to claim 1, wherein said substrate is made of Al 2 O 3 , A
l N, claim 1, characterized by comprising a ceramic mainly containing at least one selected from the group the Si 3 N 4
The ceramic wiring board as described.
JP36501999A 1999-12-22 1999-12-22 Ceramic wiring board Pending JP2001185838A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP36501999A JP2001185838A (en) 1999-12-22 1999-12-22 Ceramic wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP36501999A JP2001185838A (en) 1999-12-22 1999-12-22 Ceramic wiring board

Publications (1)

Publication Number Publication Date
JP2001185838A true JP2001185838A (en) 2001-07-06

Family

ID=18483237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP36501999A Pending JP2001185838A (en) 1999-12-22 1999-12-22 Ceramic wiring board

Country Status (1)

Country Link
JP (1) JP2001185838A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005106973A1 (en) * 2004-04-27 2005-11-10 Kyocera Corporation Wiring board for light emitting element
JP2006066409A (en) * 2004-07-28 2006-03-09 Kyocera Corp Wiring board for light emitting element, manufacturing method thereof and light emitting device
JP2006093565A (en) * 2004-09-27 2006-04-06 Kyocera Corp Wiring board for light emitting element, light emitting device and method for manufacturing it
JP2006156447A (en) * 2004-11-25 2006-06-15 Kyocera Corp Wiring board for light emitting element, light emitting device and its manufacturing method
US20200083062A1 (en) * 2012-11-28 2020-03-12 Dowa Metaltech Co., Ltd. Electronic part mounting substrate and method for producing same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005106973A1 (en) * 2004-04-27 2005-11-10 Kyocera Corporation Wiring board for light emitting element
US8314346B2 (en) 2004-04-27 2012-11-20 Kyocera Corporation Wiring board for light-emitting element
JP2006066409A (en) * 2004-07-28 2006-03-09 Kyocera Corp Wiring board for light emitting element, manufacturing method thereof and light emitting device
JP2006093565A (en) * 2004-09-27 2006-04-06 Kyocera Corp Wiring board for light emitting element, light emitting device and method for manufacturing it
JP2006156447A (en) * 2004-11-25 2006-06-15 Kyocera Corp Wiring board for light emitting element, light emitting device and its manufacturing method
US20200083062A1 (en) * 2012-11-28 2020-03-12 Dowa Metaltech Co., Ltd. Electronic part mounting substrate and method for producing same

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