JP2014135509A - Intermediate molded product for semiconductor device and semiconductor device - Google Patents

Intermediate molded product for semiconductor device and semiconductor device Download PDF

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JP2014135509A
JP2014135509A JP2014056571A JP2014056571A JP2014135509A JP 2014135509 A JP2014135509 A JP 2014135509A JP 2014056571 A JP2014056571 A JP 2014056571A JP 2014056571 A JP2014056571 A JP 2014056571A JP 2014135509 A JP2014135509 A JP 2014135509A
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layer
external electrode
semiconductor device
semiconductor element
mounting pad
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JP5866719B2 (en
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Hiroshi Nakagawa
宏史 中川
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Maxell Holdings Ltd
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Hitachi Maxell Ltd
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which does not adversely affect a semiconductor element magnetically, and does not cause decrease in conductivity even if the frequency of a transmission signal increases, by solving the diffusion problem of a surface layer formation metal and obtaining a non-magnetic external electrode.SOLUTION: An Ni-P layer 11 is interposed between a Cu layer 12 and a surface layer (Au layer) 10 composing an external electrode 3. The Ni-P composing such an Ni-P layer 11 exhibits excellent adhesion to both Cu and Au, and can prevent diffusion of Au effectively. The Ni-P is a non-magnetic material, and since all magnetic metal layers are eliminated from the external electrode 3, the external electrode 3 can be made non-magnetic completely. Since magnetic influence derived from the magnetic metal layer can be prevented from reaching a semiconductor element 2 reliably, malfunction of the semiconductor element 2 is prevented and reliability of a semiconductor device can be enhanced.

Description

本発明は、半導体素子と、該半導体素子と電気的に接続されている外部電極とを有し、これら半導体素子および外部電極が樹脂により封止されているリードレスタイプの半導体装置と、その製造方法に関する。   The present invention includes a semiconductor element and a leadless type semiconductor device having an external electrode electrically connected to the semiconductor element, the semiconductor element and the external electrode being sealed with a resin, and manufacturing the same Regarding the method.

この種の半導体装置の従来例としては、例えば特許文献１を挙げることができる。この半導体装置においては、基板上に、Ａｕ層、Ｎｉ層、およびＡｕ層を順にメッキすることにより、外部電極および半導体素子の搭載パッドとを形成している。   As a conventional example of this type of semiconductor device, for example, Patent Document 1 can be cited. In this semiconductor device, an Au layer, a Ni layer, and an Au layer are sequentially plated on a substrate to form an external electrode and a mounting pad for a semiconductor element.

また、Ｎｉ層に替えて、Ｃｕ層を外部電極等の構成層としたものもある（文献不詳）。このように、Ｃｕ層を採用したのは、ＣｕがＮｉに比べて安価であり、しかも導電性に優れていることに拠る。   In some cases, the Cu layer is replaced with a constituent layer such as an external electrode in place of the Ni layer (document unknown). As described above, the Cu layer is used because Cu is cheaper than Ni and has excellent conductivity.

特開昭５９−２０８７５６号公報JP 59-208756 A

特許文献１に記載の外部電極等の形態では、これを構成するＮｉ層が磁性金属であるため、半導体素子に磁気的な悪影響が及ぶことが避けられない。一方、外部電極の構成層をＮｉ層に替えてＣｕ層としていると、Ｃｕは非磁性金属であるため、半導体素子に対して磁気的な悪影響を与える不都合は生じない。しかし、Ｃｕ層上にＡｕ層を備える外部電極の形態では、Ａｕが拡散してしまうという新たな問題を招来する。   In the form of the external electrode or the like described in Patent Document 1, since the Ni layer constituting the external electrode is a magnetic metal, it is inevitable that the semiconductor element is adversely affected magnetically. On the other hand, when the constituent layer of the external electrode is replaced with a Ni layer to form a Cu layer, since Cu is a nonmagnetic metal, there is no inconvenience that adversely affects the semiconductor element magnetically. However, in the form of an external electrode having an Au layer on a Cu layer, a new problem that Au diffuses is caused.

Ａｕの拡散問題は、例えば、Ｃｕ層とＡｕ層との間にバリア層としてのＮｉ層を介在させることで解決できる。すなわち、Ｎｉは、ＣｕおよびＡｕの両金属との密着性に優れるとともに、これをＣｕ層とＡｕ層との間に介在させることで、先のＡｕの拡散問題を効果的に解決することができる。しかし、この場合には、外部電極等に磁性金属であるＮｉを用いることとなるため、先の特許文献１と同様に、半導体素子に対して磁気的な悪影響が及ぶことが懸念される。   The Au diffusion problem can be solved, for example, by interposing a Ni layer as a barrier layer between the Cu layer and the Au layer. That is, Ni is excellent in adhesion to both Cu and Au metals, and by interposing this between the Cu layer and the Au layer, the above diffusion problem of Au can be effectively solved. . However, in this case, since Ni, which is a magnetic metal, is used for the external electrode or the like, there is a concern that a magnetic adverse effect may be exerted on the semiconductor element as in the case of the above-mentioned Patent Document 1.

加えて、Ｎｉ層に替えてＣｕ層を採用した場合でも、近年の半導体素子の動作周波数が飛躍的に増大する傾向下では、高周波信号の伝達特性が問われて、外部電極等の導電性不良が問題となるおそれがある。
具体的には、外部電極等の表面にしか電流が流れなくなる「表皮効果」の影響がある。このように、表皮効果が生じると、実質的に通電に寄与する部分（通電部）の断面積が減少するため、通電部材そのものの導電性が高くなければ、その分だけ外部電極等のインピーダンスは増加し、半導体素子の動作特性に悪影響を与える。
次に、磁性の影響がある。磁性を持つ外部電極の場合は、伝送信号の周波数が増加すればするほど、インピーダンス虚数部分、すなわち減衰項が増大して導電率が劣化することが予想される。かかる不具合は、先のＮｉのほか、２％Ｆｅ含有の銅合金や４２アロイでは、相当の磁性を持つので、この効果が無視できない。 In addition, even when a Cu layer is used instead of the Ni layer, the operating frequency of semiconductor elements in recent years has increased dramatically. May be a problem.
Specifically, there is an influence of “skin effect” in which current flows only on the surface of an external electrode or the like. In this way, when the skin effect occurs, the cross-sectional area of the portion that substantially contributes to energization (the energization portion) decreases, so if the conductivity of the energization member itself is not high, the impedance of the external electrode, etc. Increases and adversely affects the operating characteristics of the semiconductor device.
Next, there is an influence of magnetism. In the case of an external electrode having magnetism, it is expected that as the frequency of the transmission signal increases, the imaginary part of the impedance, that is, the attenuation term increases, and the conductivity deteriorates. Such an inconvenience cannot be ignored because 2% Fe-containing copper alloy and 42 alloy have considerable magnetism in addition to the above Ni.

本発明は以上のような従来の半導体装置の抱える問題を解決するためになされたものであり、Ｃｕ層および表面層とを積層してなる外部電極を具備する半導体装置でありながら、Ｃｕと表面層形成金属の拡散問題を確実に解決することができ、しかも、これらＣｕ層と表面層との間のバリア層としてＮｉ層を採用せず、非磁性の外部電極を実現することにより、磁気的な悪影響を半導体素子に与えることが無く、加えて伝送信号の周波数が増加した場合でも導電率の低下が生じない、半導体装置、およびその製造方法を得ることを目的とする。
本発明の目的は、さらに表皮効果に由来するインピーダンスの増加が生じず、優れた導電率を備えた外部電極を具備する半導体装置、およびその製造方法を得ることにある。 The present invention has been made in order to solve the problems of the conventional semiconductor device as described above, and is a semiconductor device including an external electrode formed by laminating a Cu layer and a surface layer. It is possible to reliably solve the problem of diffusion of the layer-forming metal, and by adopting a non-magnetic external electrode without using a Ni layer as a barrier layer between the Cu layer and the surface layer, It is an object of the present invention to obtain a semiconductor device and a method for manufacturing the same that do not adversely affect the semiconductor element and that do not cause a decrease in conductivity even when the frequency of the transmission signal increases.
An object of the present invention is to obtain a semiconductor device including an external electrode having excellent conductivity without causing an increase in impedance due to the skin effect, and a manufacturing method thereof.

本発明は、半導体素子２と、該半導体素子２と電気的に接続されている外部電極３とを有し、これら半導体素子２および外部電極３が樹脂７により封止されている半導体装置を対象とする。
そして、外部電極３が、Ｃｕ層１２と、該Ｃｕ層１２の下方側に形成された表面層１０とを含み、加えて一切の磁性金属層を具備しないものであり、これらＣｕ層１２と表面層１０との間に、Ｎｉ−Ｐ層１１が介在されていることを特徴とする。Ｎｉ−ＰにおけるＰの含有率は８〜１４％程度であることが好ましく、９〜１０％が最適である。 The present invention is directed to a semiconductor device having a semiconductor element 2 and an external electrode 3 electrically connected to the semiconductor element 2, and the semiconductor element 2 and the external electrode 3 are sealed with a resin 7. And
The external electrode 3 includes a Cu layer 12 and a surface layer 10 formed on the lower side of the Cu layer 12, and does not include any magnetic metal layer. A Ni—P layer 11 is interposed between the layer 10 and the layer 10. The P content in Ni-P is preferably about 8 to 14%, and 9 to 10% is optimal.

半導体素子２は搭載パッド４上に配置されており、この搭載パッド４が、Ｃｕ層１２と、該Ｃｕ層１２の下方側に形成された表面層１０とを含み、加えて一切の磁性金属層を具備しないものであり、これらＣｕ層１２と表面層１０との間に、Ｎｉ−Ｐ層１１が介在されている形態を採ることができる。   The semiconductor element 2 is disposed on a mounting pad 4, which includes a Cu layer 12 and a surface layer 10 formed on the lower side of the Cu layer 12, in addition to any magnetic metal layer. The Ni-P layer 11 may be interposed between the Cu layer 12 and the surface layer 10.

表面層１０の具体例としては、Ｓｎ層、Ｓｎ−Ａｇ層（ＳｎとＡｇとの合金層）のほか、Ａｕ層、Ａｇ層、Ｐｄ層を挙げることができるが、Ａｕ層が最も好適である。   Specific examples of the surface layer 10 include an Sn layer, an Sn—Ag layer (an alloy layer of Sn and Ag), an Au layer, an Ag layer, and a Pd layer, and an Au layer is most preferable. .

外部電極３および搭載パッド４の少なくともいずれか一方は、表面層１０、Ｎｉ−Ｐ層１１およびＣｕ層１２の順に、各層を積層してなるものであり、Ｃｕ層１２が、周縁が上下方向に真っ直ぐに伸びるストレート部１２ａと、該ストレート部１２ａの上端から水平方向に張り出し形成されたフランジ部１２ｂとを含むものとすることができる。   At least one of the external electrode 3 and the mounting pad 4 is formed by laminating layers in the order of the surface layer 10, the Ni—P layer 11, and the Cu layer 12. The straight portion 12a that extends straight and the flange portion 12b that extends in the horizontal direction from the upper end of the straight portion 12a may be included.

フランジ部１２ｂの上面が、水平方向の中央部分の厚み寸法が大きく、周縁部に行くに従って厚み寸法が漸次小さくなるドーム状に形成することができる。なおここで言うドーム状とは、図１に示すごとく、フランジ部１２ｂの盤面中央がフラットで、周縁部が水平方向に行くに従って、漸次厚み寸法が小さくなるような形態をも含む概念である。   The upper surface of the flange portion 12b can be formed in a dome shape in which the thickness dimension of the central portion in the horizontal direction is large and the thickness dimension gradually decreases toward the peripheral edge. The dome shape referred to here is a concept including a form in which the center of the surface of the flange portion 12b is flat and the thickness dimension gradually decreases as the peripheral portion goes in the horizontal direction, as shown in FIG.

外部電極３は、表面層１０、Ｎｉ−Ｐ層１１およびＣｕ層１２の順に、各層を積層してなるものであり、Ｃｕ層１２は、その盤面中央部に貫通孔３０を有する中空構造とすることができる。   The external electrode 3 is formed by laminating layers in the order of the surface layer 10, the Ni—P layer 11, and the Cu layer 12, and the Cu layer 12 has a hollow structure having a through hole 30 at the center of the board surface. be able to.

Ｃｕ層１２上に、Ａｕ層１３、Ａｇ層１４およびＰｄ層から選択される一層又は複数層を形成することが好ましい。   It is preferable to form one layer or a plurality of layers selected from the Au layer 13, the Ag layer 14 and the Pd layer on the Cu layer 12.

また本発明は、半導体素子２と、該半導体素子２が搭載される搭載パッド４と、該半導体素子２と電気的に接続される外部電極３とを有し、これら半導体素子２、搭載パッド４、および外部電極３が樹脂７により封止されている半導体装置の製造方法を対象とする。 この製造方法は、基板２０の表面に、搭載パッド４および外部電極３の形成箇所を除く部分に対応するレジスト体２５ａを有するパターンレジスト２５を形成する工程と、レジスト体２５ａを用いて、基板２０上に表面層１０、Ｎｉ−Ｐ層１１およびＣｕ層１２をメッキ法により形成するメッキ工程と、パターンレジスト２５を除去する工程とを含む。   The present invention also includes a semiconductor element 2, a mounting pad 4 on which the semiconductor element 2 is mounted, and an external electrode 3 electrically connected to the semiconductor element 2. And a method of manufacturing a semiconductor device in which the external electrode 3 is sealed with a resin 7. This manufacturing method uses a step of forming a pattern resist 25 having a resist body 25a corresponding to a portion excluding the formation positions of the mounting pad 4 and the external electrode 3 on the surface of the substrate 20, and using the resist body 25a, the substrate 20 A plating process for forming the surface layer 10, the Ni-P layer 11 and the Cu layer 12 thereon by plating and a process for removing the pattern resist 25 are included.

前記電鋳工程のＣｕ層１２の形成に際しては、電着金属をレジスト体２５ａの高さ位置を超えて電着させることで、Ｃｕ層１２に周縁が上下方向に真っ直ぐに伸びるストレート部１２ａと、該ストレート部１２ａの上端から水平方向に張り出し形成されたフランジ部１２ｂとが形成されるようにすることができる。   In forming the Cu layer 12 in the electroforming process, by depositing the electrodeposited metal beyond the height position of the resist body 25a, a straight portion 12a whose peripheral edge extends straight in the vertical direction on the Cu layer 12, It is possible to form a flange portion 12b that is formed to project from the upper end of the straight portion 12a in the horizontal direction.

Ｃｕ層１２の形成工程に際しては、フランジ部１２ｂの上面が、水平方向の中央部分の厚み寸法が大きく、周縁部に行くに従って厚み寸法が漸次小さくなるドーム状となるようにすることができる。   In the process of forming the Cu layer 12, the upper surface of the flange portion 12b can be formed in a dome shape in which the thickness dimension of the central portion in the horizontal direction is large and the thickness dimension gradually decreases toward the peripheral edge.

Ｃｕ層１２上に、Ａｕ層１３、Ａｇ層１４およびＰｄ層から選択される一層又は複数層を形成する工程を含むものとすることができる。   A step of forming a single layer or a plurality of layers selected from the Au layer 13, the Ag layer 14, and the Pd layer on the Cu layer 12 may be included.

本発明に係る半導体装置においては、外部電極３を構成するＣｕ層１２と表面層１０との間に、Ｎｉ−Ｐ層１１を介在させた。かかるＮｉ−Ｐ層１１を構成するＮｉ−Ｐは、Ｃｕおよび表面層形成金属（例えばＡｕ、Ｓｎなど）の両者に対して優れた密着性を示すため、表面層１０の剥がれや脱落を確実に防止することができる。また、このように、Ｃｕ層１２と表面層１０との間にＮｉ−Ｐ層１１を介在させることにより、表面層形成金属の拡散を効果的に防止することができる。これにて、半導体装置の信頼性の向上を図ることができる。   In the semiconductor device according to the present invention, the Ni—P layer 11 is interposed between the Cu layer 12 constituting the external electrode 3 and the surface layer 10. Ni-P constituting the Ni-P layer 11 exhibits excellent adhesion to both Cu and a surface layer forming metal (for example, Au, Sn, etc.), so that the surface layer 10 is surely peeled off or dropped off. Can be prevented. Further, by interposing the Ni-P layer 11 between the Cu layer 12 and the surface layer 10 as described above, the diffusion of the surface layer forming metal can be effectively prevented. Thus, the reliability of the semiconductor device can be improved.

Ｎｉ−Ｐは非磁性体であり、加えて外部電極３から一切の磁性金属層を廃したため、本発明によれば、外部電極３の全体を完全に非磁性化できる。これにて、磁性金属層に由来する磁気的な影響が半導体素子２に及ぶことを確実に防ぐことができるので、半導体素子２の動作不良を防いで、半導体装置の信頼性向上に貢献できる。
加えて、外部電極３の全体を非磁性化していると、磁性を持つ外部電極３においては不可避であった、伝送信号の周波数の増加に伴って導電率が劣化する問題を確実に解消できる。従って、動作周波数や伝送信号の周波数を増加させた場合にも、外部電極３の導電率が低下する不具合は生じず、この点でも信頼性に優れた半導体装置を得ることができる。 Since Ni-P is a non-magnetic material and in addition, any magnetic metal layer is eliminated from the external electrode 3, the entire external electrode 3 can be made completely non-magnetic according to the present invention. As a result, it is possible to reliably prevent the magnetic influence derived from the magnetic metal layer from reaching the semiconductor element 2, thereby preventing malfunction of the semiconductor element 2 and contributing to improving the reliability of the semiconductor device.
In addition, if the entire external electrode 3 is made non-magnetic, it is possible to reliably solve the problem that the conductivity deteriorates with an increase in the frequency of the transmission signal, which is inevitable in the magnetic external electrode 3. Therefore, even when the operating frequency and the frequency of the transmission signal are increased, there is no problem that the conductivity of the external electrode 3 is reduced, and a semiconductor device with excellent reliability can be obtained in this respect.

搭載パッド４を構成するＣｕ層１２と表面層１０との間に、Ｎｉ−Ｐ層１１を介在させた場合にも、先の外部電極３と同様の作用効果を得ることができる。すなわち、Ｎｉ−Ｐは、Ｃｕおよび表面層形成金属（例えばＡｕ、Ｓｎなど）の両者に対して優れた密着性を示すため、搭載パッド４を構成する表面層１０の剥がれや脱落を確実に防止することができる。また、Ｃｕ層１２と表面層１０との間に、Ｎｉ−Ｐ層１１を介在させることにより、表面層形成金属の拡散を効果的に防止することができる。
加えて、搭載パッド４の全体を非磁性化することができるので、磁気的な影響が半導体素子２に及ぶことは無く、磁気的影響に由来する動作不良が生じることも無い。 Even when the Ni-P layer 11 is interposed between the Cu layer 12 and the surface layer 10 constituting the mounting pad 4, the same effects as those of the external electrode 3 can be obtained. That is, since Ni-P exhibits excellent adhesion to both Cu and surface layer forming metals (for example, Au, Sn, etc.), it is possible to reliably prevent the surface layer 10 constituting the mounting pad 4 from peeling off or falling off. can do. In addition, by interposing the Ni-P layer 11 between the Cu layer 12 and the surface layer 10, the diffusion of the surface layer forming metal can be effectively prevented.
In addition, since the entire mounting pad 4 can be made non-magnetic, there is no magnetic influence on the semiconductor element 2, and there is no malfunction caused by the magnetic influence.

Ｃｕ層１２を、周縁が上下方向に真っ直ぐに伸びるストレート部１２ａと、該ストレート部１２ａの上端から水平方向に張り出し形成されたフランジ部１２ｂとを含むものとしていると、フランジ部１２ｂの張り出し分だけ、Ｃｕ層１２の表面積を大きくすることができる。これによれば、表面にのみで電流が流れる表皮効果の影響を小さくすることができるので、外部電極３のインピーダンスの増加を抑えて、外部電極３の導電率の低下を抑えることができる。これにて、動作信号等の伝送不能に由来する半導体素子２の動作不良の発生を防ぐことができるので、半導体装置の信頼性向上に貢献できる。
かかる作用効果は、Ｃｕ層１２上にＡｕ層１３、Ａｇ層１４、Ｐｄ層等を形成した場合でも同様であり、フランジ部１２ｂの張り出し分だけ、Ａｕ層１３、Ａｇ層１４、Ｐｄ層の表面積を大きくすることができるので、表皮効果の影響を小さくすることができる。また、Ｃｕ層１２とＡｕ層１３やＡｇ層１４等との間の接着面積の増加を図ることができるので、この点でも表皮効果を影響を小さくすることができる。 When the Cu layer 12 includes a straight portion 12a whose peripheral edge extends straight in the up-down direction and a flange portion 12b that is formed to protrude from the upper end of the straight portion 12a in the horizontal direction, only the portion of the flange portion 12b that protrudes. The surface area of the Cu layer 12 can be increased. According to this, since the influence of the skin effect in which current flows only on the surface can be reduced, an increase in the impedance of the external electrode 3 can be suppressed, and a decrease in the conductivity of the external electrode 3 can be suppressed. As a result, it is possible to prevent the malfunction of the semiconductor element 2 resulting from the inability to transmit operation signals and the like, which can contribute to improving the reliability of the semiconductor device.
This effect is the same even when the Au layer 13, the Ag layer 14, the Pd layer, and the like are formed on the Cu layer 12, and the surface area of the Au layer 13, the Ag layer 14, and the Pd layer is the same as the overhang of the flange portion 12b. Therefore, the influence of the skin effect can be reduced. In addition, since the adhesion area between the Cu layer 12 and the Au layer 13 or the Ag layer 14 can be increased, the skin effect can be reduced in this respect as well.

加えて、Ｃｕ層１２を、周縁が上下方向に真っ直ぐに伸びるストレート部１２ａと、該ストレート部１２ａの上端から水平方向に張り出し形成されたフランジ部１２ｂとを含むものとしていると、フランジ部１２ｂの張り出し部分が樹脂７に食い込ませることができるため、外部電極３や搭載パッド４の不用意な脱落等を確実に防ぐことができる。かかる作用効果は、特に基板２０から樹脂封止体を剥離する際（図５（ｄ）参照）に有用である。すなわち、基板２０からの剥離時に、外部電極３等が基板２０に張り付いて、外部電極３等が樹脂封止体（半導体装置）から脱落することを効果的に防ぐことができる。また、樹脂封止体に対して外部電極３等が位置ズレしたり、外部電極３等の一部が欠けることも効果的に防ぐことができる。   In addition, when the Cu layer 12 includes a straight portion 12a whose peripheral edge extends straight in the vertical direction and a flange portion 12b formed so as to extend horizontally from the upper end of the straight portion 12a, the flange portion 12b Since the overhanging portion can bite into the resin 7, it is possible to reliably prevent the external electrode 3 and the mounting pad 4 from being accidentally dropped off. Such an effect is particularly useful when the resin sealing body is peeled from the substrate 20 (see FIG. 5D). That is, it is possible to effectively prevent the external electrodes 3 and the like from sticking to the substrate 20 and peeling off from the resin sealing body (semiconductor device) when peeling from the substrate 20. In addition, it is possible to effectively prevent the external electrode 3 and the like from being displaced relative to the resin sealing body and a part of the external electrode 3 and the like from being lost.

フランジ部１２ｂの上面が、水平方向の中央部分の厚み寸法が大きく、周縁部に行くに従って厚み寸法が漸次小さくなるドーム状に形成することができる。これによれば、フランジ部１２ｂの上面をフラットとする形態に比べて、Ｃｕ層１２の表面積を大きくできるので、表皮効果の影響をより小さくして、導電率の低下を抑えることができる。かかる作用効果は、Ｃｕ層１２上に、Ａｕ層１３、Ａｇ層１４、Ｐｄ層等を形成した場合でも同様である。   The upper surface of the flange portion 12b can be formed in a dome shape in which the thickness dimension of the central portion in the horizontal direction is large and the thickness dimension gradually decreases toward the peripheral edge. According to this, since the surface area of the Cu layer 12 can be increased as compared with the form in which the upper surface of the flange portion 12b is flat, it is possible to reduce the influence of the skin effect and suppress the decrease in conductivity. This effect is the same even when the Au layer 13, the Ag layer 14, the Pd layer, and the like are formed on the Cu layer 12.

外部電極３は、Ｃｕ層１２の盤面中央部に貫通孔３０を有する中空構造とすることができる。これによっても、貫通孔３０の内面の分だけ、Ｃｕ層１２の表面積を大きくすることができるので、「表皮効果」の影響をより小さくして、外部電極の導電率の低下を抑えることができる。   The external electrode 3 can have a hollow structure having a through hole 30 in the center of the board surface of the Cu layer 12. Also by this, since the surface area of the Cu layer 12 can be increased by the inner surface of the through hole 30, the influence of the “skin effect” can be reduced and the decrease in the conductivity of the external electrode can be suppressed. .

Ｃｕ層１２上に、Ａｕ層１３、Ａｇ層１４およびＰｄ層から選択される一層又は複数層が形成されている形態を採ることができる。これら金属（Ａｕ、Ａｇ、Ｐｄ）は、非磁性金属であるため、半導体素子２に磁気的影響を与えることが無い。加えて、これら金属（Ａｕ、Ａｇ、Ｐｄ）は、良好な導電率を有し、表皮効果に由来する導電率低下の悪影響も効果的に抑えることができる。   A form in which one layer or a plurality of layers selected from the Au layer 13, the Ag layer 14, and the Pd layer is formed on the Cu layer 12 can be adopted. Since these metals (Au, Ag, Pd) are nonmagnetic metals, they do not affect the semiconductor element 2 magnetically. In addition, these metals (Au, Ag, Pd) have good conductivity, and can effectively suppress the adverse effect of the decrease in conductivity derived from the skin effect.

本発明に係る半導体装置の製造方法においては、外部電極３および搭載パッド４を構成するＣｕ層１２と表面層１０との間に、Ｃｕおよび表面層形成金属（例えば、Ａｕ、Ｓｎなど）の両者に対して優れた密着性を示すＮｉ−Ｐ層１１を介在させたので、表面層形成金属の拡散を効果的に防止でき、従って、外部電極３や搭載パッド４を構成する表面層１０の剥がれや脱落を防止して、信頼性に優れた半導体装置を得ることができる。
加えて、外部電極３と搭載パッド４の全体を非磁性化することができるので、磁気的な影響が半導体素子２に及ぶことは無く、磁気的影響に由来する半導体素子の動作不良の発生も効果的に防止することができる。 In the method of manufacturing a semiconductor device according to the present invention, both Cu and a surface layer forming metal (for example, Au, Sn, etc.) are provided between the Cu layer 12 and the surface layer 10 constituting the external electrode 3 and the mounting pad 4. Since the Ni—P layer 11 exhibiting excellent adhesion to the surface is interposed, the diffusion of the surface layer forming metal can be effectively prevented, and therefore the surface layer 10 constituting the external electrode 3 and the mounting pad 4 is peeled off. Thus, a semiconductor device with excellent reliability can be obtained.
In addition, since the entire external electrode 3 and the mounting pad 4 can be made non-magnetic, the magnetic influence does not reach the semiconductor element 2, and the semiconductor element malfunctions due to the magnetic influence. It can be effectively prevented.

電鋳工程のＣｕ層１２の形成に際しては、電着金属をレジスト体２５ａの厚み寸法を超えて電着させることで、Ｃｕ層１２に周縁が上下方向に真っ直ぐに伸びるストレート部１２ａと、該ストレート部１２ａの上端から水平方向に張り出し形成されたフランジ部１２ｂとを形成するようにすることができる。これによれば、フランジ部１２ｂの張り出し分だけ、Ｃｕ層１２の表面積を大きくできるので、表皮効果の影響を小さくでき、従って外部電極３のインピーダンスの増加を抑えて、外部電極３の導電率の低下を抑えることができる。これにて、動作信号等の伝送不能に由来する半導体素子２の動作不良の発生を防ぐことができるので、半導体装置の信頼性向上に貢献できる。   In forming the Cu layer 12 in the electroforming process, the electrodeposited metal is electrodeposited beyond the thickness of the resist body 25a, whereby the Cu layer 12 has a straight portion 12a whose periphery extends straight in the vertical direction, and the straight It is possible to form a flange portion 12b that is formed to project from the upper end of the portion 12a in the horizontal direction. According to this, since the surface area of the Cu layer 12 can be increased by the overhanging portion of the flange portion 12b, the influence of the skin effect can be reduced, and thus the increase in the impedance of the external electrode 3 can be suppressed, and the conductivity of the external electrode 3 can be reduced. The decrease can be suppressed. As a result, it is possible to prevent the malfunction of the semiconductor element 2 resulting from the inability to transmit operation signals and the like, which can contribute to improving the reliability of the semiconductor device.

フランジ部１２ｂの上面が、水平方向の中央部分の厚み寸法が大きく、周縁部に行くに従って厚み寸法が漸次小さくなるドーム状に形成することができ、これによれば、フランジ部１２ｂの上面をフラットとする形態に比べて、Ｃｕ層１２の表面積を大きくできる。従って、表皮効果の影響をより小さくして、外部電極３の導電率の低下を抑えることができる。   The upper surface of the flange portion 12b can be formed in a dome shape in which the thickness dimension of the central portion in the horizontal direction is large and the thickness dimension gradually decreases toward the peripheral portion. According to this, the upper surface of the flange portion 12b is flattened. The surface area of the Cu layer 12 can be increased as compared with the embodiment. Therefore, the influence of the skin effect can be further reduced, and the decrease in the conductivity of the external electrode 3 can be suppressed.

Ｃｕ層１２上に、Ａｕ層１３、Ａｇ層１４およびＰｄ層から選択される一層又は複数層が形成されている形態を採ることができる。これら金属（Ａｕ、Ａｇ、Ｐｄ）は、非磁性金属であるため、半導体素子２に磁気的影響を与えることが無い。加えて、これら金属（Ａｕ、Ａｇ、Ｐｄ）は、良好な導電率を有するため、表皮効果に由来する外部電極３の導電率低下の悪影響が生じることも無い。   A form in which one layer or a plurality of layers selected from the Au layer 13, the Ag layer 14, and the Pd layer is formed on the Cu layer 12 can be adopted. Since these metals (Au, Ag, Pd) are nonmagnetic metals, they do not affect the semiconductor element 2 magnetically. In addition, since these metals (Au, Ag, Pd) have good conductivity, there is no adverse effect of lowering the conductivity of the external electrode 3 due to the skin effect.

本発明の第１実施形態に係る半導体装置の縦断側面図である。It is a vertical side view of the semiconductor device concerning a 1st embodiment of the present invention. 本発明の第１実施形態に係る半導体装置の斜視図である。1 is a perspective view of a semiconductor device according to a first embodiment of the present invention. （ａ）〜（ｅ）は、第１実施形態に係る半導体装置の製造方法を説明するための図である。(A)-(e) is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment. （ａ）〜（ｅ）は、電鋳工程を説明するための図である。(A)-(e) is a figure for demonstrating an electroforming process. （ａ）〜（ｄ）は、第１実施形態に係る半導体装置の製造方法を説明するための図である。(A)-(d) is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 半導体装置の製造方法を説明するための平面図である。It is a top view for demonstrating the manufacturing method of a semiconductor device. 本発明の第２実施形態に係る半導体装置の縦断側面図である。It is a vertical side view of the semiconductor device which concerns on 2nd Embodiment of this invention. （ａ）〜（ｄ）は、第２実施形態に係る半導体装置の製造方法を説明するための図である。(A)-(d) is a figure for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. 第２実施形態の変形例に係る半導体装置の縦断側面図である。It is a vertical side view of the semiconductor device which concerns on the modification of 2nd Embodiment.

（第１実施形態） 図１乃至図６に本発明の第１実施形態に係る半導体装置を示す。図１は、本発明に係るリードレス表面実装型の半導体装置の縦断側面図、図２は、半導体装置の裏面を示す斜視図である。
図１および図２に示すように、この半導体装置１は、一つの半導体素子２と、この半導体体素子２を囲むように配された複数個（６個）の外部電極３と、半導体素子２が載置される搭載パッド４と、半導体素子２の上面に形成された電極５と外部電極３とを電気的に接続するワイヤ６とを有し、これら半導体素子２、外部電極３、搭載パッド４およびワイヤ６をエポキシ樹脂等の樹脂７により封止してなるものである。
図２に示すように、半導体装置１は、全体として四角ブロック形状に形成されており、その底面側には、搭載パッド４と外部電極３とが露出している。 First Embodiment FIGS. 1 to 6 show a semiconductor device according to a first embodiment of the present invention. FIG. 1 is a longitudinal side view of a leadless surface mount type semiconductor device according to the present invention, and FIG. 2 is a perspective view showing the back surface of the semiconductor device.
As shown in FIGS. 1 and 2, the semiconductor device 1 includes a single semiconductor element 2, a plurality (six) external electrodes 3 arranged so as to surround the semiconductor body element 2, and a semiconductor element 2. , A wire 6 for electrically connecting the electrode 5 formed on the upper surface of the semiconductor element 2 and the external electrode 3, the semiconductor element 2, the external electrode 3, and the mounting pad 4 and the wire 6 are sealed with a resin 7 such as an epoxy resin.
As shown in FIG. 2, the semiconductor device 1 is formed in a square block shape as a whole, and the mounting pad 4 and the external electrode 3 are exposed on the bottom side thereof.

外部電極３および搭載パッド４は、Ａｕ層（表面層）１０、Ｎｉ−Ｐ層１１、Ｃｕ層１２、Ａｕ層１３、Ａｇ層１４を下方側から順に積層してなるものである。外部電極３のＡｕ層１０は、不図示の外部装置からの動作信号等の送入・送出口として機能する。Ａｕ層１０とＣｕ層１２との間に介在されるＮｉ−Ｐ層１１を構成するＮｉ−Ｐは、ＡｕおよびＣｕの両者に対して、良好な密着性を示すため、Ａｕ層１０の不用意な剥がれや脱落を効果的に防止することができる。また、かかるＮｉ−Ｐ層１１は、バリア層として作用するため、Ａｕの拡散を確実に防止することができる。なお、これらＡｕ層１０とＮｉ−Ｐ層１１とは、周縁（四周縁）が上下方向に真っ直ぐに伸びるストレート状に形成されている。   The external electrode 3 and the mounting pad 4 are formed by sequentially laminating an Au layer (surface layer) 10, a Ni-P layer 11, a Cu layer 12, an Au layer 13, and an Ag layer 14 from the lower side. The Au layer 10 of the external electrode 3 functions as an input / output port for an operation signal or the like from an external device (not shown). Since Ni—P constituting the Ni—P layer 11 interposed between the Au layer 10 and the Cu layer 12 exhibits good adhesion to both Au and Cu, the Au layer 10 is not prepared. Can be effectively prevented from peeling off or falling off. Further, since the Ni—P layer 11 acts as a barrier layer, it is possible to reliably prevent Au from diffusing. Note that the Au layer 10 and the Ni-P layer 11 are formed in a straight shape whose peripheral edges (four peripheral edges) extend straight in the vertical direction.

Ｃｕ層１２は、外部電極３および搭載パッド４の主体をなすものであり、Ｎｉ−Ｐ層１１と同一の外形寸法で周縁が上下方向に真っ直ぐに伸びるストレート部１２ａと、該ストレート部１２ａの上端から水平方向に張り出し形成されたフランジ部１２ｂとで構成される。フランジ部１２ｂの上面の盤面中央はフラットとされており、フランジ部１２ｂの周縁は、水平外方向に行くに従って漸次厚み寸法が小さくされており、全体として、フラット部分の厚み寸法が大きなドーム状とされている。   The Cu layer 12 constitutes the main body of the external electrode 3 and the mounting pad 4, and has a straight portion 12a having the same outer dimensions as the Ni-P layer 11 and a peripheral edge extending straight in the vertical direction, and an upper end of the straight portion 12a. And a flange portion 12b formed in a horizontal direction. The center of the surface of the upper surface of the flange portion 12b is flat, and the peripheral edge of the flange portion 12b is gradually reduced in thickness toward the outer horizontal direction. As a whole, the flat portion has a large dome shape. Has been.

Ａｕ層１３およびＡｇ層１４は、表皮効果対策として形成される。すなわち、Ｃｕよりも導電率に優れたＡｇ層１４を最表面に配することで、電流をＣｕ層１２側にも流して、外部電極３の全体の導電性の向上を図っている。   The Au layer 13 and the Ag layer 14 are formed as a countermeasure against the skin effect. That is, by disposing the Ag layer 14 having a conductivity higher than that of Cu on the outermost surface, a current is caused to flow also to the Cu layer 12 side, thereby improving the overall conductivity of the external electrode 3.

図３乃至図６に、この半導体装置１の製造方法を示す。まず、図３（ａ）に示すごとく、ステンレスやアルミ、銅等の導電性の金属板からなる基板２０の表面に、アルカリタイプの感光性フィルムレジストをラミネートして、フォトレジスト層２１を形成する。次に、フォトレジスト層２１の上面に、搭載パッド４および外部電極３の形成箇所を除く部分に対応する透光孔２２を有するパターンフィルム２３（ガラスマスク）を密着させたのち、紫外光ランプ２４で紫外線光を照射して露光を行う。ここでは、紫外光ランプ２４から上下方向に指向性を有する紫外線光を照射することにより、フォトレジスト層２１に対してストレート状に露光を行った。次いで、乾燥の各処理を行って、未露光部分を溶解除去することにより、図３（ｂ）に示すように、搭載パッド４および外部電極３の形成箇所を除く部分に対応するレジスト体２５ａを有し、搭載パッド４および外部電極３の形成箇所に対応する、平面視で四角状の通孔２５ｂ・２５ｃを有するパターンレジスト２５を基板２０上に形成する。通孔２５ｂ・２５ｃの内周縁（対向辺の間隔寸法）は、均一なストレート状となるようにした。   3 to 6 show a method for manufacturing the semiconductor device 1. First, as shown in FIG. 3A, an alkali-type photosensitive film resist is laminated on the surface of a substrate 20 made of a conductive metal plate such as stainless steel, aluminum, or copper to form a photoresist layer 21. . Next, after a pattern film 23 (glass mask) having a light transmitting hole 22 corresponding to a portion excluding the formation position of the mounting pad 4 and the external electrode 3 is brought into intimate contact with the upper surface of the photoresist layer 21, the ultraviolet light lamp 24. The exposure is performed by irradiating with UV light. Here, the photoresist layer 21 was exposed in a straight shape by irradiating ultraviolet light having directivity in the vertical direction from the ultraviolet lamp 24. Next, each drying process is performed to dissolve and remove the unexposed portion, thereby removing the resist body 25a corresponding to the portion excluding the formation position of the mounting pad 4 and the external electrode 3 as shown in FIG. A pattern resist 25 having square through holes 25b and 25c in plan view corresponding to the mounting pads 4 and the external electrode 3 is formed on the substrate 20. The inner peripheries (spacing dimensions of the opposing sides) of the through holes 25b and 25c were made to be a uniform straight shape.

続いて、図３（ｃ）に示すように、Ａｕ層１０、Ｎｉ−Ｐ層１１、Ｃｕ層１２、Ａｕ層１３、Ａｇ層１４を順にメッキ法により積層して、搭載パッド４および外部電極３を形成する（メッキ工程）。
図４（ａ）〜（ｅ）に、このメッキ工程のより詳細を示す。そこではまず、必要に応じて化学エッチングによる表面酸化皮膜除去や薬品による周知の化学処理等の表面活性化処理を基板２０に対して行ったのち、基板２０を所定の条件に建浴した電鋳槽に入れ、図４（ａ）に示すごとく、先のレジスト体２５ａで覆われていない基板２０の表面（通孔２５ｂ・２５ｃ）に、Ａｕを電鋳してＡｕ層１０を形成する。次に、先と同様の手順で、Ａｕ層１０上に、Ｎｉ−Ｐをメッキ（無電解）してＮｉ−Ｐ層１１を形成する（図４（ｂ））。 Subsequently, as shown in FIG. 3C, the Au layer 10, the Ni—P layer 11, the Cu layer 12, the Au layer 13, and the Ag layer 14 are sequentially laminated by a plating method, and the mounting pad 4 and the external electrode 3 are stacked. (Plating process).
4A to 4E show more details of this plating process. First, surface activation treatment such as removal of a surface oxide film by chemical etching or well-known chemical treatment by chemicals is performed on the substrate 20 as necessary, and then the electroforming is performed by bathing the substrate 20 under a predetermined condition. 4A, the Au layer 10 is formed by electroforming Au on the surface (through holes 25b and 25c) of the substrate 20 that is not covered with the previous resist body 25a. Next, Ni—P is plated (electroless) on the Au layer 10 by the same procedure as described above to form the Ni—P layer 11 (FIG. 4B).

次に、図４（ｃ）に示すごとく、Ｎｉ−Ｐ層１１上にＣｕを電鋳してＣｕ層１２を形成する。かかるＣｕ層１２の形成に際しては、Ｃｕをレジスト体２５ａの高さ位置を越えて電着させることで、レジスト体２５ａの高さ位置を越えない箇所には、周縁が上下方向に真っ直ぐに伸びるストレート部１２ａが形成され、レジスト体２５ａの高さ位置を越える箇所には、該ストレート部１２ａの上端から水平方向に張り出し形成されたフランジ部１２ｂとが形成されるようにする。   Next, as shown in FIG. 4C, Cu is electroformed on the Ni—P layer 11 to form a Cu layer 12. In the formation of the Cu layer 12, Cu is electrodeposited beyond the height position of the resist body 25 a, so that the periphery extends straight in the vertical direction at a position not exceeding the height position of the resist body 25 a. A portion 12a is formed, and a flange portion 12b is formed at a location exceeding the height position of the resist body 25a. The flange portion 12b extends from the upper end of the straight portion 12a in the horizontal direction.

次に、図４（ｄ）に示すごとく、Ｃｕ層１２の上面の全体にＡｕをメッキ（ストライクメッキ）してＡｕ層１３を形成したのち、図４（ｅ）および図３（ｃ）に示すごとく、Ａｕ層１３の上面の全体にＡｇを電鋳してＡｇ層１４を形成する。これにて、基板２０上に、Ａｕ層１０、Ｎｉ−Ｐ層１１、Ｃｕ層１２、Ａｕ層１３およびＡｇ層１４で構成される搭載パッド４および外部電極３を形成することができた。   Next, as shown in FIG. 4 (d), Au is plated on the entire upper surface of the Cu layer 12 (strike plating) to form the Au layer 13, and then shown in FIGS. 4 (e) and 3 (c). As described above, Ag is electroformed on the entire upper surface of the Au layer 13 to form the Ag layer 14. Thus, the mounting pad 4 and the external electrode 3 composed of the Au layer 10, the Ni—P layer 11, the Cu layer 12, the Au layer 13, and the Ag layer 14 could be formed on the substrate 20.

次に、図３（ｄ）に示すごとく、パターンレジスト２５（レジスト体２５ａ）を溶解除去して、基板２０上に搭載パッド４と外部電極３とが搭載された中間成形品を得た。   Next, as shown in FIG. 3D, the pattern resist 25 (resist body 25a) was dissolved and removed to obtain an intermediate molded product in which the mounting pad 4 and the external electrode 3 were mounted on the substrate 20.

次に、図５（ａ）に示すごとく、半導体素子２を公知の手法により搭載パッド４上に接着して搭載したのち、図５（ｂ）に示すごとく、半導体素子２上の電極５とこれに対応する外部電極３との間を、金線等のワイヤ６を用いて超音波ボンディング装置等により結線する。ここで、ワイヤ６を結線するにあたり、外部電極３等にやボンディング装置からの引き離し力が作用し、外部電極３等は基板２０から浮き上がろうとするが、上述のように、メッキ工程に先立って、基板２０に対して表面活性化処理を行うことにより、基板２０からの外部電極３等の脱落や浮き上がりを効果的に防止でき、製造工程時の不良品形成率を低減できる。   Next, as shown in FIG. 5 (a), the semiconductor element 2 is mounted on the mounting pad 4 by a known method, and thereafter, as shown in FIG. Are connected by an ultrasonic bonding apparatus or the like using a wire 6 such as a gold wire. Here, when the wire 6 is connected, a pulling force is applied to the external electrode 3 or the like or from the bonding apparatus, and the external electrode 3 or the like tends to float up from the substrate 20, but as described above, prior to the plating step. Thus, by performing the surface activation process on the substrate 20, it is possible to effectively prevent the external electrodes 3 and the like from falling off the substrate 20 and lifting, and to reduce the defective product formation rate during the manufacturing process.

次に、基板２０上の半導体素子２の搭載部分を、図５（ｃ）に示すごとく熱硬化性エポキシ樹脂等の樹脂７でモールドし、基板２０上に樹脂封止体を形成する。具体的には、基板２０の上面側をモールド金型（上型）に装着するとともに、モールド金型内にエポキシ樹脂をキャビティにより圧入した。これにより基板２０上に並列して形成した複数個の半導体素子搭載部が樹脂７により連続して封止された形態となった。なお、このとき基板２０が樹脂モールドの下型の役割を果たす。   Next, the mounting portion of the semiconductor element 2 on the substrate 20 is molded with a resin 7 such as a thermosetting epoxy resin as shown in FIG. 5C to form a resin sealing body on the substrate 20. Specifically, the upper surface side of the substrate 20 was mounted on a mold (upper mold), and epoxy resin was press-fitted into the mold through a cavity. As a result, a plurality of semiconductor element mounting portions formed in parallel on the substrate 20 were continuously sealed with the resin 7. At this time, the substrate 20 serves as a lower mold of the resin mold.

次いで図５（ｄ）に示すごとく、樹脂封止体から基板２０を除去する。基板２０の除去方法としては、強制的に基板を剥離除去する方法の他、例えば基板２０を構成する材質に拠っては、樹脂封止体側への影響の無い溶剤や薬品等により基板２０を溶解除去する方法や研磨除去する方法を採ることができる。なお、かかる基板２０の除去に際しては、フランジ部１２ｂの存在により、外部電極３や搭載パッド４の脱落を効果的に防ぐことができる。すなわち、フランジ部１２ｂの張り出し部分が樹脂７に食い込むため、基板２０の剥離作業時に外部電極３等が基板２０とともに剥がれることを確実に防ぐことができる。また、樹脂封止体に対して外部電極３等が位置ズレしたり、外部電極３等の一部が欠けることも防ぐことができる。   Next, as shown in FIG. 5D, the substrate 20 is removed from the resin sealing body. As a method for removing the substrate 20, in addition to a method for forcibly separating and removing the substrate, for example, depending on the material constituting the substrate 20, the substrate 20 is dissolved by a solvent or a chemical having no influence on the resin sealing body side. A removal method or a polishing removal method can be employed. When removing the substrate 20, the presence of the flange portion 12b can effectively prevent the external electrode 3 and the mounting pad 4 from falling off. That is, since the protruding portion of the flange portion 12b bites into the resin 7, it is possible to reliably prevent the external electrode 3 and the like from being peeled off together with the substrate 20 during the peeling operation of the substrate 20. In addition, it is possible to prevent the external electrode 3 and the like from being misaligned with respect to the resin sealing body, and a part of the external electrode 3 and the like to be missing.

最後に、図６および図５（ｄ）に示すごとく、樹脂封止体に対して切断線Ｘに沿ってダイシングを行うことにより、図１に示すように、一つの半導体素子２と、この半導体体素子２を囲むように配された複数個（６個）の外部電極３と、半導体素子２が載置される搭載パッド４とを備え、これらが樹脂７により封止された半導体装置１を得た。   Finally, as shown in FIG. 6 and FIG. 5D, by dicing the resin sealing body along the cutting line X, as shown in FIG. 1, one semiconductor element 2 and this semiconductor A semiconductor device 1 including a plurality (six) of external electrodes 3 arranged so as to surround the body element 2 and a mounting pad 4 on which the semiconductor element 2 is placed, which are sealed with a resin 7. Obtained.

以上のように、本実施形態に係る半導体装置１においては、外部電極３および搭載パッド４を構成するＣｕ層１２と下方側のＡｕ層１０との間に、Ｎｉ−Ｐ層１１を介在させた。かかるＮｉ−Ｐ層を構成するＮｉ−Ｐは、ＣｕおよびＡｕの両者に対して優れた密着性を示すため、Ａｕの拡散を効果的に防止することができる。これにて、Ａｕ層１０の不用意な剥がれや脱落を確実に防止することができるので、半導体装置１の信頼性向上に貢献できる。   As described above, in the semiconductor device 1 according to the present embodiment, the Ni—P layer 11 is interposed between the Cu layer 12 constituting the external electrode 3 and the mounting pad 4 and the lower Au layer 10. . Since Ni—P constituting such a Ni—P layer exhibits excellent adhesion to both Cu and Au, it is possible to effectively prevent the diffusion of Au. Thus, inadvertent peeling or dropping of the Au layer 10 can be surely prevented, so that the reliability of the semiconductor device 1 can be improved.

なお、Ｃｕ層１２と下方側のＡｕ層１０との間にのみＮｉ−Ｐ層１１を形成し、Ｃｕ層１２と上方側のＡｕ層１３との間にはＮｉ−Ｐ層を形成しなかったのは、以下のような理由に拠る。すなわち、上方側のＡｕ層１３は樹脂７によりモールドされるため、Ａｕ層１３の不用意な脱落等は生じ難い。これに対しては、下方側のＡｕ層１０は、伝達信号の取り出し等に用いられるものであって、半導体装置１の底面から露出しているため、脱落するおそれがあり、万全の拡散防止対策を施す必要がある。以上のような理由から、下方側のＡｕ層１０とＣｕ層１２との間にのみ、Ｎｉ−Ｐ層１１を形成した。上記Ａｕ層１３のほか、ＡｇやＣｕでも良い。   The Ni—P layer 11 was formed only between the Cu layer 12 and the lower Au layer 10, and the Ni—P layer was not formed between the Cu layer 12 and the upper Au layer 13. The reason is as follows. That is, since the upper Au layer 13 is molded with the resin 7, inadvertent dropping of the Au layer 13 is unlikely to occur. On the other hand, the Au layer 10 on the lower side is used for taking out a transmission signal and is exposed from the bottom surface of the semiconductor device 1 and may fall off. It is necessary to apply. For these reasons, the Ni—P layer 11 was formed only between the lower Au layer 10 and the Cu layer 12. In addition to the Au layer 13, Ag or Cu may be used.

外部電極３および搭載パッド４を構成する、Ａｕ層１０・１３、Ｎｉ−Ｐ層１１、Ｃｕ層１２、およびＡｇ層１４は、非磁性金属であるため、本実施形態に係る半導体装置１によれば、外部電極３および搭載パッド４の全体を完全に非磁性化できる。これにて、磁性金属層に由来する磁気的な影響が半導体素子２に及ぶことを確実に防ぐことができるので、半導体素子２の動作不良を防いで、半導体装置１の信頼性向上に貢献できる。
加えて、外部電極３の全体を非磁性化していると、磁性を持つ外部電極においては不可避であった、伝送信号の周波数の増加に伴って導電率が劣化する問題を確実に解消できる。従って、動作周波数や伝送信号の周波数を増加させた場合にも、外部電極３の導電率が低下する不具合は生じず、この点でも信頼性に優れた半導体装置１を得ることができる。 Since the Au layers 10 and 13, the Ni—P layer 11, the Cu layer 12, and the Ag layer 14 that constitute the external electrode 3 and the mounting pad 4 are nonmagnetic metals, the semiconductor device 1 according to the present embodiment is used. Thus, the entire external electrode 3 and mounting pad 4 can be made completely non-magnetic. As a result, it is possible to reliably prevent the magnetic influence derived from the magnetic metal layer from reaching the semiconductor element 2, thereby preventing malfunction of the semiconductor element 2 and contributing to improving the reliability of the semiconductor device 1. .
In addition, if the entire external electrode 3 is made non-magnetic, it is possible to reliably solve the problem that the conductivity deteriorates with an increase in the frequency of the transmission signal, which is unavoidable in the magnetic external electrode. Therefore, even when the operating frequency and the frequency of the transmission signal are increased, there is no problem that the conductivity of the external electrode 3 is reduced, and the semiconductor device 1 having excellent reliability can be obtained in this respect.

外部電極３を構成するＣｕ層１２を、周縁が上下方向に真っ直ぐに伸びるストレート状に伸びるストレート部１２ａと、該ストレート部１２ａの上端から水平方向に張り出し形成されたフランジ部１２ｂとを含むものとしていると、フランジ部１２ｂの張り出し分だけ、Ｃｕ層１２の表面積を大きくできる。これによれば、表面にのみで電流が流れる表皮効果の影響を小さくすることができるので、外部電極３のインピーダンスの増加を抑えて、外部電極３の導電率の低下を抑えることができる。これにて、動作信号等の伝送不能に由来する半導体素子２の動作不良の発生を防ぐことができるので、半導体装置１の信頼性向上に貢献できる。
加えて、最表面層として、導電特性に優れたＡｇ層１４を採用していると、表皮効果の発生を効果的に抑えることができる。 The Cu layer 12 constituting the external electrode 3 includes a straight portion 12a extending in a straight shape whose peripheral edge extends straight in the vertical direction, and a flange portion 12b formed so as to extend horizontally from the upper end of the straight portion 12a. In this case, the surface area of the Cu layer 12 can be increased by the amount of protrusion of the flange portion 12b. According to this, since the influence of the skin effect in which current flows only on the surface can be reduced, an increase in the impedance of the external electrode 3 can be suppressed, and a decrease in the conductivity of the external electrode 3 can be suppressed. As a result, it is possible to prevent the occurrence of malfunction of the semiconductor element 2 due to the inability to transmit operation signals and the like, which can contribute to improving the reliability of the semiconductor device 1.
In addition, when the Ag layer 14 having excellent conductive properties is adopted as the outermost surface layer, the generation of the skin effect can be effectively suppressed.

（第２実施形態） 図７に本発明の第２実施形態に係る半導体装置を示す。そこでは、外部電極３を構成するＣｕ層１２が盤面中央に貫通孔３０を有する中空構造となっている点、および該Ｃｕ層１２上に形成されるＡｕ層１３とＡｇ層１４とが、貫通孔３０を有する中空構造となっている点が先の第１実施形態と相違する。 Second Embodiment FIG. 7 shows a semiconductor device according to a second embodiment of the present invention. There, the Cu layer 12 constituting the external electrode 3 has a hollow structure having a through-hole 30 in the center of the board surface, and the Au layer 13 and the Ag layer 14 formed on the Cu layer 12 are penetrated. The point which becomes the hollow structure which has the hole 30 differs from previous 1st Embodiment.

より詳しくは、Ｃｕ層１２の盤面中央には、貫通孔３０が形成されている。この貫通孔３０は、内径寸法が均一なストレート部３０ａと、ストレート部３０ａの上端に形成されてストレート部３０ａよりも内径寸法の小さな小径部３０ｂと、小径部３０ｂの上方に形成されて、内径寸法が上方に行くに従って漸次大きくなる上拡がりのテーパー部３０ｃとで構成される。テーパー部３０ｃの内周面を含むＣｕ層１２の上面の全体には、Ａｕ層１３とＡｇ層１４とが形成されている。   More specifically, a through hole 30 is formed in the center of the surface of the Cu layer 12. The through-hole 30 is formed at a straight portion 30a having a uniform inner diameter, a small diameter portion 30b formed at the upper end of the straight portion 30a and having a smaller inner diameter than the straight portion 30a, and above the small diameter portion 30b. It is composed of an upwardly expanding tapered portion 30c that gradually increases in size as it goes upward. An Au layer 13 and an Ag layer 14 are formed on the entire upper surface of the Cu layer 12 including the inner peripheral surface of the tapered portion 30c.

図８に、上記半導体装置の製造方法を示す。そこでは、図８（ａ）に示すように、ステンレスやアルミ、銅等の導電性の金属板からなる基板２０の表面に、アルカリタイプの感光性フィルムレジストをラミネートして、フォトレジスト層２１を形成する。次に、フォトレジスト層２１の上面に、搭載パッド４、外部電極３および通孔３０のストレート部３０ａの形成箇所を除く部分に対応する透光孔２２を有するパターンフィルム２３（ガラスマスク）を密着させたのち、紫外光ランプ２４で紫外線光を照射して露光を行う。ここでは、紫外光ランプ２４から上下方向に指向性を有する紫外線光を照射することにより、フォトレジスト層２１に対してストレート状に露光を行った。次いで、乾燥の各処理を行って、未露光部分を溶解除去することにより、図８（ｂ）に示すように、搭載パッド４、外部電極３および通孔３０のストレート部３０ａの形成箇所を除く部分に対応するレジスト体２５ａを有し、搭載パッド４の形成箇所に対応する平面視で四角状の通孔２５ｂと、外部電極３の形成箇所に対応する、平面視で円ドーナツ状の通孔２５ｃを有するパターンレジスト２５を基板２０上に形成する。通孔２５ｂ・２５ｃの内周縁（対向辺の間隔寸法）は、均一なストレート状となるようにした。   FIG. 8 shows a method for manufacturing the semiconductor device. In this case, as shown in FIG. 8 (a), an alkali type photosensitive film resist is laminated on the surface of a substrate 20 made of a conductive metal plate such as stainless steel, aluminum, or copper, and a photoresist layer 21 is formed. Form. Next, a pattern film 23 (glass mask) having a translucent hole 22 corresponding to a portion excluding the place where the mounting pad 4, the external electrode 3, and the straight portion 30 a of the through hole 30 are formed is adhered to the upper surface of the photoresist layer 21. After that, exposure is performed by irradiating ultraviolet light with an ultraviolet lamp 24. Here, the photoresist layer 21 was exposed in a straight shape by irradiating ultraviolet light having directivity in the vertical direction from the ultraviolet lamp 24. Next, each drying process is performed to dissolve and remove the unexposed portions, thereby removing the formation positions of the mounting pads 4, the external electrodes 3, and the straight portions 30a of the through holes 30 as shown in FIG. A through hole 25b having a square shape in a plan view corresponding to a place where the mounting pad 4 is formed, and a circular donut-like through hole corresponding to a place where the external electrode 3 is formed, having a resist body 25a corresponding to the portion. A pattern resist 25 having 25 c is formed on the substrate 20. The inner peripheries (spacing dimensions of the opposing sides) of the through holes 25b and 25c were made to be a uniform straight shape.

続いて、図８（ｃ）に示すように、パターンレジスト３５を利用して、Ａｕ層１０、Ｎｉ−Ｐ層１１、Ｃｕ層１２、Ａｕ層１３、Ａｇ層１４を順にメッキ法により積層することにより、搭載パッド４および外部電極３を形成する（メッキ工程）。Ｃｕ層１２の形成に際しては、Ｃｕをレジスト体２５ａの高さ位置を越えて電着させることで、レジスト体２５ａの高さ位置を越えない箇所には、周縁が上下方向に真っ直ぐに伸びるストレート部１２ａが形成され、レジスト体２５ａの高さ位置を越える箇所には、該ストレート部１２ａの上端から内外の両水平方向に張り出し形成されたフランジ部１２ｂとが形成されるようにする。これにて、Ｃｕ層１２に内径寸法が均一なストレート部３０ａと、ストレート部３０ａの上端に形成されてストレート部３０ａよりも内径寸法の小さな小径部３０ｂと、小径部３０ｂの上方に形成されて、内径寸法が上方に行くに従って漸次大きくなる上拡がりのテーパー部３０ｃとで構成される貫通孔３０を形成することができる。   Subsequently, as illustrated in FIG. 8C, the Au layer 10, the Ni—P layer 11, the Cu layer 12, the Au layer 13, and the Ag layer 14 are sequentially laminated by using the pattern resist 35. Thus, the mounting pad 4 and the external electrode 3 are formed (plating process). When the Cu layer 12 is formed, Cu is electrodeposited beyond the height position of the resist body 25a, so that the periphery of the resist body 25a does not exceed the height position. 12a is formed, and a flange portion 12b is formed at a position exceeding the height position of the resist body 25a, and is formed so as to project from the upper end of the straight portion 12a in both the inner and outer horizontal directions. Thus, the straight portion 30a having a uniform inner diameter size in the Cu layer 12, the small diameter portion 30b formed at the upper end of the straight portion 30a and having a smaller inner diameter than the straight portion 30a, and the small diameter portion 30b are formed. A through hole 30 constituted by an upwardly expanding tapered portion 30c that gradually increases as the inner diameter dimension goes upward can be formed.

次に、図８（ｄ）に示すごとく、パターンレジスト２５（レジスト体２５ａ）を溶解除去して、基板２０上に搭載パッド４と外部電極３とが搭載された中間成形品を得る。以後の半導体素子２の搭載や結線作業等は、図５と同様であるので、その説明は省略する。   Next, as shown in FIG. 8D, the pattern resist 25 (resist body 25 a) is dissolved and removed to obtain an intermediate molded product in which the mounting pad 4 and the external electrode 3 are mounted on the substrate 20. Subsequent mounting of the semiconductor element 2, connection work, and the like are the same as those in FIG.

図９に、第２実施形態の別実施例を示す。そこでは、Ｃｕ層１２の盤面中央に平面視で四角形状の貫通孔３０を形成している。また、貫通孔３０の内周面に沿うように、Ａｕ層１３とＡｇ層１４が形成されている。それ以外の点は、先の図７と同様である。   FIG. 9 shows another example of the second embodiment. There, a rectangular through hole 30 is formed in the center of the surface of the Cu layer 12 in plan view. An Au layer 13 and an Ag layer 14 are formed along the inner peripheral surface of the through hole 30. The other points are the same as in FIG.

本第２実施形態に係る半導体装置１のように、Ｃｕ層１２の盤面中央に貫通孔３０を形成してあると、該貫通孔３０の内周面の面積分だけ、Ｃｕ層１２の表面積を大きくすることができるので、その上面に形成されるＡｇ層１４の表面積を大きくすることができる。これにより、Ａｇ層１４における表皮効果の影響をより小さくすることができるので、外部電極３の導電率の低下を抑えることができる。また、Ａｕ層１３を介したＡｇ層１４とＣｕ層１２との間の接触面積の増大を図ることができるので、この点でも表皮効果の影響を小さくして外部電極３の導電率の低下を抑えることができる。
また、フランジ部１２ｂが樹脂７に食い込むため、樹脂７に対する外部電極３の結合強度の向上を図ることができる。従って、外部電極３の不用意な脱落や位置ずれを確実に防ぐことができる。 When the through hole 30 is formed in the center of the surface of the Cu layer 12 as in the semiconductor device 1 according to the second embodiment, the surface area of the Cu layer 12 is increased by the area of the inner peripheral surface of the through hole 30. Since it can be increased, the surface area of the Ag layer 14 formed on the upper surface thereof can be increased. Thereby, since the influence of the skin effect in Ag layer 14 can be made smaller, the fall of the electrical conductivity of the external electrode 3 can be suppressed. In addition, since the contact area between the Ag layer 14 and the Cu layer 12 via the Au layer 13 can be increased, the influence of the skin effect can be reduced in this respect as well to reduce the conductivity of the external electrode 3. Can be suppressed.
Further, since the flange portion 12b bites into the resin 7, it is possible to improve the bonding strength of the external electrode 3 to the resin 7. Accordingly, it is possible to reliably prevent the external electrode 3 from being accidentally dropped or displaced.

上記実施形態においては、Ｃｕ層１２上には、Ａｕ層１３とＡｇ層１４とが形成されていたが、本発明はこれに限られず、Ｃｕ層１２上には、Ａｕ層、Ａｇ層、Ｐｄ層から選択される一種又は二種以上の層を形成することができる。
表面層１０としては、Ａｕ層のほか、Ｓｎ層やＳｎ−Ａｇ層などであってもよい。
外部電極３の位置や形状等は、上記実施形態に示したものに限られない。
上記第２実施形態に係る半導体装置１においては、Ｃｕ層１２にフランジ部１２ｂを形成していたが、これは無くとも良く、貫通孔３０のみを備える形態であってもよい。 In the above embodiment, the Au layer 13 and the Ag layer 14 are formed on the Cu layer 12. However, the present invention is not limited to this, and the Au layer, the Ag layer, and the Pd layer are formed on the Cu layer 12. One or two or more layers selected from the layers can be formed.
The surface layer 10 may be an Sn layer, a Sn—Ag layer, or the like in addition to the Au layer.
The position, shape, and the like of the external electrode 3 are not limited to those shown in the above embodiment.
In the semiconductor device 1 according to the second embodiment, the flange portion 12b is formed in the Cu layer 12. However, this may be omitted, and the embodiment including only the through hole 30 may be used.

１ 半導体装置
２ 半導体素子
３ 外部電極
４ 搭載パッド
６ ワイヤ
７ 樹脂
１０ 表面層（Ａｕ層）
１１ Ｎｉ−Ｐ層
１２ Ｃｕ層
１３ Ａｕ層
１４ Ａｇ層
２０ 基板
２５ パターンレジスト
２５ａ レジスト体
３０ 貫通孔 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor element 3 External electrode 4 Mounting pad 6 Wire 7 Resin 10 Surface layer (Au layer)
11 Ni-P layer 12 Cu layer 13 Au layer 14 Ag layer 20 Substrate 25 Pattern resist 25a Resist body 30 Through-hole

本発明は、半導体素子２と電気的に接続され、樹脂７により封止されて半導体装置の底面側に露出する外部電極３が基板２０上に搭載された半導体装置用の中間成形品を対象とする。そして、外部電極３が、Ｃｕ層１２を主体としており、加えて一切の磁性金属を具備しないものであり、Ｃｕ層１２の上方側にＡｕ層１３が形成され、Ｃｕ層１２の下方側にＡｕ層１０が形成されており、Ｃｕ層１２と下方側のＡｕ層１０との間にのみＮｉ−Ｐ層１１を形成したことを特徴とする。 The present invention is directed to an intermediate molded product for a semiconductor device in which an external electrode 3 that is electrically connected to a semiconductor element 2, is sealed with a resin 7, and is exposed on the bottom surface side of the semiconductor device is mounted on a substrate 20. To do. The external electrode 3 is mainly composed of the Cu layer 12 and does not include any magnetic metal. The Au layer 13 is formed on the upper side of the Cu layer 12, and the Au layer 13 is formed on the lower side of the Cu layer 12. The layer 10 is formed, and the Ni-P layer 11 is formed only between the Cu layer 12 and the lower Au layer 10 .

半導体素子２が載置され、外部電極３とともに樹脂７により封止される搭載パッド４が基板２０上に搭載されており、搭載パッド４がＣｕ層１２を主体としており、加えて一切の磁性金属を具備しないものであり、Ｃｕ層１２の上方側にＡｕ層１３が形成され、Ｃｕ層１２の下方側にＡｕ層１０が形成されており、Ｃｕ層１２と下方側のＡｕ層１０との間にのみＮｉ−Ｐ層１１が介在されている形態を採ることができる。 A mounting pad 4 on which a semiconductor element 2 is mounted and sealed with a resin 7 together with an external electrode 3 is mounted on a substrate 20. The mounting pad 4 is mainly composed of a Cu layer 12, in addition to any magnetic metal. The Au layer 13 is formed on the upper side of the Cu layer 12, the Au layer 10 is formed on the lower side of the Cu layer 12, and between the Cu layer 12 and the lower Au layer 10. It is possible to adopt a form in which the Ni-P layer 11 is interposed only in the first electrode.

Ｎｉ−ＰにおけるＰの含有率は８〜１４％程度であることが好ましく、９〜１０％が最適である。The P content in Ni-P is preferably about 8 to 14%, and 9 to 10% is optimal.

Ｃｕ層１２が、周縁が上下方向に真っ直ぐに伸びるストレート部１２ａと、該ストレート部１２ａの上端から水平方向に張り出し形成されたフランジ部１２ｂとを含むものとすることができる。また、フランジ部１２ｂの上面が、水平方向の中央部分の厚み寸法が大きく、周縁部に行くに従って厚み寸法が漸次小さくなるドーム状に形成することができる。なおここで言うドーム状とは、図１に示すごとく、フランジ部１２ｂの盤面中央がフラットで、周縁部が水平方向に行くに従って、漸次厚み寸法が小さくなるような形態をも含む概念である。The Cu layer 12 may include a straight portion 12a whose peripheral edge extends straight in the vertical direction, and a flange portion 12b that is formed to protrude in the horizontal direction from the upper end of the straight portion 12a. Further, the upper surface of the flange portion 12b can be formed in a dome shape in which the thickness dimension of the central portion in the horizontal direction is large and the thickness dimension gradually decreases toward the peripheral edge. The dome shape referred to here is a concept including a form in which the center of the surface of the flange portion 12b is flat and the thickness dimension gradually decreases as the peripheral portion goes in the horizontal direction, as shown in FIG.

また本発明は、半導体素子２と、半導体素子２と電気的に接続されている外部電極３とを有し、半導体素子２および外部電極３が樹脂７により封止されている半導体装置を対象とする。そして、外部電極３がＣｕ層１２を主体としており、加えて一切の磁性金属を具備しないものであり、Ｃｕ層１２の上方側にＡｕ層１３が形成され、Ｃｕ層１２の下方側にＡｕ層１０が形成されており、Ｃｕ層１２と下方側のＡｕ層１０との間にのみＮｉ−Ｐ層１１を形成したことを特徴とする。The present invention is also directed to a semiconductor device having a semiconductor element 2 and an external electrode 3 electrically connected to the semiconductor element 2, and the semiconductor element 2 and the external electrode 3 are sealed with a resin 7. To do. The external electrode 3 is mainly composed of the Cu layer 12 and does not include any magnetic metal. The Au layer 13 is formed on the upper side of the Cu layer 12, and the Au layer is formed on the lower side of the Cu layer 12. 10 is formed, and the Ni—P layer 11 is formed only between the Cu layer 12 and the lower Au layer 10.

半導体素子２は、搭載パッド４上に配置され、半導体素子２および外部電極３とともに、樹脂７により封止されており、外部電極３がＣｕ層１２を主体としており、加えて一切の磁性金属を具備しないものであり、Ｃｕ層１２の上方側にＡｕ層１３が形成され、Ｃｕ層１２の下方側にＡｕ層１０が形成されており、Ｃｕ層１２と下方側のＡｕ層１０との間にのみＮｉ−Ｐ層１１が介在されている形態を採ることができる。The semiconductor element 2 is disposed on the mounting pad 4 and is sealed with a resin 7 together with the semiconductor element 2 and the external electrode 3. The external electrode 3 is mainly composed of the Cu layer 12, and any magnetic metal is added. The Au layer 13 is formed on the upper side of the Cu layer 12, the Au layer 10 is formed on the lower side of the Cu layer 12, and between the Cu layer 12 and the lower Au layer 10. Only the Ni-P layer 11 can be employed.

Ｎｉ−ＰにおけるＰの含有率は８〜１４％程度であることが好ましく、９〜１０％が最適である。The P content in Ni-P is preferably about 8 to 14%, and 9 to 10% is optimal.

Ｃｕ層１２が、周縁が上下方向に真っ直ぐに伸びるストレート部１２ａと、該ストレート部１２ａの上端から水平方向に張り出し形成されたフランジ部１２ｂとを含むものとすることができる。また、フランジ部１２ｂの上面が、水平方向の中央部分の厚み寸法が大きく、周縁部に行くに従って厚み寸法が漸次小さくなるドーム状に形成することができる。なおここで言うドーム状とは、図１に示すごとく、フランジ部１２ｂの盤面中央がフラットで、周縁部が水平方向に行くに従って、漸次厚み寸法が小さくなるような形態をも含む概念である。The Cu layer 12 may include a straight portion 12a whose peripheral edge extends straight in the vertical direction, and a flange portion 12b that is formed to protrude in the horizontal direction from the upper end of the straight portion 12a. Further, the upper surface of the flange portion 12b can be formed in a dome shape in which the thickness dimension of the central portion in the horizontal direction is large and the thickness dimension gradually decreases toward the peripheral edge. The dome shape referred to here is a concept including a form in which the center of the surface of the flange portion 12b is flat and the thickness dimension gradually decreases as the peripheral portion goes in the horizontal direction, as shown in FIG.

本発明に係る半導体装置用の中間成形品及び半導体装置においては、外部電極３を構成するＣｕ層１２とＡｕ層１０との間に、Ｎｉ−Ｐ層１１を介在させた。かかるＮｉ−Ｐ層１１を構成するＮｉ−Ｐは、ＣｕおよびＡｕの両者に対して優れた密着性を示すため、Ａｕ層１０の剥がれや脱落を確実に防止することができる。また、このように、Ｃｕ層１２とＡｕ層１０との間にＮｉ−Ｐ層１１を介在させることにより、Ａｕの拡散を効果的に防止することができる。これにて、半導体装置の信頼性の向上を図ることができる。 In the intermediate molded product for a semiconductor device and the semiconductor device according to the present invention, the Ni—P layer 11 is interposed between the Cu layer 12 and the Au layer 10 constituting the external electrode 3. Since Ni-P constituting the Ni-P layer 11 exhibits excellent adhesion to both Cu and Au , it is possible to reliably prevent the Au layer 10 from peeling off or falling off. In addition, the diffusion of Au can be effectively prevented by interposing the Ni-P layer 11 between the Cu layer 12 and the Au layer 10 in this way. Thus, the reliability of the semiconductor device can be improved.

搭載パッド４を構成するＣｕ層１２とＡｕ層１０との間に、Ｎｉ−Ｐ層１１を介在させた場合にも、先の外部電極３と同様の作用効果を得ることができる。すなわち、Ｎｉ−Ｐは、ＣｕおよびＡｕの両者に対して優れた密着性を示すため、搭載パッド４を構成するＡｕ層１０の剥がれや脱落を確実に防止することができる。また、Ｃｕ層１２とＡｕ層１０との間に、Ｎｉ−Ｐ層１１を介在させることにより、Ａｕの拡散を効果的に防止することができる。
加えて、搭載パッド４の全体を非磁性化することができるので、磁気的な影響が半導体素子２に及ぶことは無く、磁気的影響に由来する動作不良が生じることも無い。
ここで、Ｃｕ層１２と下方側のＡｕ層１０との間にのみＮｉ−Ｐ層１１を形成し、Ｃｕ層１２と上方側のＡｕ層１３との間にはＮｉ−Ｐ層を形成しない理由は、上方側のＡｕ層１３は樹脂７によりモールドされるため、Ａｕ層１３の不用意な脱落等は生じ難い。これに対して、下方側のＡｕ層１０は、伝達信号の取り出し等に用いられるものであって、半導体装置１の底面から露出されるため、脱落するおそれがあり、万全の拡散防止対策を施す必要がある。以上のような理由から、下方側のＡｕ層１０とＣｕ層１２との間にのみ、Ｎｉ−Ｐ層１１を形成している。 Even when the Ni-P layer 11 is interposed between the Cu layer 12 and the Au layer 10 constituting the mounting pad 4, the same effects as those of the external electrode 3 can be obtained. That is, since Ni—P exhibits excellent adhesion to both Cu and Au , it is possible to reliably prevent the Au layer 10 constituting the mounting pad 4 from being peeled off or dropped off. Further, by interposing the Ni-P layer 11 between the Cu layer 12 and the Au layer 10, diffusion of Au can be effectively prevented.
In addition, since the entire mounting pad 4 can be made non-magnetic, there is no magnetic influence on the semiconductor element 2, and there is no malfunction caused by the magnetic influence.
Here, the reason why the Ni—P layer 11 is formed only between the Cu layer 12 and the lower Au layer 10, and the Ni—P layer is not formed between the Cu layer 12 and the upper Au layer 13. Since the upper Au layer 13 is molded with the resin 7, inadvertent dropping of the Au layer 13 is unlikely to occur. On the other hand, the Au layer 10 on the lower side is used for taking out a transmission signal and is exposed from the bottom surface of the semiconductor device 1 and thus may fall off. There is a need. For these reasons, the Ni—P layer 11 is formed only between the lower Au layer 10 and the Cu layer 12.

Claims (11)

半導体素子（２）と、該半導体素子（２）と電気的に接続されている外部電極（３）とを有し、これら半導体素子（２）および外部電極（３）が樹脂（７）により封止されている半導体装置であって、
外部電極（３）が、Ｃｕ層（１２）と、該Ｃｕ層（１２）の下方側に形成された表面層（１０）とを含み、加えて一切の磁性金属層を具備しないものであり、
これらＣｕ層（１２）と表面層（１０）との間に、Ｎｉ−Ｐ層（１１）が介在されていることを特徴とする半導体装置。 A semiconductor element (2); and an external electrode (3) electrically connected to the semiconductor element (2). The semiconductor element (2) and the external electrode (3) are sealed with a resin (7). A semiconductor device that is stopped,
The external electrode (3) includes a Cu layer (12) and a surface layer (10) formed on the lower side of the Cu layer (12), and additionally does not include any magnetic metal layer,
A semiconductor device characterized in that a Ni-P layer (11) is interposed between the Cu layer (12) and the surface layer (10). 半導体素子（２）は、搭載パッド（４）上に配置されており、
搭載パッド（４）が、Ｃｕ層（１２）と、該Ｃｕ層（１２）の下方側に形成された表面層（１０）とを含み、加えて一切の磁性金属層を具備しないものであり、
これらＣｕ層（１２）と表面層（１０）との間に、Ｎｉ−Ｐ層（１１）が介在されている請求項１記載の半導体装置。 The semiconductor element (2) is disposed on the mounting pad (4),
The mounting pad (4) includes a Cu layer (12) and a surface layer (10) formed on the lower side of the Cu layer (12), and additionally does not include any magnetic metal layer,
The semiconductor device according to claim 1, wherein a Ni-P layer (11) is interposed between the Cu layer (12) and the surface layer (10). 前記表面層（１０）がＡｕ層である請求項１又は２記載の半導体装置。   The semiconductor device according to claim 1, wherein the surface layer is an Au layer. 外部電極（３）および搭載パッド（４）の少なくともいずれか一方は、表面層（１０）、Ｎｉ−Ｐ層（１１）およびＣｕ層（１２）の順に、各層を積層してなるものであり、
Ｃｕ層（１２）が、周縁が上下方向に真っ直ぐに伸びるストレート部（１２ａ）と、該ストレート部（１２ａ）の上端から水平方向に張り出し形成されたフランジ部（１２ｂ）とを含んでいる請求項１乃至３のいずれかに記載の半導体装置。 At least one of the external electrode (3) and the mounting pad (4) is formed by laminating each layer in the order of the surface layer (10), the Ni-P layer (11), and the Cu layer (12).
The Cu layer (12) includes a straight portion (12a) whose peripheral edge extends straight in the up-down direction and a flange portion (12b) formed so as to extend horizontally from the upper end of the straight portion (12a). The semiconductor device according to any one of 1 to 3. フランジ部（１２ｂ）の上面が、水平方向の中央部分の厚み寸法が大きく、周縁部に行くに従って厚み寸法が漸次小さくなるドーム状に形成されている請求項４記載の半導体装置。   The semiconductor device according to claim 4, wherein the upper surface of the flange portion (12 b) is formed in a dome shape in which the thickness dimension of the central portion in the horizontal direction is large and the thickness dimension gradually decreases toward the peripheral portion. 外部電極（３）は、表面層（１０）、Ｎｉ−Ｐ層（１１）およびＣｕ層（１２）の順に、各層を積層してなるものであり、
Ｃｕ層（１２）は、その盤面中央部に貫通孔（３０）を有する中空構造となっている請求項１乃至５のいずれかに記載の半導体装置。 The external electrode (3) is formed by laminating each layer in the order of the surface layer (10), the Ni-P layer (11), and the Cu layer (12).
The semiconductor device according to any one of claims 1 to 5, wherein the Cu layer (12) has a hollow structure having a through hole (30) in a central portion of the board surface. Ｃｕ層（１２）上に、Ａｕ層（１３）、Ａｇ層（１４）およびＰｄ層から選択される一層又は複数層が形成されている請求項１乃至６のいずれかに記載の半導体装置。   7. The semiconductor device according to claim 1, wherein one or more layers selected from an Au layer (13), an Ag layer (14), and a Pd layer are formed on the Cu layer (12). 半導体素子（２）と、該半導体素子（２）が搭載される搭載パッド（４）と、該半導体素子（２）と電気的に接続される外部電極（３）とを有し、
これら半導体素子（２）、搭載パッド（４）、および外部電極（３）が樹脂（７）により封止されている半導体装置の製造方法であって、
基板（２０）の表面に、搭載パッド（４）および外部電極（３）の形成箇所を除く部分に対応するレジスト体（２５ａ）を有するパターンレジスト（２５）を形成する工程と、 レジスト体（２５ａ）を用いて、基板（２０）上に表面層（１０）、Ｎｉ−Ｐ層（１１）およびＣｕ層（１２）をメッキ法により形成するメッキ工程と、
パターンレジスト（２５）を除去する工程とを含むことを特徴とする半導体装置の製造方法。 A semiconductor element (2), a mounting pad (4) on which the semiconductor element (2) is mounted, and an external electrode (3) electrically connected to the semiconductor element (2),
A method of manufacturing a semiconductor device in which the semiconductor element (2), the mounting pad (4), and the external electrode (3) are sealed with a resin (7),
A step of forming a pattern resist (25) having a resist body (25a) corresponding to a portion excluding the formation position of the mounting pad (4) and the external electrode (3) on the surface of the substrate (20); ) To form a surface layer (10), a Ni-P layer (11) and a Cu layer (12) on the substrate (20) by a plating method,
And a step of removing the pattern resist (25). 前記電鋳工程のＣｕ層（１２）の形成に際しては、電着金属をレジスト体（２５ａ）の高さ位置を超えて電着させることで、Ｃｕ層（１２）に周縁が上下方向に真っ直ぐに伸びるストレート部（１２ａ）と、該ストレート部（１２ａ）の上端から水平方向に張り出し形成されたフランジ部（１２ｂ）とを形成するようになっていること請求項８記載の半導体装置の製造方法。   When forming the Cu layer (12) in the electroforming process, the electrodeposition metal is electrodeposited beyond the height position of the resist body (25a), so that the periphery of the Cu layer (12) is straight in the vertical direction. 9. The method of manufacturing a semiconductor device according to claim 8, wherein an extending straight portion (12a) and a flange portion (12b) extending in a horizontal direction from an upper end of the straight portion (12a) are formed. Ｃｕ層（１２）の形成工程に際しては、フランジ部（１２ｂ）の上面が、水平方向の中央部分の厚み寸法が大きく、周縁部に行くに従って厚み寸法が漸次小さくなるドーム状となるようにしている、請求項９記載の半導体装置の製造方法。   In the process of forming the Cu layer (12), the upper surface of the flange portion (12b) is formed in a dome shape in which the thickness dimension of the central portion in the horizontal direction is large and the thickness dimension gradually decreases toward the periphery. A method for manufacturing a semiconductor device according to claim 9. Ｃｕ層（１２）上に、Ａｕ層（１３）、Ａｇ層（１４）およびＰｄ層から選択される一層又は複数層を形成する工程を含む、請求項８乃至１０のいずれかに記載の半導体装置の製造方法。   The semiconductor device according to claim 8, comprising a step of forming a single layer or a plurality of layers selected from an Au layer (13), an Ag layer (14), and a Pd layer on the Cu layer (12). Manufacturing method.
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