JP2958201B2 - Package for storing semiconductor elements - Google Patents
Package for storing semiconductor elementsInfo
- Publication number
- JP2958201B2 JP2958201B2 JP31332092A JP31332092A JP2958201B2 JP 2958201 B2 JP2958201 B2 JP 2958201B2 JP 31332092 A JP31332092 A JP 31332092A JP 31332092 A JP31332092 A JP 31332092A JP 2958201 B2 JP2958201 B2 JP 2958201B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- electrode
- package
- area
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子を収容するた
めの半導体素子収納用パッケージに関し、より詳細には
内部に収容する半導体素子への電源ノイズの悪影響を有
効に防止するようになした半導体素子収納用パッケージ
の改良に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for accommodating a semiconductor device for accommodating a semiconductor device, and more particularly, to a semiconductor device for effectively preventing a semiconductor device contained therein from being adversely affected by power supply noise. The present invention relates to an improvement in an element storage package.
【０００２】[0002]
【従来の技術】従来、半導体素子を収容するための半導
体素子収納用パッケージは一般に、酸化アルミニウム質
焼結体から成り、上面に半導体素子を収容するための凹
部及び該凹部周辺から外周縁かけて導出するタングステ
ン、モリブデン、マンガン等の高融点金属粉末から成る
メタライズ配線層を有する絶縁基体と、半導体素子の各
電極を外部電気回路に接続するために前記メタライズ配
線層に銀ロウ等のロウ材を介し取着された外部リード端
子と、蓋体とから構成されており、絶縁基体の凹部底面
に半導体素子をガラス、樹脂、ロウ材等の接着剤を介し
て接着固定するとともに各電極をメタライズ配線層にボ
ンディングワイヤを介して電気的に接続し、しかる後、
絶縁基体の上面に蓋体をガラス、樹脂、ロウ材等の封止
材を介して接合させ，絶縁基体と蓋体とから成る容器内
部に半導体素子を気密に封入することによって製品とし
ての半導体装置となる。2. Description of the Related Art Conventionally, a semiconductor element housing package for housing a semiconductor element is generally made of an aluminum oxide sintered body, and has a concave portion for accommodating a semiconductor element on its upper surface and a portion extending from the periphery of the concave portion to the outer peripheral edge. An insulating base having a metallized wiring layer made of a refractory metal powder such as tungsten, molybdenum, or manganese to be derived, and a brazing material such as a silver braze for the metallized wiring layer for connecting each electrode of the semiconductor element to an external electric circuit. The semiconductor device is composed of an external lead terminal attached via an interposer and a lid, and the semiconductor element is bonded and fixed to the bottom surface of the concave portion of the insulating base via an adhesive such as glass, resin, brazing material and the like, and each electrode is metalized wiring. Electrically connected to the layers via bonding wires, and then
A semiconductor device as a product by joining a lid to the upper surface of an insulating base via a sealing material such as glass, resin, brazing material, etc., and hermetically sealing a semiconductor element inside a container including the insulating base and the lid. Becomes
【０００３】尚、かかる従来の半導体素子収納用パッケ
ージは絶縁基体の上面に内部に収容する半導体素子の電
源電極及び接地電極に接続される接続パッドが形成され
ており、該接続パッドにチタン酸バリウム磁器を誘電体
とした容量素子の電極がエポキシ樹脂に銀粉末を充填し
て成る導電性樹脂接着剤を介して直接取着され、半導体
素子の電源電極と接地電極の間に容量素子を接続するこ
とによって半導体素子への電源ノイズの悪影響を有効に
防止するように成っている。In such a conventional package for accommodating a semiconductor element, connection pads are formed on the upper surface of an insulating substrate to be connected to a power supply electrode and a ground electrode of the semiconductor element accommodated therein. The electrodes of the capacitive element using porcelain as a dielectric are directly attached via a conductive resin adhesive made of epoxy resin filled with silver powder, and the capacitive element is connected between the power electrode and the ground electrode of the semiconductor element. As a result, the adverse effect of power supply noise on the semiconductor element is effectively prevented.
【０００４】また前記絶縁基体の上面に形成されている
接続パッドはその面積が通常、容量素子の電極面積に対
し、300 ％以上の広い面積となっている。The area of the connection pad formed on the upper surface of the insulating substrate is generally 300% or more of the area of the electrode of the capacitor.
【０００５】しかしながら、この従来の半導体素子収納
用パッケージは半導体素子を収容する絶縁基体が酸化ア
ルミニウム質焼結体から成り、その熱伝導率が15W/m ・
K と低いこと及び近時、半導体素子は高密度化、高集積
化、高速度化が急激に進み、半導体素子の単位面積、単
位体積当たりの発熱量が増大してきたこと等から絶縁基
体の凹部内に半導体素子を収容し、半導体装置となした
後、半導体素子を作動させると半導体素子が該素子自身
の発する熱によって高温となり、半導体素子に熱破壊を
起こさせたり、特性に熱変化を来し、誤動作させるとい
う欠点を有していた。However, in this conventional package for housing a semiconductor element, the insulating base for housing the semiconductor element is made of an aluminum oxide sintered body and has a thermal conductivity of 15 W / m ·
In recent years, semiconductor devices have rapidly increased in density, integration, and speed, and heat generation per unit area and volume has increased. When a semiconductor device is housed in a semiconductor device and then activated, the semiconductor device is heated to a high temperature due to the heat generated by the device itself, causing thermal destruction of the semiconductor device and a change in characteristics. However, it has a disadvantage of causing a malfunction.
【０００６】そこで上記欠点を解消するために絶縁基体
を酸化アルミニウム質焼結体に変えて熱伝導率が50W/m
・K 以上と極めて熱を伝えやすい窒化アルミニウム質焼
結体で形成し、半導体素子の発する熱を絶縁基体を介し
大気中に良好に放散させることが考えられる。Therefore, in order to solve the above-mentioned drawbacks, the insulating substrate is changed to an aluminum oxide sintered body and the thermal conductivity is reduced to 50 W / m.
-It is conceivable to form the aluminum nitride sintered body which is extremely easy to conduct heat as high as K or more, and to satisfactorily dissipate the heat generated by the semiconductor element to the atmosphere via the insulating base.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、窒化ア
ルミニウム質焼結体で絶縁基体を形成した場合、窒化ア
ルミニウム質焼結体の熱膨張係数は4 〜5 ×10-6/ ℃で
あり、容量素子を絶縁基体に取着する導電性樹脂接着剤
の熱膨張係数(10 〜11×10-6/ ℃) と大きく相違するこ
と及び絶縁基体に形成した接続パッドの面積が容量素子
の面積の約4 倍(400%)であり、両者間に介在する導電性
樹脂接着剤の量が多いこと等から半導体素子の作動時に
発する熱が絶縁基体と導電性接着剤に繰り返し印加され
ると両者の接着部に両者の熱膨張係数の相違に起因する
大きな熱応力が発生し、該熱応力によって導電性接着剤
が絶縁基体より剥離してしまい、その結果、容量素子が
絶縁基体上面より外れ、容量素子によって半導体素子へ
の電源ノイズの悪影響を有効に防止することができなく
なるという欠点を誘発した。However, when the insulating substrate is formed of an aluminum nitride sintered body, the coefficient of thermal expansion of the aluminum nitride sintered body is 4 to 5 × 10 -6 / ° C. Is significantly different from the coefficient of thermal expansion (10 to 11 × 10 −6 / ° C.) of the conductive resin adhesive that attaches the insulating pad to the insulating base, and the area of the connection pad formed on the insulating base is approximately 4% of the area of the capacitor. (400%), and the amount of conductive resin adhesive interposed between them is large, so if the heat generated during the operation of the semiconductor element is repeatedly applied to the insulating base and the conductive adhesive, the bonding portion between the two A large thermal stress is generated due to a difference in thermal expansion coefficient between the two, and the conductive adhesive is separated from the insulating substrate due to the thermal stress. Effectively suppresses adverse effects of power supply noise on semiconductor elements The drawback is that it can no longer be prevented.
【０００８】[0008]
【発明の目的】本発明は上記諸欠点に鑑み案出されたも
ので、その目的は半導体素子への熱の影響及び電源ノイ
ズの影響を有効に防止し、半導体素子を長期間にわたり
正常、且つ安定に作動させることができる半導体素子収
納用パッケージを提供することにある。SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and has as its object to effectively prevent the effects of heat and power supply noise on a semiconductor element and to keep the semiconductor element normal and long-term. It is an object of the present invention to provide a semiconductor device housing package that can be operated stably.
【０００９】[0009]
【課題を解決するための手段】本発明は内部に半導体素
子を収容するための空所を有する窒化アルミニウム質焼
結体から成る絶縁容器の外表面に、内部に収容する半導
体素子の電源電極及び接地電極に接続される接続パッド
を形成するとともに該接続パッドに容量素子の電極を導
電性樹脂接着剤を介して取着して成る半導体素子収納用
パッケージであって、前記絶縁容器に形成した接続パッ
ドの面積を容量素子の電極面積に対し0.6 乃至200 ％と
したことを特徴とするものである。SUMMARY OF THE INVENTION The present invention provides a power supply electrode for a semiconductor element housed inside an insulating container made of an aluminum nitride sintered body having a space for housing a semiconductor element inside. What is claimed is: 1. A semiconductor element storage package comprising: a connection pad connected to a ground electrode; and a capacitor element electrode attached to the connection pad via a conductive resin adhesive. The pad area is 0.6 to 200% of the electrode area of the capacitor.
【００１０】[0010]
【作用】本発明の半導体素子収納用パッケージによれ
ば、絶縁容器を窒化アルミニウム質焼結体で形成したこ
とから半導体素子の作動時に発する熱は容器を介して大
気中に良好に放散され、その結果、容器内部に収容され
る半導体素子は常に低温となり、半導体素子を長期間に
わたり正常、且つ安定に作動させることができる。According to the semiconductor device housing package of the present invention, since the insulating container is formed of the aluminum nitride sintered body, the heat generated during the operation of the semiconductor device is satisfactorily dissipated into the atmosphere through the container. As a result, the temperature of the semiconductor element contained in the container is always low, and the semiconductor element can be operated normally and stably for a long period of time.
【００１１】また絶縁容器の外表面に設けた接続パッド
の面積を容量素子の電極面積に対し0.6 乃至200 ％とし
たこと絶縁容器に容量素子を導電性樹脂接着材を介して
取着した後、絶縁容器と導電性樹脂接着剤に繰り返し熱
が印加されたとしても両者間に発生する熱応力は小さな
ものとなり、その結果、絶縁容器に設けた接続パッドに
導電性接着剤が強固に接合され、容量素子を半導体素子
の電源電極と接地電極間に確実に接続させて半導体素子
への電源ノイズの悪影響を有効に防止することが可能と
なる。The area of the connection pads provided on the outer surface of the insulating container is set to 0.6 to 200% of the electrode area of the capacitor. After the capacitor is attached to the insulating container via a conductive resin adhesive, Even if heat is repeatedly applied to the insulating container and the conductive resin adhesive, the thermal stress generated between them becomes small, and as a result, the conductive adhesive is strongly bonded to the connection pads provided on the insulating container, By connecting the capacitor element between the power supply electrode and the ground electrode of the semiconductor element without fail, it is possible to effectively prevent the adverse effect of power supply noise on the semiconductor element.
【００１２】[0012]
【実施例】次に本発明を添付図面に基づき詳細に説明す
る。BRIEF DESCRIPTION OF THE DRAWINGS FIG.
【００１３】図1 及び図2 は本発明の半導体素子収納用
パッケージの一実施例を示し、1 は絶縁基体、2 は蓋体
である。この絶縁基体1 と蓋体2 とで半導体素子3 を収
容するための容器4 が構成される。FIGS. 1 and 2 show an embodiment of a package for accommodating a semiconductor element according to the present invention, wherein 1 is an insulating base and 2 is a lid. The insulating base 1 and the lid 2 constitute a container 4 for housing the semiconductor element 3.
【００１４】前記絶縁基体1 は窒化アルミニウム質焼結
体から成り、その上面に凹部1aを有し、該凹部1a底面に
は半導体素子3 がガラス、樹脂、ロウ材等の接着剤を介
して接着固定される。The insulating substrate 1 is made of an aluminum nitride sintered body and has a concave portion 1a on its upper surface, and a semiconductor element 3 is bonded to the bottom surface of the concave portion 1a via an adhesive such as glass, resin, brazing material or the like. Fixed.
【００１５】前記窒化アルミニウム質焼結体から成る絶
縁基体1 は例えば、アルミナ(Al 2O 3 ) 、イットリア
(Y2 O 3 ) 、カルシア(CaO) 、マグネシア(MgO) 等の原
料粉末に適当な有機溶剤、溶媒を添加混合して泥漿状と
なすとともにこれを従来周知のドクターブレード法やカ
レンダーロール法等を採用することによってセラミック
グリーンシート( セラミック生シート) を得、しかる
後、前記セラミックグリーンシートに適当な打ち抜き加
工を施すとともに複数枚積層し、高温( 約1800℃) で焼
成することによって製作される。The insulating substrate 1 made of the aluminum nitride sintered body is made of, for example, alumina (Al 2 O 3 ), yttria
(Y 2 O 3 ), calcia (CaO), magnesia (MgO), and other suitable raw materials powders are mixed with an appropriate organic solvent and a solvent to form a slurry, which is then formed into a slurry by a conventionally known doctor blade method, calender roll method, etc. A ceramic green sheet (ceramic green sheet) is obtained by adopting the above method, and thereafter, the ceramic green sheet is manufactured by performing an appropriate punching process, laminating a plurality of sheets, and firing at a high temperature (about 1800 ° C.). .
【００１６】前記窒化アルミニウム焼結体から成る絶縁
基体1 はその熱伝導率が50W/m ・K以上であり、熱を伝
え易いことから半導体素子3 が作動時に多量の熱を発生
したとしてもその熱は絶縁基体1 を介して大気中に良好
に放散され、その結果、半導体素子3 は該素子3 自身の
発する熱によって高温になることは一切なく、半導体素
子3 に熱破壊や特性に熱変化を来し、誤動作を起こさせ
ることはなくなる。The insulating substrate 1 made of the aluminum nitride sintered body has a thermal conductivity of 50 W / m · K or more, and is easy to conduct heat. The heat is satisfactorily dissipated into the atmosphere via the insulating substrate 1, and as a result, the semiconductor element 3 does not become hot due to the heat generated by the element 3 itself. And no malfunction occurs.
【００１７】また前記絶縁基体1 は凹部1a周辺から下面
にかけて複数個のメタライズ配線層5 が被着形成されて
おり、該メタライズ配線層5 の凹部1a周辺部には半導体
素子3 の各電極( 電源電極、接地電極、信号電極) がボ
ンディングワイヤ6 を介して電気的に接続され、また絶
縁基体1 の下面に導出された部位には外部電気回路と接
続される外部リード端子7 が銀ロウ等のロウ材を介し取
着されている。A plurality of metallized wiring layers 5 are formed on the insulating substrate 1 from the periphery to the lower surface of the concave portion 1a, and each electrode (power supply) of the semiconductor element 3 is formed around the concave portion 1a of the metallized wiring layer 5. (Electrodes, ground electrodes, signal electrodes) are electrically connected via bonding wires 6, and an external lead terminal 7 connected to an external electric circuit is provided at a portion led out on the lower surface of the insulating base 1. It is attached via brazing material.
【００１８】前記メタライズ配線層5 はタングステン、
モリブデン、マンガン等の高融点金属粉末から成り、該
タングステン等の高融点金属粉末に適当な有機溶剤、溶
媒を添加混合して得た金属ペーストを絶縁基体1 となる
セラミックグリーンシートに予め従来周知のスクリーン
印刷法により所定パターンに印刷塗布しておくことによ
って絶縁基体1 の凹部1a周辺から下面にかけて被着され
る。The metallized wiring layer 5 is made of tungsten,
A metal paste made of a high melting point metal powder such as molybdenum, manganese or the like, and an appropriate organic solvent or a solvent added to and mixed with the high melting point metal powder such as tungsten is applied to a ceramic green sheet serving as an insulating substrate 1 in a known manner. By printing and applying a predetermined pattern by a screen printing method, the insulating substrate 1 is applied from the periphery of the concave portion 1a to the lower surface.
【００１９】尚、前記メタライズ配線層5 はその露出表
面にニッケル、金等の耐蝕性に優れ、且つロウ材と濡れ
性の良い金属をメッキ法により1.0 乃至20.0μm の厚み
に層着させておくとメタライズ配線層5 の酸化腐食を有
効に防止することができるとともにメタライズ配線層5
とボンディングワイヤ6 との接続及びメタライズ配線層
5 への外部リード端子7 の取着を強固となすことができ
る。従って、メタライズ配線層5 の酸化腐食を防止し、
メタライズ配線層5 とボンディングワイヤ6 及び外部リ
ード端子7 との取着を強固とするにはメタライズ配線層
5 の露出表面にニッケル、金等を1.0 乃至20.0μm の厚
みに層着させておくことが好ましい。The metallized wiring layer 5 is coated with a metal having excellent corrosion resistance such as nickel and gold and a good wettability with a brazing material to a thickness of 1.0 to 20.0 μm on an exposed surface thereof by plating. And the metallized wiring layer 5 can be effectively prevented from being oxidized and corroded.
Between metallization and bonding wire 6 and metallized wiring layer
The attachment of the external lead terminal 7 to the terminal 5 can be made firm. Therefore, oxidation corrosion of the metallized wiring layer 5 is prevented,
To firmly attach the metallized wiring layer 5 to the bonding wires 6 and the external lead terminals 7, the metallized wiring layer
It is preferable to coat nickel, gold, or the like on the exposed surface of No. 5 in a thickness of 1.0 to 20.0 μm.
【００２０】また前記メタライズ配線層5 に銀ロウ等の
ロウ材を介して取着される外部リード端子7 はコバール
金属( 鉄ーニッケルーコバルト合金) や42アロイ( 鉄ー
ニッケル合金) 等の金属材料から成り、外部リード端子
7 を外部電気回路に接続することによって絶縁基体1 の
凹部1a内に収容される半導体素子3 の各電極はメタライ
ズ配線層5 及び外部リード端子7 を介して外部電気回路
に電気的に接続されることとなる。The external lead terminals 7 attached to the metallized wiring layer 5 via a brazing material such as silver brazing are made of a metal material such as Kovar metal (iron-nickel-cobalt alloy) or 42 alloy (iron-nickel alloy). Consisting of an external lead terminal
7 is connected to an external electric circuit, whereby each electrode of the semiconductor element 3 housed in the concave portion 1a of the insulating base 1 is electrically connected to the external electric circuit via the metallized wiring layer 5 and the external lead terminal 7. It will be.
【００２１】前記外部リード端子7 はコバール金属のイ
ンゴット( 塊) を圧延加工法や打ち抜き加工法等、従来
周知の金属加工法を採用することによって所定の形状に
形成される。The external lead terminals 7 are formed in a predetermined shape by employing a conventionally known metal working method such as a rolling method or a punching method for an ingot of a Kovar metal.
【００２２】また前記外部リード端子7 はその露出表面
にニッケル、金等の耐蝕性に優れ、且つロウ材と濡れ性
の良い金属をメッキ法により1.0 乃至20.0μm の厚みに
層着させておくと外部リード端子7 の酸化腐食を有効に
防止することができるとともに外部リード端子7 を半田
等のロウ材を介し外部電気回路に強固に接続することが
可能となる。従って、前記外部リード端子7 はその露出
表面にニッケル、金等を1.0 乃至20.0μm の厚みに層着
させておくことが好ましい。The external lead terminal 7 is preferably formed by plating an exposed surface of a metal having excellent corrosion resistance such as nickel and gold and having good wettability with a brazing material to a thickness of 1.0 to 20.0 μm by plating. Oxidation and corrosion of the external lead terminal 7 can be effectively prevented, and the external lead terminal 7 can be firmly connected to an external electric circuit via a brazing material such as solder. Therefore, it is preferable that nickel, gold, or the like be layered on the exposed surface of the external lead terminal 7 to a thickness of 1.0 to 20.0 μm.
【００２３】前記絶縁基体1 はまたその上面に内部に収
容する半導体素子3 の電源電極及び接地電極に接続され
る接続パッド5aが形成されており、該接続パッド5aには
容量素子8 の電極8aが導電性樹脂接着剤9 を介して取着
されている。On the upper surface of the insulating base 1, there are formed connection pads 5a connected to a power supply electrode and a ground electrode of a semiconductor element 3 housed therein. The connection pads 5a have electrodes 8a of a capacitive element 8 formed thereon. Are attached via a conductive resin adhesive 9.
【００２４】前記接続パッド5aは容量素子8 を絶縁基体
1 上面に取着させるための下地部材として作用するとと
もに容量素子8 を半導体素子3 の電源電極と接地電極の
間に接続させる作用を為し、タングステン、モリブデ
ン、マンガン等の高融点金属粉末により形成されてい
る。The connection pad 5a is used to connect the capacitive element 8 to an insulating base.
(1) Acts as a base member for attachment to the upper surface and acts to connect the capacitive element (8) between the power electrode and the ground electrode of the semiconductor element (3), and is formed of a high melting point metal powder such as tungsten, molybdenum, and manganese. Have been.
【００２５】また前記接続パッド5aはメタライズ配線層
5 と同様の方法によって絶縁基体1の上面に所定形状に
形成される。The connection pad 5a is a metallized wiring layer.
5, a predetermined shape is formed on the upper surface of the insulating base 1.
【００２６】更に前記接続パッド5aは図2(b)に示すよう
にその面積が容量素子8 の電極8aの面積よりも小さくな
っており、これによって接続パッド5aに容量素子8 の電
極8aを導電性樹脂接着剤9 を介して接合させ、容量素子
8 を絶縁基体1 に取着した後、絶縁基体1 と導電性樹脂
接着剤9 に繰り返し熱が印加されたとしても両者間に発
生する熱応力は小さなものとなり、その結果、絶縁基体
1 に設けた接続パッド5aに導電性接着剤9 が強固に接合
され、容量素子8 を半導体素子3 の電源電極と接地電極
間に確実に接続させて半導体素子3 への電源ノイズの悪
影響を有効に防止することが可能となる。Further, as shown in FIG. 2 (b), the area of the connection pad 5a is smaller than the area of the electrode 8a of the capacitor 8 so that the electrode 8a of the capacitor 8 is electrically connected to the connection pad 5a. Bonding via a conductive resin adhesive 9
8 is attached to the insulating base 1, even if heat is repeatedly applied to the insulating base 1 and the conductive resin adhesive 9, the thermal stress generated between them becomes small, and as a result,
The conductive adhesive 9 is firmly bonded to the connection pad 5a provided in 1 and the capacitor 8 is securely connected between the power supply electrode and the ground electrode of the semiconductor element 3 to effectively reduce the adverse effect of power supply noise on the semiconductor element 3. Can be prevented.
【００２７】尚、前記接続パッド5aはその面積が容量素
子8 の電極8a面積に対し、0.6 ％未満であると接続パッ
ド5aと導電性樹脂接着剤9 との接合面積が小さくなりす
ぎて絶縁基体1 に容量素子8 を強固に取着することがで
きなくなり、また200 ％越えると絶縁基体1 に容量素子
8 を取着した後、熱が繰り返し印加されると接続パッド
5aと導電性樹脂接着剤9 との間に大きな熱応力が発生
し、導電性樹脂接着剤9が接続パッド5aから剥離してし
まう。従って、前記接続パッド5aの面積は容量素子8 の
電極8aの面積に対し、0.6 乃至200 ％の範囲に特定され
る。If the area of the connection pad 5a is less than 0.6% of the area of the electrode 8a of the capacitive element 8, the bonding area between the connection pad 5a and the conductive resin adhesive 9 becomes too small, and 1 cannot firmly attach the capacitive element 8, and if it exceeds 200%, the capacitive element 8
8 After mounting, the connection pad will be
A large thermal stress is generated between 5a and the conductive resin adhesive 9, and the conductive resin adhesive 9 peels off from the connection pad 5a. Therefore, the area of the connection pad 5a is specified in the range of 0.6 to 200% of the area of the electrode 8a of the capacitive element 8.
【００２８】また前記接続パッド5aに取着される容量素
子8 は例えば、チタン酸バリウム磁器内に対向電極を多
数埋設して形成され、該容量素子8 は半導体素子3 の誤
動作の原因となる供給電源電圧の変動に起因する電源ノ
イズを除去する作用を為し、これによって半導体素子3
は電源ノイズの悪影響から保護され、長期間にわたり正
常、且つ安定に作動することが可能となる。The capacitive element 8 attached to the connection pad 5a is formed, for example, by embedding a large number of counter electrodes in a barium titanate porcelain. It acts to remove power supply noise caused by fluctuations in power supply voltage.
Is protected from the adverse effects of power supply noise, and can operate normally and stably for a long period of time.
【００２９】更に前記絶縁基体1 に設けた接続パッド5a
と容量素子8 の電極8aとを接合させる導電性樹脂接着剤
9 はエポキシ樹脂に銀粉末を所定量含有させてなり、該
導電性樹脂接着剤9 は容量素子8 を絶縁基体1 上に取着
する作用を為す。Further, connection pads 5a provided on the insulating base 1
Conductive resin adhesive for joining the capacitor 8 and the electrode 8a of the capacitor 8
Reference numeral 9 denotes a predetermined amount of silver powder contained in an epoxy resin, and the conductive resin adhesive 9 acts to attach the capacitive element 8 to the insulating base 1.
【００３０】前記導電性樹脂接着剤9 による容量素子8
の絶縁基体1 上への取着は、絶縁基体1 の上面に設けた
接続パッド5a上に液状の導電性樹脂接着剤9 を塗布し、
次に前記導電性樹脂接着剤9 上に容量素子8 を該素子8
の電極8aが前記接続パッド5aと対向するようにして載置
させ、最後に前記導電性樹脂接着剤9 を約150 ℃の温度
で熱硬化させことによって行われる。The capacitive element 8 made of the conductive resin adhesive 9
Is attached onto the insulating base 1 by applying a liquid conductive resin adhesive 9 onto the connection pads 5a provided on the upper surface of the insulating base 1,
Next, a capacitive element 8 is placed on the conductive resin adhesive 9.
The electrode 8a is placed so as to face the connection pad 5a, and finally, the conductive resin adhesive 9 is thermally cured at a temperature of about 150 ° C.
【００３１】かくして本発明の半導体素子収納用パッケ
ージによれば絶縁基体１の凹部1a底面に半導体素子3 を
ガラス、樹脂、ロウ材等の接着剤を介して接着固定する
とともに半導体素子3 の各電極をメタライズ配線層5 に
ボンディングワイヤ6 を介して電気的に接続し、しかる
後、絶縁基体1 の上面に蓋体2 をガラス、樹脂、ロウ材
等から成る封止材を介して接合させ、絶縁基体1 と蓋体
2 とから成る容器4 内部に半導体素子3 を気密に収容す
ることによって製品としての半導体装置が完成する。Thus, according to the package for accommodating a semiconductor element of the present invention, the semiconductor element 3 is bonded and fixed to the bottom surface of the concave portion 1a of the insulating base 1 with an adhesive such as glass, resin, brazing material or the like. Is electrically connected to the metallized wiring layer 5 via bonding wires 6, and then the lid 2 is joined to the upper surface of the insulating base 1 via a sealing material made of glass, resin, brazing material, etc. Base 1 and lid
The semiconductor device 3 as a product is completed by hermetically housing the semiconductor element 3 inside the container 4 composed of
【００３２】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能である。The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.
【００３３】[0033]
【発明の効果】本発明の半導体素子収納用パッケージに
よれば絶縁容器を窒化アルミニウム質焼結体で形成した
ことから半導体素子の作動時に発する熱は容器を介して
大気中に良好に放散され、その結果、容器内部に収容さ
れる半導体素子は常に低温となり、半導体素子を長期間
にわたり正常、且つ安定に作動させることができる。According to the semiconductor device housing package of the present invention, since the insulating container is formed of an aluminum nitride sintered body, the heat generated during operation of the semiconductor device is satisfactorily radiated to the atmosphere via the container. As a result, the temperature of the semiconductor element housed in the container is always low, and the semiconductor element can be operated normally and stably for a long time.
【００３４】また絶縁容器の外表面に設けた接続パッド
の面積を容量素子の電極面積に対し0.6 乃至200 ％とし
たこと絶縁容器に容量素子を導電性樹脂接着材を介して
取着した後、絶縁容器と導電性樹脂接着剤に繰り返し熱
が印加されたとしても両者間に発生する熱応力は小さな
ものとなり、その結果、絶縁容器に設けた接続パッドに
導電性接着剤が強固に接合され、容量素子を半導体素子
の電源電極と接地電極間に確実に接続させて半導体素子
への電源ノイズの悪影響を有効に防止することが可能と
なる。The area of the connection pads provided on the outer surface of the insulating container is set to 0.6 to 200% of the electrode area of the capacitor. After the capacitor is attached to the insulating container via a conductive resin adhesive, Even if heat is repeatedly applied to the insulating container and the conductive resin adhesive, the thermal stress generated between them becomes small, and as a result, the conductive adhesive is strongly bonded to the connection pads provided on the insulating container, By connecting the capacitor element between the power supply electrode and the ground electrode of the semiconductor element without fail, it is possible to effectively prevent the adverse effect of power supply noise on the semiconductor element.
【図１】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor element storage package according to the present invention.
【図２】(a) は図1 に示すパッケージの容量素子の取着
状態を示す部分拡大断面図、(b) は接続パッドと容量素
子の電極との関係を説明するための図である。2 (a) is a partially enlarged cross-sectional view showing a mounted state of a capacitive element of the package shown in FIG. 1, and FIG. 2 (b) is a view for explaining a relationship between a connection pad and an electrode of the capacitive element.
１・・・・・絶縁基体 ２・・・・・蓋体 ３・・・・・半導体素子 ４・・・・・絶縁容器 ５・・・・・メタライズ配線層 ５ａ・・・・接続パッド ８・・・・・容量素子 ８ａ・・・・容量素子の電極 ９・・・・・導電性樹脂接着剤 DESCRIPTION OF SYMBOLS 1 ... Insulating base 2 ... Lid 3 ... Semiconductor element 4 ... Insulating container 5 ... Metallized wiring layer 5a ... Connection pad 8 ... ··· Capacitance element 8a ··· Electrode of capacitance element 9 ···· Conductive resin adhesive
Claims (1)
有する窒化アルミニウム質焼結体から成る絶縁容器の外
表面に、内部に収容する半導体素子の電源電極及び接地
電極に接続される接続パッドを形成するとともに該接続
パッドに容量素子の電極を導電性樹脂接着剤を介して取
着して成る半導体素子収納用パッケージであって、前記
絶縁容器に形成した接続パッドの面積を容量素子の電極
面積に対し0.6 乃至200 ％としたことを特徴とする半導
体素子収納用パッケージ。A connection connected to a power supply electrode and a ground electrode of a semiconductor element housed on an outer surface of an insulating container made of an aluminum nitride sintered body having a space for housing a semiconductor element inside. A semiconductor element housing package comprising a pad and an electrode of a capacitor attached to the connection pad via a conductive resin adhesive, wherein the area of the connection pad formed on the insulating container is equal to the area of the capacitor. A package for housing a semiconductor element, wherein the package area is 0.6 to 200% of the electrode area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31332092A JP2958201B2 (en) | 1992-11-24 | 1992-11-24 | Package for storing semiconductor elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31332092A JP2958201B2 (en) | 1992-11-24 | 1992-11-24 | Package for storing semiconductor elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06163805A JPH06163805A (en) | 1994-06-10 |
| JP2958201B2 true JP2958201B2 (en) | 1999-10-06 |
Family
ID=18039814
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31332092A Expired - Lifetime JP2958201B2 (en) | 1992-11-24 | 1992-11-24 | Package for storing semiconductor elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2958201B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7348661B2 (en) * | 2004-09-24 | 2008-03-25 | Intel Corporation | Array capacitor apparatuses to filter input/output signal |
-
1992
- 1992-11-24 JP JP31332092A patent/JP2958201B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06163805A (en) | 1994-06-10 |
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