JPS5840339B2 - high frequency transistor - Google Patents
high frequency transistorInfo
- Publication number
- JPS5840339B2 JPS5840339B2 JP50059470A JP5947075A JPS5840339B2 JP S5840339 B2 JPS5840339 B2 JP S5840339B2 JP 50059470 A JP50059470 A JP 50059470A JP 5947075 A JP5947075 A JP 5947075A JP S5840339 B2 JPS5840339 B2 JP S5840339B2
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- insulating plate
- conductive layer
- base
- collector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Description
【発明の詳細な説明】
本発明は、エミッタインダクタンスを減少させた高周波
トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high frequency transistor with reduced emitter inductance.
一般に高周波高出力トランジスタにおいては、エミッタ
インダクタンスの出力に与える影響が大きくなり、特に
１００ ＭＨｚ以上の周波数においては、出力特性を向
上させる上で、エミッタインダクタンスを減少させるこ
とが必須の要件となる。In general, in high-frequency, high-output transistors, the influence of emitter inductance on output becomes large, and particularly at frequencies of 100 MHz or higher, it is essential to reduce emitter inductance in order to improve output characteristics.
従来、この種の高周波トランジスタにおいては、ベース
とコレクタとの間隔を大きく配置して相互の干渉を少な
くしたり、エミッタリードを２本にし、かつ表面積を拡
げてインダクタンスを減少すせるように配慮がなされて
いる。Conventionally, in this type of high-frequency transistor, consideration has been given to reducing inductance by arranging a large distance between the base and collector to reduce mutual interference, and by using two emitter leads and increasing the surface area. being done.
第１図はこのような従来の高周波トランジスタの一例を
示す斜視図であり、図中１は熱伝導度の良好な誘電体支
持基体で、例えばべＩＪ ＩＪヤ磁器が用いられる。FIG. 1 is a perspective view showing an example of such a conventional high-frequency transistor. In the figure, numeral 1 denotes a dielectric support base having good thermal conductivity, and is made of, for example, ceramic.
２．２’、３，４は上記支持基体１の表面に形成された
メラライズ層であり、例えばべＩＪ ＩＪヤ磁器の表面
の所定位置にＭｏ Ｍｎ合金層を付着し、これを水素
雰囲気中で約１０００’Ｃで焼結拡散することにより形
成される。2.2', 3, and 4 are mellized layers formed on the surface of the support base 1, for example, a MoMn alloy layer is attached to a predetermined position on the surface of ceramic, and this is deposited in a hydrogen atmosphere. It is formed by sintering and diffusion at about 1000'C.
なお２゜２′は互いに対向して設けられたエミッタメタ
ライズ層、３はコレクタメタライズ層、４はベースメタ
ライズ層である。Note that 2.degree. 2' is an emitter metallization layer provided facing each other, 3 is a collector metallization layer, and 4 is a base metallization layer.
５は上記エミッタメタライズ層２，２′上にろう材で接
着されたエミッタリード、６は同じくコレクタメタライ
ズ層３上に接着されたコレクタリード、Ｉは同じくベー
スメタライズ層４上に接着されたベースリード、８はそ
の両端を上記エミッタリード５間にコレクタメタライズ
層３をまたがるように掛は渡されたブリッジ、９は例え
ば高周波用トランジスタ素子（以下トランジスタ素子と
呼ぶ）で、上記コレクタメタライズ層３の所定位置にろ
う材で接着されている。5 is an emitter lead bonded on the emitter metallized layer 2, 2' with a brazing material, 6 is a collector lead bonded on the collector metallized layer 3, and I is a base lead bonded on the base metallized layer 4. , 8 is a bridge whose both ends are extended between the emitter leads 5 so as to straddle the collector metallized layer 3; 9 is, for example, a high frequency transistor element (hereinafter referred to as a transistor element); It is glued in place with brazing material.
１０は金あるいはアルミニウムなどからなる細線で、上
記トランジスタ素子９のエミッタ電極（図示せず）とブ
リッジ８間、及びトランジスタ素子９のベース電極（図
示せず）とベースメタライズ層４間を電気的に接続する
ものである。Reference numeral 10 denotes a thin wire made of gold or aluminum, which electrically connects between the emitter electrode (not shown) of the transistor element 9 and the bridge 8, and between the base electrode (not shown) of the transistor element 9 and the base metallized layer 4. It is something that connects.
しかるにこのような構成の高周波トランジスタのエミッ
タ電極を流れる高周波電流は、細線１０を介して更に幾
伺学的形状及び寸法により決まるインダクタンスが比較
的大きいブリッジ８を流れなければならず、前記インダ
クタンスによる高周波特性への悪影響は、高周波になる
ほど無視できなくなってきた。However, the high-frequency current flowing through the emitter electrode of the high-frequency transistor with such a configuration must flow through the thin wire 10 and further through the bridge 8, which has a relatively large inductance determined by the geometrical shape and dimensions, and the high-frequency current due to the inductance is The higher the frequency, the more the negative effect on the characteristics cannot be ignored.
本発明はかかる不都合を改善できる改良された高周波ト
ランジスタを提供するものである。The present invention provides an improved high frequency transistor that can overcome these disadvantages.
本発明は従来の高周波トランジスタの如くインダクタン
スの大きいブリッジを使用しないようにして、入力側に
おけるインダクタンスの値を小さくしたものである。The present invention avoids using a bridge with large inductance as in conventional high frequency transistors, and reduces the value of inductance on the input side.
第２図は本発明における一実施例の斜視図、第３図は第
２図における一実施例の正面図、第４図は第３図におい
てＸ−Ｙ線で切断したときの断面図を示すもので、図中
同じ部分は第１図と同一符号で示している。Fig. 2 is a perspective view of one embodiment of the present invention, Fig. 3 is a front view of the embodiment shown in Fig. 2, and Fig. 4 is a sectional view taken along the X-Y line in Fig. 3. The same parts in the figure are designated by the same reference numerals as in FIG.
この実施例において、１１は例えばべＩＪ ＩＪヤ磁器
等の第１絶縁板で、その上面には第５図に示す如く、コ
レクタ導電層を構成するメタライズ層３及びベース導電
層を構成するメタライズ層４が互いに離間して形成され
ているとともに、コレクタメタライズ層３を形成する領
域中において、トランジスタ素子９に近い部分に窓部１
３が穿設されている。In this embodiment, 11 is a first insulating plate made of ceramic, for example, and on its upper surface, as shown in FIG. 4 are formed spaced apart from each other, and in the region where the collector metallized layer 3 is formed, a window portion 1 is formed in a portion close to the transistor element 9.
3 is drilled.
上記各メタライズ層３および４が延在する第１絶縁板１
１の両端面はそれぞれ一部が切り欠かれており、上記各
メタライズ層３および４は、この切り欠き部の端面まで
連続して設けられている。A first insulating plate 1 on which each of the metallized layers 3 and 4 extends.
Parts of each of both end faces of the metallization layer 1 are cut out, and the metallized layers 3 and 4 are provided continuously up to the end faces of the cutout portions.
１２は第２絶縁板であって、上面には第６図の如く、上
記窓部１３に対向する部分も含めて比較的広い面積にエ
ミッタ導電層を構成するメタライズ層１４が形成され、
またこのエミッタメタライズ層１４とそれぞれ離間して
コレクタメタライズ層１７及びベースメタライズ層１８
が形成されている。Reference numeral 12 denotes a second insulating plate, on the upper surface of which, as shown in FIG.
Further, a collector metallized layer 17 and a base metallized layer 18 are spaced apart from this emitter metallized layer 14, respectively.
is formed.
そして、第１絶縁板１１と第２絶縁板１２とは第４図に
示すように、第２絶縁板１２に形成されたエミッタメタ
ライズ層１４のほぼ全面に及んだ部分を導電性の良い銀
ろう１５などの接着剤で接着され、更に第１絶縁板１１
に形成されたコレクタメタライズ層３及びベースメタラ
イズ層４は、第２絶縁板１２に形成されたコレクタメタ
ライズ層１７及びベースメタライズ層１Ｂに夫々銀ろう
１６でもって接着されるとともに、電気的に接続される
関係にある。As shown in FIG. 4, the first insulating plate 11 and the second insulating plate 12 cover almost the entire surface of the emitter metallized layer 14 formed on the second insulating plate 12 with a highly conductive silver layer. The first insulating plate 11 is bonded with an adhesive such as a wax 15.
The collector metallized layer 3 and the base metallized layer 4 formed on the second insulating plate 12 are adhered to the collector metallized layer 17 and the base metallized layer 1B formed on the second insulating plate 12 with silver solder 16, respectively, and are electrically connected. There is a relationship between
この接着剤である銀ろう１６にはコレクタリード６及び
ベースリード７が夫々接着され、このコレクタリード６
及びベースリード７は、コレクタメタライズ層３及びベ
ースメタライズ層４にそれぞれ電気的に接続されている
。A collector lead 6 and a base lead 7 are bonded to the silver solder 16, which is the adhesive, respectively.
and base lead 7 are electrically connected to collector metallized layer 3 and base metallized layer 4, respectively.
しかして、第２図あるいは第４図かられかるように、第
１絶縁板１１上に形成されたコレクタメタライズ層３上
に保持されたトランジスタ９のエミッタ電極と銀ろう１
５とは、第１絶縁板１１に設けられた窓部１３を利用し
て細線１０でもって接続されている。As can be seen from FIG. 2 or 4, the emitter electrode of the transistor 9 held on the collector metallized layer 3 formed on the first insulating plate 11 and the silver solder 1
5 is connected by a thin wire 10 using a window 13 provided in the first insulating plate 11.
従ってトランジスタ９のエミッタ電極と第２絶縁板１２
に形成されたメタライズ層１４とは、窓部１３を利用し
て電気的に接続した関係にある。Therefore, the emitter electrode of the transistor 9 and the second insulating plate 12
The metallized layer 14 formed thereon is electrically connected to the metallized layer 14 using the window portion 13.
しかるに、この実施例において、例えば高周波入力信号
は、第２絶縁板１２に形成されたエミッタメタライズ層
１４に流れ窓部１３を設けて出来るだけ短かくした細線
１０を通してトランジスタ９のエミッタ電極部に流れる
。However, in this embodiment, for example, a high frequency input signal flows to the emitter electrode portion of the transistor 9 through the thin wire 10 which is made as short as possible by providing a flow window portion 13 in the emitter metallized layer 14 formed on the second insulating plate 12. .
それ故、第１図に示す従来装置のようにブリッジ８を使
用しないため、入力側インダクタンスの値を小さくでき
るので、特に高周波領域における電気的特性の劣化を軽
減することができる。Therefore, since the bridge 8 is not used as in the conventional device shown in FIG. 1, the value of the input side inductance can be reduced, so that deterioration of electrical characteristics, especially in the high frequency region, can be reduced.
実際に、第２図に示す本発明装置は、第１図に示す従来
装置に比して利得を約１０％以上の改善することができ
た。In fact, the device of the present invention shown in FIG. 2 was able to improve the gain by about 10% or more compared to the conventional device shown in FIG.
次に、入力側の不整合によりトランジスタに流入する信
号入力は減少するので、この信号入力の減少を軽減する
ための整合回路を付加する場合には、第７図に示すよう
な構成が提案される。Next, the signal input flowing into the transistor decreases due to mismatching on the input side, so when adding a matching circuit to alleviate this decrease in signal input, a configuration as shown in Figure 7 is proposed. Ru.
この第７図は、入力整合回路を付加した本発明装置に係
る斜視図を示したものである。FIG. 7 shows a perspective view of the device of the present invention to which an input matching circuit is added.
１９は整合回路で、簡単な場合にはコンデンサ等の容量
素子を使用して高周波入力信号の利得の減少を補償する
ものである。Reference numeral 19 denotes a matching circuit which, in a simple case, uses a capacitive element such as a capacitor to compensate for a decrease in the gain of the high frequency input signal.
第１絶縁板１１には第８図に示すように、第２図におい
て設けた窓部１３の他に新たに窓部２０をコレクタメタ
ライズ層３とベースメタライズ層４との間の位置に設け
ている。As shown in FIG. 8, in the first insulating plate 11, in addition to the window portion 13 provided in FIG. 2, a new window portion 20 is provided at a position between the collector metallized layer 3 and the base metallized layer 4. There is.
そして、整合回路１９は第２絶縁板１２に形成されたエ
ミッタメタライズ層１４に保持され、この整合回路１９
は窓部２０を利用してトランジスタ９とベースメタライ
ズ層４とに夫々細線１０でもって接続されている。The matching circuit 19 is held by the emitter metallized layer 14 formed on the second insulating plate 12, and the matching circuit 19
are connected to the transistor 9 and the base metallized layer 4 by thin wires 10 using the window portions 20, respectively.
２１は補助部材で、一方の面ば第１絶縁板１１に接着さ
れ、他方の面には第９図に示すように周辺部にＡｕ−８
ｎ共晶はんだ等の接着剤２２が形成されており、この接
着剤２２はキャップ（図示せず）を接着するためのもの
である。Reference numeral 21 denotes an auxiliary member, one surface of which is glued to the first insulating plate 11, and the other surface with Au-8 around the periphery as shown in FIG.
An adhesive 22 such as n-eutectic solder is formed, and this adhesive 22 is for adhering a cap (not shown).
２３は銅などから成るスフラドで、熱放散効果を高める
ためのものである。Reference numeral 23 is a sufrado made of copper or the like, and is used to enhance the heat dissipation effect.
なお上記実施例においては、第１及び第２絶縁板に形成
される各導電層３，４，１４，１７゜１Ｂをメタライズ
層としたがこれに限られることなく、薄く平面状に延び
た導電板をろう材等で付着するようにしてもよい。In the above embodiment, each of the conductive layers 3, 4, 14, 17°1B formed on the first and second insulating plates is a metallized layer, but the present invention is not limited to this. The plate may be attached using a brazing material or the like.
以上説明したように本発明装置は、第１絶縁板の上面に
コレクタ導電層を形成し、このコレクタ導電層上にトラ
ンジスタ素子を保持し、さらにこのトランジスタ素子に
近い位置で第１絶縁板に窓部を設け、この窓部を利用し
てトランジスタ素子のエミッタ電極と第２絶縁板の上面
に形成されたエミッタ導電層とを金属細線で電気的に接
続したので、入力側における入力インダクタンスの値を
従来装置に比して相当小さくすることができるため、高
周波領域における利得の低下を軽減することができる。As explained above, in the device of the present invention, a collector conductive layer is formed on the upper surface of a first insulating plate, a transistor element is held on this collector conductive layer, and a window is formed in the first insulating plate at a position close to the transistor element. Since the emitter electrode of the transistor element and the emitter conductive layer formed on the upper surface of the second insulating plate are electrically connected by a thin metal wire using this window, the value of the input inductance on the input side can be Since it can be made considerably smaller than conventional devices, it is possible to reduce the decrease in gain in the high frequency region.
この効果は高周波領域になるほど顕著であり、高周波高
出力化が進むにつれ、高周波高出力用として有効である
。This effect becomes more pronounced as the frequency range increases, and as the frequency and output increases, it becomes effective for high-frequency and high-output applications.
また、第１絶縁板と第２絶縁板とを接着するろう材を上
記金属細線の接続用に兼用したから、構造が簡略になる
。Further, since the brazing material for bonding the first insulating plate and the second insulating plate is also used for connecting the thin metal wire, the structure is simplified.
第１図は従来装置の斜視図、第２図は本発明装置の一実
施例を示す斜視図、第３図は本発明装置の平面図、第４
図は第３図においてＸ−Ｙ線で切断したときの断面図、
第５図及び第６図は第１および第２絶縁板の表面に形成
された導電層のパターン説明図、第７図は本発明装置に
整合回路を付加した場合の実施例の斜視図、第８図は第
７図に示す装置の第１絶縁板における導電層のパターン
説明図、第９図は補助部材の平面図である。
図中同一部分あるいは相当部分には同一符号を付してい
る。
図において、３・・・・・・コレクタ導電層、４・・・
・・・ベース導電層、５・・・・・・エミツクリード、
６・・・・・・コレクタリード、７・・・・・・ベース
リード、９・・・・・・トランジスタ素子、１０・・・
・・・金属細線、１１・・・・・・第１絶縁板、１２・
・・・・・第２絶縁板、１３・・・・・・窓部、１４は
エミッタ導電層、１５・・・・・・ろう材。Fig. 1 is a perspective view of a conventional device, Fig. 2 is a perspective view showing an embodiment of the device of the present invention, Fig. 3 is a plan view of the device of the present invention, and Fig. 4 is a perspective view of a conventional device.
The figure is a cross-sectional view taken along the X-Y line in Figure 3,
5 and 6 are explanatory diagrams of patterns of conductive layers formed on the surfaces of the first and second insulating plates, FIG. 7 is a perspective view of an embodiment in which a matching circuit is added to the device of the present invention, and FIG. FIG. 8 is an explanatory diagram of the pattern of the conductive layer on the first insulating plate of the device shown in FIG. 7, and FIG. 9 is a plan view of the auxiliary member. Identical or equivalent parts in the figures are designated by the same reference numerals. In the figure, 3... Collector conductive layer, 4...
... Base conductive layer, 5 ... Emitsukreed,
6...Collector lead, 7...Base lead, 9...Transistor element, 10...
...Thin metal wire, 11...First insulating plate, 12.
... second insulating plate, 13 ... window section, 14 emitter conductive layer, 15 ... brazing material.
Claims (1)
に延びたコレクタ導電層およびベース導電層を形成し、
上記コレクタ導電層上にトランジスタ素子を接着すると
ともに、上記第１絶縁板の上記トランジスタ素子に近い
所定位置に窓部を形成し、上面における上記窓部に対向
する部分を含めた所定部にエミッタ導電層が形成された
第２絶縁板を、上記第１絶縁板の下面に導電性の良いろ
う材を用いて接着し、上記トランジスタ素子のエミッタ
電極と上記ろう材とを、上記窓部を利用して金属細線で
接続することにより、上記エミッタ電極を上記エミッタ
導電層に電気的に接続するとともに、上記トランジスタ
素子のベース電極と上記ベース導電層とを金属細線で接
続し、上記コレクタ導電層、ベース導電層およびエミッ
タ導電層にそれぞれコレクタリード、ベースリードおよ
びエミッタリードを電気的に接続して戒る高周波トラン
ジスタ。1. A collector conductive layer and a base conductive layer are formed at predetermined portions on the upper surface of the first insulating plate, spaced apart from each other and extending in a plane.
A transistor element is bonded onto the collector conductive layer, a window is formed at a predetermined position of the first insulating plate near the transistor element, and an emitter conductor is formed in a predetermined portion of the upper surface including a portion facing the window. A second insulating plate on which a layer has been formed is adhered to the lower surface of the first insulating plate using a brazing material with good conductivity, and the emitter electrode of the transistor element and the brazing material are connected using the window part. The emitter electrode is electrically connected to the emitter conductive layer by connecting with a thin metal wire, and the base electrode of the transistor element and the base conductive layer are connected with a thin metal wire. A high-frequency transistor whose collector lead, base lead, and emitter lead are electrically connected to the conductive layer and emitter conductive layer, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50059470A JPS5840339B2 (en) | 1975-05-19 | 1975-05-19 | high frequency transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50059470A JPS5840339B2 (en) | 1975-05-19 | 1975-05-19 | high frequency transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS51135367A JPS51135367A (en) | 1976-11-24 |
| JPS5840339B2 true JPS5840339B2 (en) | 1983-09-05 |
Family
ID=13114217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50059470A Expired JPS5840339B2 (en) | 1975-05-19 | 1975-05-19 | high frequency transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5840339B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6195844A (en) * | 1984-10-13 | 1986-05-14 | Mazda Motor Corp | Gate type machining center |
| JPH0247140U (en) * | 1988-09-26 | 1990-03-30 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4979467A (en) * | 1972-11-03 | 1974-07-31 |
-
1975
- 1975-05-19 JP JP50059470A patent/JPS5840339B2/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4979467A (en) * | 1972-11-03 | 1974-07-31 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6195844A (en) * | 1984-10-13 | 1986-05-14 | Mazda Motor Corp | Gate type machining center |
| JPH0247140U (en) * | 1988-09-26 | 1990-03-30 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS51135367A (en) | 1976-11-24 |
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