JPS605055B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure that is effective for semiconductor substrates, particularly containers for high frequency, high power transistors.

In a container for a high-frequency, high-output transistor, especially a container equipped with a plurality of electronic circuit elements such as a high-frequency, high-output transistor with a built-in internal matching circuit, it is desirable that the insulator constituting the container be small, and It is desirable that the dew conduction pattern provided on the body be arranged closely.

Therefore, the plurality of electronic circuit elements housed in the container must of course be housed in a steel-tight manner, and the electronic circuit elements and the conductive pattern must be electrically and efficiently connected using metal pongee wire or the like. There is a need. In this case, the grounding inductance becomes a particular problem, and the flow of the brazing material when storing and fixing it in the container also becomes a problem.

The purpose of the present invention is to solve these problems, and its specific contents are as follows. 1st
2 and 2 are partial plan views showing the structure of a transistor housed in a conventional semiconductor container.
a, lb, 6, 10 are bonding lines, 2 is a transistor chip, 3, 3a, 8 are metallization layers, 4a, 4b are ground metallizations, 5 is an output metallization, 9 is a capacitor, and 11 is an input metallization.

Today, containers for high-frequency, high-output transistors with a frequency of 300 nm or more need to have short grounding bonding lines in order to reduce grounding inductance, and have a structure that allows wiring of a large number of bonding lines.

For this reason, as shown in FIGS. 1 and 2, a method is generally used in which bonding lines la and lb are wired from the ground electrode on the transistor chip 2 to the left and right sides of the chip, or to both sides of the chip, straddling the chip. Therefore, this method can be said to be effective in the sense that the mutual inductance between the bonding lines on both sides can be kept extremely small. However, normally, the shape of the transistor chip 2 becomes elongated as it becomes a high-output element, and in order to bond a chip with this shape using the same method, the shape of the collector metallization layer 3 for mounting the chip must also be elongated. Moreover, it is necessary to have ground metallization 4a, 4b on both sides thereof.
Due to the above constraints, from the collector metallized layer 3 for chip mounting to the output lead metallized layer 5 as an output terminal.
It is more convenient to use the bonding wire 6 for connection up to the point than the usual method using a metallized layer. This collector ponding method is also preferable in terms of reducing the output capacitance. In such a structure, for the sake of ease of assembly and reliability of the element, the adhesive may flow to the part where adhesive bonding is performed to fix the element chip to the metallization, and the bonding wire 6 may not be able to be bonded.

In order to prevent such bonding defects, the collector metallization 3 is formed into an elongated shape as shown in FIG. A protrusion is provided on the protrusion, a bonding pad 3a is formed on the protrusion, and a bonding wire 6 is bonded to the bonding pad 3a. In either case, the distance between the bonding 6 and the transistor chip 2 increases, resulting in an increase in collector lead-out resistance, resulting in increased loss and deterioration of high frequency characteristics. An object of the present invention is to provide a semiconductor device which has a structure in which an adhesive for bonding a transistor chip does not flow into the bonding part of a metallized layer on which a transistor chip is mounted, has a small collector lead-out resistance, and has excellent high frequency characteristics. be.

Hereinafter, the present invention will be explained in detail based on Examples.

Figures 3a and 3b are a plan view and a sectional view, respectively, showing an embodiment of the present invention.

As shown in the figure, metallization 8 for the collector bonding pad is formed on the collector metallization 3 through a flow prevention material 7 of brazing material such as ceramic, and the collector metallization 3 and metallization 8 for the pad are through-holes. More suitable for halls. If this pad metallization is formed into an elongated shape with a length of several degrees and a width of about 0.3, the ground bonding line lb can be wired as short as in the conventional structure. Further, the adhesive material when mounting the chip is shielded by the ceramic 7, and there is no risk that the collector bonding pad portion will be contaminated by the adhesive material, so the collector metallization 3 may be designed to be slightly larger than the element chip. Therefore, an increase in parasitic capacitance due to a somewhat increased pad metallization area compared to the conventional structure can be sufficiently compensated for. This structure allows collector bonding lines 6 to be arranged alternately with each ground bonding line lb, and it is possible to perform collector bonding in the same number as or more than the number of ground bonding lines.

In other words, the number and electrical length of collector bonding lines per transistor unit can be kept constant.
The structure is such that, in principle, increases in current capacity, potential drop, and non-uniformity in electrical length due to high output do not occur, and a container can be realized that allows high output elements to pass through.

Note that the bonding portion 8 or 8' is connected to the metallized layer 8 and 3, 8 in order to prevent the resistance of the metallized layer from increasing as much as possible.
' and 4a are preferably connected by providing a plurality of holes or slits in the brazing material flow prevention material 7. In addition, in this embodiment, an example in which metallization for a bonding pad is formed on a collector metallized portion is described, but it is not limited to collector bonding, and bonding in a portion where adhesive material may flow, for example, as shown in FIG. , the structure according to the present invention, such as the capacitor 9 in FIG. It is not intended to limit.

The container of the present invention can be easily manufactured using the well-known green sheet method or ceramic printing method.

[Brief explanation of the drawing]

1 and 2 are plan views showing the structure of a transistor housed in a subordinate semiconductor container, and FIGS. 3 a and 3 b are a plan view and a sectional view showing the basic structure of the present invention, respectively. . 1: bonding wire, 2: transistor chip, 3: metallization layer, 4: ground metallization, 5: output metallization, 6: bonding wire, 7: brazing material flow prevention material, 8
: Metallized layer for collector bonding, 9: Capacitor, 10: Bonding line, 11: Metallized for input,
12: Ceramic. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. A semiconductor element, a surface insulating substrate, a metal layer formed on the surface insulating substrate and bonding the semiconductor element,
an insulating member having a through hole provided on the metal layer in a portion other than the portion to which the semiconductor element is bonded; and a bonding region formed on the insulating member so as to be continuous with the metal layer via the through hole. A semiconductor device comprising: