JPS6327859B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device used in a high frequency band, and particularly to a high output semiconductor device in which two or more transistor chips are mounted in one package.

The field of high-frequency, high-power transistors in the VHF and UHF bands is currently making remarkable progress, and is now several hundred W.
There are now devices that can output power exceeding this amount.
In the prior art, the way to achieve this trend toward higher output power has been to house a large number of transistor chips in one package and arrange them in parallel.

However, with this structure, the parasitic reactance associated with the transistor chip and the conductive wires (bonding wires) inside the package lowers the transistor's input/output impedance level, narrows the transistor's operating band width, causes power loss, and ultimately This had the disadvantage of adversely affecting impedance matching ability.

Therefore, an object of the present invention is to provide a structure of a semiconductor device having a good impedance level, and it is possible to obtain a semiconductor device having a high input/output impedance that satisfies wide bandwidth, high power, and simplification of external circuits. It will be done.

The semiconductor device of the present invention includes at least one dielectric member in a container, and a pair of inputs comprising a first conductive input section and a second conductive input section separately provided on the dielectric member. a pair of output parts each consisting of a first conduction output part and a second conduction output part provided separately on the dielectric member, and a first conduction output part;
a first metallized pattern on which a transistor chip is mounted, and a second metallized pattern on which a second transistor chip is mounted;
a conductive input of a first transistor chip;
The conductive outputs of the transistor chips are arranged in a straight line, and likewise the second conductive inputs, the second transistor chip,
The second conducting output is also arranged in parallel and in a straight line. Each input and output electrode of the first and second transistor chips is connected to an opposing conductive input and conductive output by a bonding line. Furthermore, a pair of conductive ground portions are provided between the pair of input portions and the pair of output portions so as to sandwich the first and second transistor chips, and the pair of conductive ground portions are It is provided on the dielectric member and connected to an external ground plane through a through hole. The ground electrodes (common electrodes) of the first and second transistor chips are bonded to the pair of conductive ground portions, and the bonding line is parallel to a straight line connecting the conductive input portion and the conductive output portion. established in

Basically, the semiconductor device of the present invention may have any structure as long as it satisfies the above structure, but it is preferable that the conductive input section and the conductive output section are arranged symmetrically with respect to a pair of conductive ground portions. Further, when the first and second transistor chips are placed on the first and second conductive output parts, the conductive ground parts are not paired, but the conductive input part and the conductive output part These may be separated between the two.
Furthermore, when the electrodes on the transistor chip are bonded together via a conductive ground, a bonding line is fabricated to bridge the conductive ground.

According to the present invention, a plurality of transistor chips can be combined into one
In a high-power semiconductor device housed in a single container, a conduction input section and a conduction output section related to each transistor chip are arranged in a straight line, and a conduction ground section is provided to cross this.
This conductive ground portion is designed to be operationally shared by all transistor chips. Furthermore, the conductive ground portion is connected to the external ground plane via a through hole. As a result, high input/output impedance and broadband characteristics can be obtained, and parasitic reactance can also be significantly reduced. In particular, if a through hole is provided in a common conductive grounding part, multiple grounding electrode pads of a transistor chip are connected to the conductive grounding part by bonding wires, etc. There is an advantage that the electrical length of the external electrode pad and the external ground plane can be made almost equal. This makes it possible to stabilize high frequency operation, increase output, and increase gain.

That is, the present invention can provide a semiconductor device in which two or more transistor chips fixed to a common dielectric having high thermal conductivity can easily constitute a push-pull circuit type. Here, when the area of the transistor chip is the same, by using the semiconductor device based on the present invention in a push-pull circuit system, both the input impedance and the output impedance are four times as large as those using the conventional simple parallel transistor system. becomes. When the mounting technology of the present invention is used, the circuit configuration is simplified due to the high input impedance and output impedance.
Power losses are reduced resulting in higher power levels and wider bandwidth.

An embodiment of the present invention will be described in detail below with reference to the drawings. The transistor package of this embodiment includes a wafer 10 made of a thermally conductive ceramic, such as beryllia, on which separate metal parts or pads are deposited according to known metallization techniques. This metal part is a pair of input parts 12, 14.
including. Input terminals 16 and 18 are attached to metal input portions 12 and 14, respectively. A pair of output portions 20, 22 are also deposited on wafer 10. The long axis of the output parts 20 and 22 is the input part 1
It almost coincides with the corresponding long axes of Nos. 2 and 14. Output terminals 24 and 26 are connected to output portions 20 and 22, respectively.
is attached to. Furthermore, a pair of metallized portions 28, 30 for mounting transistor chips are also deposited on the wafer 10. Here, the metallized part 28 is arranged between the input and output parts 12 and 20, and the metallized part 30 is arranged between the input and output parts 14 and 22. The common ground plane in this example consists of a pair of metal ground portions 32,34. These grounding portions are deposited on the wafer 10 and are located between the input portion and the output portion and are positioned approximately perpendicular to the longitudinal direction of the input and output portions. Further, through holes 36 and 38 provided in the wafer 10 are provided in the common ground portions 32 and 34 to connect the wafer 1
0 to allow electrical connection to an external ground plane attached to the ground plane. In other words, in order to enable the above connection,
Metallization is applied inside the through holes 36 and 38 up to the bottom surface of the wafer 10. Furthermore, a pair of transistor chips 40 and 42 are mounted on the metallized parts 28 and 30, respectively, and the input electrode pad and the ground electrode pad on the chip are connected to each other by bonding wires 44, and the input electrode pad is connected to the input part 12, connected to 14,
A grounding electrode pad is connected to the grounding portions 32,34.

With this structure, the parasitic reactance at the ground portion is significantly reduced, and at the same time, the stray capacitance between the input and output is also reduced. Furthermore, signal leakage and interference between adjacent transistor chips can be effectively prevented. As a result, it is possible to achieve a wide band, high gain, and high input/output impedance with little power loss.

Incidentally, when the transistor chips 40, 42 are placed on the output conductive part, the ground conductive part 34 can be omitted.

[Brief explanation of the drawing]

FIG. 1 shows a configuration diagram of a semiconductor device according to an embodiment of the present invention. 10...ceramic wafer such as beryllia, 1
2, 14...a pair of conductive parts for input, 16, 18
...One pair of input pull-out leads, 20, 22...
...1 pair of output conductive parts, 24, 26...1 pair of output lead-out leads, 28, 30...1 pair of transistor mounting metallized parts, 32, 34...
common ground conductive part, 36, 38... through hole, 40, 42... a pair of transistor chips,
44...Bonding wire.

Claims (1)

[Claims] A set of a metal layer for output, a metal layer for mounting a semiconductor chip, and a metal layer for input are arranged on a dielectric substrate in a straight line. A plurality of metal layer sets are arranged in parallel in the same order, and the dielectric substrate between the input metal layer and the semiconductor chip mounting metal layer of each set has a continuous layer. A common grounding metal layer is provided, and each set of the input metal layer and each set of the semiconductor chip mounting metal layer are prevented from directly facing each other by the grounding metal layer, and The grounding metal layer is provided with a grounding potential through a through hole formed in the dielectric substrate in a portion where the grounding metal layer is provided,
A semiconductor device characterized in that the input electrode and the output electrode of the semiconductor chip attached to each set of the semiconductor chip mounting metal layer are electrically connected to the input metal layer and the output metal layer of each set, respectively. .