JP2534841B2 - Envelope for microwave integrated circuit - Google Patents

Envelope for microwave integrated circuit

Info

Publication number
JP2534841B2
JP2534841B2 JP6260921A JP26092194A JP2534841B2 JP 2534841 B2 JP2534841 B2 JP 2534841B2 JP 6260921 A JP6260921 A JP 6260921A JP 26092194 A JP26092194 A JP 26092194A JP 2534841 B2 JP2534841 B2 JP 2534841B2
Authority
JP
Japan
Prior art keywords
input
integrated circuit
terminal
microwave integrated
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP6260921A
Other languages
Japanese (ja)
Other versions
JPH07231051A (en
Inventor
清裕 柴田
寿一 尾崎
重和 堀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP6260921A priority Critical patent/JP2534841B2/en
Publication of JPH07231051A publication Critical patent/JPH07231051A/en
Application granted granted Critical
Publication of JP2534841B2 publication Critical patent/JP2534841B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はマイクロ波帯周波数で用
いられる半導体装置を収容するマイクロ波集積回路の外
囲器に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an envelope of a microwave integrated circuit which accommodates a semiconductor device used in a microwave band frequency.

【0002】[0002]

【従来の技術】マイクロ波帯周波数で用いられる半導体
装置として、GaAs等の半絶縁性の半導体基板上に整
合回路やバイアス回路あるいはFET等の半導体素子を
一体化するモノリシック・マイクロ波集積回路(以下M
MICと称す)は小形化,軽量化,量産時の低価格化の
点で注目されている。このMMICは信頼性の点から気
密封じの外囲器に組込む必要があり、一般にマイクロ波
回路で使用する外囲器としては、入出力リード部がマイ
クロストリップ線路を形成していて、かつ側壁部が3層
構造になっているものが多い。しかしながらこの外囲器
は高周波入出力部での寄生リアクタンスが小さいという
長所はあるが、価格が非常に高いという欠点がある。そ
こで低価格の外囲器としては、現在デジタル集積回路等
に広く用いられている外囲器がありこの外囲器にMMI
Cチップを組込んだ構造を図3に示す。
2. Description of the Related Art As a semiconductor device used in a microwave band frequency, a monolithic microwave integrated circuit (hereinafter referred to as a monolithic microwave integrated circuit in which a matching circuit, a bias circuit, or a semiconductor element such as an FET is integrated on a semi-insulating semiconductor substrate such as GaAs. M
MIC) is attracting attention because of its small size, light weight, and low price during mass production. From the viewpoint of reliability, this MMIC needs to be incorporated in an airtight envelope. Generally, as an envelope used in a microwave circuit, an input / output lead portion forms a microstrip line and a side wall portion. Many have a three-layer structure. However, this envelope has the advantage that the parasitic reactance in the high frequency input / output section is small, but has the disadvantage of being extremely expensive. Therefore, as a low-cost package, there is a package currently widely used in digital integrated circuits and the like.
A structure incorporating a C chip is shown in FIG.

【0003】図3(a) は平面図、図3(b) は裏面図、図
3(c) はA−A´における断面図、図3(d) は側面図で
ある。セラミック基板1上の周辺部に複数個の接続端子
部を対称に設け、又セラミック基板1上の周辺部にはそ
の中心部を囲むようにセラミック基板1の外形と同様な
形状であるセラミックの側壁2を設けている。さらにこ
のセラミックの側壁2の上部を閉じる蓋3を設けてい
る。ここでセラミック基板1の中央部には、接地導体4
を設けて、この接地導体4上にはMMIC5が取り付け
られている。
3 (a) is a plan view, FIG. 3 (b) is a rear view, FIG. 3 (c) is a sectional view taken along line AA ', and FIG. 3 (d) is a side view. A plurality of connecting terminal portions are symmetrically provided in the peripheral portion of the ceramic substrate 1, and the side wall of the ceramic substrate 1 has the same shape as the outer shape of the ceramic substrate 1 so as to surround the central portion thereof. 2 is provided. Further, a lid 3 for closing the upper portion of the ceramic side wall 2 is provided. Here, in the central portion of the ceramic substrate 1, the ground conductor 4
Is provided, and the MMIC 5 is mounted on the ground conductor 4.

【0004】また、MMIC5の高周波入出力端子及び
バイアス端子はそれぞれボンデイングワイヤ6によりセ
ラミック基板1の表面に設けられた複数個の接続端子部
の中の所定の入出力端子7に接続されている。一方MM
IC5の接地電極は、MMIC5内のスルーホール等に
より接地導体4に接続され、この接地導体4はボンデイ
ングワイヤ6によりセラミック基板の表面の所定の接地
端子8に接続される。
Further, the high frequency input / output terminal and the bias terminal of the MMIC 5 are connected to a predetermined input / output terminal 7 of a plurality of connection terminal portions provided on the surface of the ceramic substrate 1 by a bonding wire 6, respectively. Meanwhile, MM
The ground electrode of the IC 5 is connected to the ground conductor 4 by a through hole or the like in the MMIC 5, and the ground conductor 4 is connected by a bonding wire 6 to a predetermined ground terminal 8 on the surface of the ceramic substrate.

【0005】ここで外囲器の入出力端子7及び接地端子
8は、それぞれセラミック基板1の周辺に設けられた金
属膜9及び接地用金属膜10を介してセラミック基板1
の裏面に設けられた外部接続端子11及び外部接地端子
12に接続されている。
Here, the input / output terminal 7 and the grounding terminal 8 of the envelope are sandwiched by the metal film 9 and the grounding metal film 10 provided around the ceramic substrate 1, respectively.
Is connected to an external connection terminal 11 and an external ground terminal 12 provided on the back surface of the.

【0006】ところで上記のようにMMIC5を外囲器
に組み込んだ場合、MMIC5の接地電極と外囲器の外
部接地端子12の間には、ボンデイングワイヤ6や接地
端子8や接地用金属膜10のインダクタンスが接続され
るために接地インダクタンスが大きくなり特にMMIC
5がFETを用いた増幅器の場合には利得が低下する欠
点があつた。
When the MMIC 5 is incorporated in the envelope as described above, the bonding wire 6, the ground terminal 8 and the grounding metal film 10 are provided between the ground electrode of the MMIC 5 and the external ground terminal 12 of the envelope. Since the inductance is connected, the ground inductance becomes large, especially MMIC.
In the case where 5 is an amplifier using an FET, there is a drawback that the gain is lowered.

【0007】また、MMIC5の高周波入出力端子ある
いはバイアス端子と外部接続端子11の間にはボンデイ
ングワイヤ6と入出力端子7及び金属膜9を介している
ので上記と同様にインダクタンスが大きくなるのでMM
ICの利得が低下する欠点があった。さらに外囲器を外
部回路に接続する場合に、高周波入出力部では、接続端
子7及び金属膜9と接地端子8及び接地金属膜10との
間隔が広いので接続端子7及び金属膜9に寄生インピー
ダンスが接続されるので所定のインピーダンスを持つ経
路が形成されず外囲器の入出力部におけるインピーダン
スが大きく変化してMMICの特性が低下するという欠
点もあった。
Further, since the bonding wire 6, the input / output terminal 7 and the metal film 9 are interposed between the high frequency input / output terminal or the bias terminal of the MMIC 5 and the external connection terminal 11, the inductance is increased similarly to the above, and thus the MM is obtained.
There is a drawback that the gain of the IC is lowered. Further, when the envelope is connected to an external circuit, in the high frequency input / output unit, the connection terminal 7 and the metal film 9 and the ground terminal 8 and the ground metal film 10 have a large interval, so that the connection terminal 7 and the metal film 9 are parasitic. Since the impedances are connected to each other, a path having a predetermined impedance is not formed, and the impedance at the input / output portion of the envelope greatly changes, which deteriorates the characteristics of the MMIC.

【0008】[0008]

【発明が解決しようとする課題】本発明は上記の欠点を
除去するもので、マイクロ波集積回路用外囲器の誘電体
基板上の導体及び接地導体を改良することによりMMI
Cの特性を低下させないマイクロ波集積回路用外囲器を
提供することを目的とする。
SUMMARY OF THE INVENTION The present invention eliminates the above-mentioned drawbacks, and improves the MMI by improving the conductor and the ground conductor on the dielectric substrate of the envelope for a microwave integrated circuit.
An object of the present invention is to provide an envelope for a microwave integrated circuit that does not deteriorate the characteristics of C.

【0009】[0009]

【課題を解決するための手段】本発明は、誘電体基板
と、この誘電体基板の表面上の周辺部に設けられた少な
くとも1個の入出力端子と、この入出力端子に沿って一
定の距離を有して囲むとともに前記誘電体基板の表面全
面に設けられ、さらにマイクロ波集積回路を載置すると
ともにこの載置されるマイクロ波集積回路の接地電極が
接続される接地導体と、この接地導体に取り付けられる
マイクロ波集積回路の入出力部と前記入出力端子を接続
する接続体と、前記誘電体基板の裏面上の周辺部に設け
られた外部接続端子及び外部接地端子と、この外部接続
端子及び外部接地端子と前記入出力端子及び前記接地導
体とをそれぞれ接続する接続導体と、前記誘電体基板の
表面上の周辺部に前記誘電体基板の中心部を囲むように
設けられた側壁部と、この側壁部の上部を閉じる蓋とを
具備したことを特徴とするものである。
According to the present invention, a dielectric substrate, at least one input / output terminal provided in the peripheral portion on the surface of the dielectric substrate, and a constant number along the input / output terminal are provided. A grounding conductor, which is surrounded by a distance and is provided on the entire surface of the dielectric substrate, on which a microwave integrated circuit is mounted and to which a ground electrode of the mounted microwave integrated circuit is connected, and the grounding conductor. A connector for connecting the input / output unit of the microwave integrated circuit attached to the conductor and the input / output terminal, an external connection terminal and an external ground terminal provided in the peripheral portion on the back surface of the dielectric substrate, and the external connection. Connection conductors for connecting the terminals and external ground terminals to the input / output terminals and the ground conductor, respectively, and a side wall portion provided on the peripheral portion on the surface of the dielectric substrate so as to surround the central portion of the dielectric substrate. When It is characterized in that it has and a lid for closing the upper portion of the side wall portion.

【0010】[0010]

【作用】上記構成したマイクロ波集積回路要外囲器で
は、外囲器の入出力部におけるインピーダンスの変化を
抑制し、外囲器内のMMICの特性の低下を防止するこ
とができる。
In the microwave integrated circuit enclosure required as described above, it is possible to suppress the change in impedance at the input / output portion of the enclosure and prevent the deterioration of the characteristics of the MMIC in the enclosure.

【0011】[0011]

【実施例】以下本発明の一実施例を図面によって説明す
る。図1は本発明による外囲器にMMICを取り付けた
構成図であり、図1(a) は平面図、図1(b) は裏面図、
図1(c) はA−A´における断面図、図1(d) は側面図
である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram in which an MMIC is attached to an envelope according to the present invention, FIG. 1 (a) is a plan view, FIG. 1 (b) is a rear view,
FIG. 1 (c) is a sectional view taken along the line AA ', and FIG. 1 (d) is a side view.

【0012】図1において、セラミック基板1の上の周
辺部に入出力端子7を対称に設け、さらに接地導体4が
この入出力端子7に沿って一定の距離を有して囲むよう
にしてセラミック基板1の表面全面に設けている。すな
わち、入出力端子7と接地導体4間にはギャップ13が
形成されている。
In FIG. 1, input / output terminals 7 are symmetrically provided on the periphery of the ceramic substrate 1, and the ground conductor 4 is surrounded along the input / output terminal 7 with a certain distance so that the ceramic substrate 1 is surrounded. Is provided on the entire surface of. That is, the gap 13 is formed between the input / output terminal 7 and the ground conductor 4.

【0013】また、この接地導体4にはMMIC5が取
り付けられて、このMMIC5の高周波入出力端子及び
バイアス端子はそれぞれボンデイングワイヤ6によりセ
ラミック基板1上の入出力端子7に接続されている。一
方このMMIC5の接地電極は接地導体4にMMIC5
内のスルーホール等により直接接続されている。
An MMIC 5 is attached to the ground conductor 4, and a high frequency input / output terminal and a bias terminal of the MMIC 5 are connected to an input / output terminal 7 on the ceramic substrate 1 by a bonding wire 6, respectively. On the other hand, the ground electrode of the MMIC 5 is connected to the ground conductor 4 by the MMIC 5
It is directly connected by a through hole inside.

【0014】また、外囲器の各々の入出力端子7及び接
地導体4はそれぞれ金属膜9及び接地用金属膜10を通
してセラミック基板1の裏面に設けられた外部接続端子
11及び外部接地端子12に接続されている。さらに、
セラミック基板1上の周辺部にはその中心部を囲むよう
にセラミック基板1の外形と同様な形状であるセラミッ
クの側壁2を設けている。さらにこのセラミックの側壁
2の上部を閉じる蓋3を設けている。
The input / output terminals 7 and the ground conductor 4 of the envelope are connected to the external connection terminal 11 and the external ground terminal 12 provided on the back surface of the ceramic substrate 1 through the metal film 9 and the ground metal film 10, respectively. It is connected. further,
A ceramic side wall 2 having the same shape as the outer shape of the ceramic substrate 1 is provided in the peripheral portion of the ceramic substrate 1 so as to surround the central portion thereof. Further, a lid 3 for closing the upper portion of the ceramic side wall 2 is provided.

【0015】ここで、入出力端子7はギャップ13と接
地導体4により一つの伝送線路(コプレーナ線路)を構
成していると考えられ、入出力端子7の幅が広いほど、
またギャップの幅が狭い(入出力端子7と接地導体4の
間隔が小さい)ほどインピーダンスが小さくなる。
It is considered that the input / output terminal 7 constitutes one transmission line (coplanar line) by the gap 13 and the ground conductor 4, and the wider the input / output terminal 7 is,
Further, the smaller the width of the gap (the smaller the distance between the input / output terminal 7 and the ground conductor 4), the smaller the impedance.

【0016】上記構成によれば、セラミック基板1のほ
ぼ全域に接地導体4が形成されているので、接地インダ
クタンスを十分に小さくすることができる。また、MM
IC5の各々の入出力端子7は、各々の入出力端子7の
幅とギャップ13の幅を最適に選ぶことによって、外囲
器の入出力部(コプレーナ線路,金属膜9及び接地用金
属膜10,外部接続端子11及び外部接地端子12を含
む)における寄生インダクタンスを小さくすることがで
き、MMIC5の性能が低下するのを防ぐことができ
る。
According to the above structure, since the ground conductor 4 is formed over almost the entire area of the ceramic substrate 1, the ground inductance can be made sufficiently small. Also, MM
For each input / output terminal 7 of the IC 5, the width of each input / output terminal 7 and the width of the gap 13 are optimally selected, so that the input / output portion (coplanar line, metal film 9 and grounding metal film 10) of the envelope is selected. , The external connection terminal 11 and the external ground terminal 12 are included), and the performance of the MMIC 5 can be prevented from decreasing.

【0017】ところで図2(a) 〜(c) は図1の実施例で
述べた外囲器において、MMIC5のコプレーナ線路を
形成している各々の入出力端子7の形状を変更した他の
実施例である。図2(a) は複数個の入出力端子7はボン
ディングワイヤ6を接続する部分の幅が金属膜9を接続
する部分の幅より広く形成された構造である。すなわ
ち、入出力端子7の形状が大きくなり、各々の入出力端
子7及びギャップ13の周辺長が長くなる。
2 (a) to 2 (c) show another embodiment in which the shape of each input / output terminal 7 forming the coplanar line of the MMIC 5 is changed in the envelope described in the embodiment of FIG. Here is an example. FIG. 2A shows a structure in which the plurality of input / output terminals 7 are formed such that the width of the portion to which the bonding wire 6 is connected is wider than the width of the portion to which the metal film 9 is connected. That is, the shape of the input / output terminal 7 becomes large, and the peripheral length of each input / output terminal 7 and the gap 13 becomes long.

【0018】このような構造にすることにより、入出力
端子7と接地導体4との間の静電容量を大きくすること
ができる。したがってボンデイングワイヤ6と入出力端
子7及び金属膜9のもっているインダクタンスによるM
MIC5の特性インピーダンスの変化を静電容量を大き
くすることにより防止することができる。
With such a structure, the capacitance between the input / output terminal 7 and the ground conductor 4 can be increased. Therefore, M due to the inductance of the bonding wire 6, the input / output terminal 7 and the metal film 9
A change in the characteristic impedance of the MIC 5 can be prevented by increasing the capacitance.

【0019】また、図2(b) のように入出力端子7と接
地導体4との間隔を狭めても、上記図2(a) の実施例と
同様な効果を生じる。
Even if the distance between the input / output terminal 7 and the ground conductor 4 is narrowed as shown in FIG. 2B, the same effect as that of the embodiment shown in FIG. 2A can be obtained.

【0020】また、図2(C) は各々の入出力端子7及び
接地導体4の対向部をくし形形状とし、互いにこれらを
組み合わせたものである。このような構造にすると、入
出力端子7と接地導体4との間のギャップ13の周辺長
が長くなり、入出力端子7と接地導体4との間の等価静
電容量を図2(a) や図2(b) の実施例よりもさらに大き
くすることができるので、MMIC5の特性インピーダ
ンスの変化を防止することができるとともに各々の入出
力部を小型にすることができて、外囲器を小型化するこ
とができる。
Further, FIG. 2C shows that the facing portions of the respective input / output terminals 7 and the ground conductor 4 are formed in a comb shape and are combined with each other. With such a structure, the peripheral length of the gap 13 between the input / output terminal 7 and the ground conductor 4 becomes long, and the equivalent capacitance between the input / output terminal 7 and the ground conductor 4 is shown in FIG. 2 and the embodiment shown in FIG. 2 (b), the characteristic impedance of the MMIC 5 can be prevented from changing, and each input / output unit can be made small, so that the envelope can be reduced. It can be miniaturized.

【0021】[0021]

【発明の効果】本発明によればマイクロ波集積回路用外
囲器内の誘電体基板上において、接地導体を入出力端子
に沿って一定の距離を有して囲むとともに誘電体基板の
表面全面に形成することにより、マイクロ波集積回路用
外囲器の入出力部における寄生インピーダンスの発生に
よるインピーダンスの変動を抑制し、マイクロ波集積回
路の本来の性能を引き出すことができるマイクロ波集積
回路用外囲器を提供できる。
According to the present invention, on the dielectric substrate in the envelope for a microwave integrated circuit, the ground conductor is surrounded along the input / output terminals with a certain distance, and the entire surface of the dielectric substrate is covered. By forming the structure in the microwave integrated circuit package, it is possible to suppress the impedance variation caused by the generation of parasitic impedance in the input / output part of the microwave integrated circuit package and to bring out the original performance of the microwave integrated circuit. An enclosure can be provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の一実施例を示す構成図である。FIG. 1 is a configuration diagram showing an embodiment of the present invention.

【図2】この発明の他の実施例を示す構成図である。FIG. 2 is a configuration diagram showing another embodiment of the present invention.

【図3】従来例を示す構成図である。FIG. 3 is a configuration diagram showing a conventional example.

【符号の説明】[Explanation of symbols]

1…誘電体基板 4…接地導体 7…入出力端子 8…接地端子 9…金属膜 10…接地用金属膜 11…外部接続端子 12…外部接地端子 DESCRIPTION OF SYMBOLS 1 ... Dielectric substrate 4 ... Ground conductor 7 ... Input / output terminal 8 ... Ground terminal 9 ... Metal film 10 ... Metal film for ground 11 ... External connection terminal 12 ... External ground terminal

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 誘電体基板と、この誘電体基板の表面上
の周辺部に設けられた少なくとも1個の入出力端子と、
この入出力端子に沿って一定の距離を有して囲むととも
に前記誘電体基板の表面全面に設けられ、さらにマイク
ロ波集積回路を載置するとともにこの載置されるマイク
ロ波集積回路の接地電極が接続される接地導体と、この
接地導体に取り付けられるマイクロ波集積回路の入出力
部と前記入出力端子を接続する接続体と、前記誘電体基
板の裏面上の周辺部に設けられた外部接続端子及び外部
接地端子と、この外部接続端子及び外部接地端子と前記
入出力端子及び前記接地導体とをそれぞれ接続する接続
導体と、前記誘電体基板の表面上の周辺部に前記誘電体
基板の中心部を囲むように設けられた側壁部と、この側
壁部の上部を閉じる蓋とを具備したマイクロ波集積回路
用外囲器。
1. A dielectric substrate, and at least one input / output terminal provided in a peripheral portion on a surface of the dielectric substrate,
It is provided along the input / output terminal with a certain distance and is provided on the entire surface of the dielectric substrate. Further, the microwave integrated circuit is mounted and the ground electrode of the mounted microwave integrated circuit is A grounding conductor to be connected, a connecting body for connecting the input / output terminal of the microwave integrated circuit attached to the grounding conductor and the input / output terminal, and an external connecting terminal provided in the peripheral portion on the back surface of the dielectric substrate. And an external ground terminal, connection conductors for connecting the external connection terminal and the external ground terminal to the input / output terminal and the ground conductor, respectively, and a central portion of the dielectric substrate on a peripheral portion on a surface of the dielectric substrate. An envelope for a microwave integrated circuit, comprising: a side wall portion provided so as to surround the side wall; and a lid closing an upper portion of the side wall portion.
【請求項2】 前記複数個の入出力端子及び前記接地導
体の対向部がそれぞれくし形形状を有して互いに組み合
せた構造である請求項1記載のマイクロ波集積回路用外
囲器。
2. The envelope for a microwave integrated circuit according to claim 1, wherein the facing portions of the plurality of input / output terminals and the ground conductor each have a comb shape and are combined with each other.
【請求項3】 前記複数個の入出力端子は前記接続体を
接続する部分の幅が前記接続導体を接続する部分の幅よ
り広いことを特徴する請求項1記載のマイクロ波集積回
路用外囲器。
3. The microwave integrated circuit envelope according to claim 1, wherein a width of a portion of the plurality of input / output terminals for connecting the connecting body is wider than a width of a portion for connecting the connecting conductor. vessel.
JP6260921A 1994-10-03 1994-10-03 Envelope for microwave integrated circuit Expired - Lifetime JP2534841B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6260921A JP2534841B2 (en) 1994-10-03 1994-10-03 Envelope for microwave integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6260921A JP2534841B2 (en) 1994-10-03 1994-10-03 Envelope for microwave integrated circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP60008377A Division JPH0732213B2 (en) 1985-01-22 1985-01-22 Envelope for microwave integrated circuit

Publications (2)

Publication Number Publication Date
JPH07231051A JPH07231051A (en) 1995-08-29
JP2534841B2 true JP2534841B2 (en) 1996-09-18

Family

ID=17354616

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6260921A Expired - Lifetime JP2534841B2 (en) 1994-10-03 1994-10-03 Envelope for microwave integrated circuit

Country Status (1)

Country Link
JP (1) JP2534841B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4563980B2 (en) * 2006-10-13 2010-10-20 三菱電機株式会社 Surface mount type package and semiconductor device
JP6228561B2 (en) * 2015-03-23 2017-11-08 日本電信電話株式会社 High frequency transmission line and optical circuit

Also Published As

Publication number Publication date
JPH07231051A (en) 1995-08-29

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