JPS58213456A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a parasitic reactance section in a ground section by forming a conductor layer for ground between a conductor layer for an output and a conductor layer for an input and connecting the conductor layer for ground to an external ground surface through a through-hole formed to a dielectric substrate. CONSTITUTION:Pairs in which the conductor layers 20, 22 for outputs, semiconductor chips 40, 42 and the conductor layers 12, 14 for inputs are arranged rectilineraly onto the dielectric substrate 10 are seperated mutually into a plurality of pairs in parallel. The conductor layers 32, 34 for ground used in common to each pair are formed among the conductor layers 20, 22 for outputs and the conductor layers 12, 14 for inputs of each pair. The conductor layers 36, 38 for ground are connected to the external ground surface through the through-holes 36, 38 formed to the dielectric substrate 10, and each electrode of the semiconductor chips 40, 42 is severally connected electrically to corresponding conductor layers.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device used in a high frequency band, and particularly to a high output semiconductor device in which two or more transistor chips are mounted in one package.

The field of high-frequency, high-output transistors in the VHF and UHF bands continues to make remarkable progress, and devices capable of outputting power exceeding several 100 W have appeared.

The conventional technique for achieving this trend toward higher output has been to house a large number of transistor chips in one package and arrange them in parallel.

However, with this structure, the parasitic reactance associated with the transistor chip and the conductive wires (bonding wires) inside the package lowers the transistor's input/output impedance level, narrows the transistor's operating band width, causes power loss, and ultimately It has the disadvantage of having a negative impact on impedance matching ability.

Therefore, it is an object of the present invention to provide a semiconductor device structure having a good impedance level, and to provide a semiconductor device having a high input/output impedance that satisfies wide bandwidth, high power, and simplification of external circuits. It will be done.

The semiconductor device storage container of the present invention includes at least one dielectric member, and a pair of conductive input portions and a second conductive input portion separately provided on the dielectric member. an input portion, a pair of output portions consisting of a first conductive output portion and a second conductive output portion provided separately on the dielectric member, and a first conductive output portion on which a first transistor chip is mounted. and a second metallization pattern carrying a second transistor chip, wherein the first conductive input part, the first transistor chip, and the first conductive output part are arranged in a straight line, and the first conductive input part, the first transistor chip, and the first conductive output part are arranged in a straight line. the second conductive input section;
A second transistor chip and a second conductive output are also arranged in parallel and in a straight line. Each input and output electrode of the first and second transistor chips is connected to an opposing conductive input and conductive output by a bonding wire. Further, a pair of conductive ground portions are provided between the pair of input portions and the pair of output portions so as to sandwich the first and second transistor chips, and the pair of conductive ground portions are It is provided on the dielectric member and connected to the external ground plane through a through hole. The ground terminals (common electrodes) of the first and second transistor chips are bonded to the conductive ground portions of the pair, and the bonding line is a straight line connecting the conductive input portion and the conductive output portion. It is set up so that it lies flat.

Although the semiconductor device of the present invention basically satisfies the above-mentioned principle, it is preferable that the conductive input portion and the conductive output portion be arranged symmetrically with respect to a pair of conductive ground portions. Additionally, when the first and second transistor chips are placed on the first and second conduction output parts of the front 111L, the conduction ground parts are not paired, and the conduction input part and the conduction ground part are not paired. These may be provided so as to be separated from the output section.

Further, in a state where the electrodes on the transistor chip are bonded and connected via the conductive ground part, the bonding wire is manufactured so as to bridge the conductive ground part and over it.

According to the present invention, in a high-power semiconductor device in which a plurality of transistor chips are housed in one container, conductive input portions and conductive output portions related to each transistor chip are arranged in a straight line, respectively. A conductive ground portion is provided across the transistor chip, and this conductive ground portion is designed to be operationally shared by all transistor chips. Furthermore, the conductive ground portion is connected to the external ground plane via a through hole. As a result, high input/output impedance and broadband characteristics can be obtained, and parasitic reactance can also be significantly reduced. In particular, if a through hole is provided in a common conductive grounding part, multiple grounding molds, poles, and electrodes of the transistor chip are connected to the conductive grounding part by bonding wires, etc., and the transistors are connected through the through hole. There is an advantage that the electrical lengths of the plurality of ground electrode pads of the chip and the external ground plane can be equal to tx tx. This makes it possible to stabilize high frequency operation, increase output, and increase gain. That is, the present invention can provide a semiconductor device in which two or more transistor chips fixed to a common dielectric with no thermal conductivity can easily constitute a push/pull circuit type. ζIf the area of the transistor chip is the same, by using the semiconductor device based on the present invention in the double circuit system, the input impedance and output impedance are both 4. It will be doubled. Using the implementation technique of the present invention, both high input and output impedances result in simple circuit construction, reduced power loss, and resulting in higher power levels and wider bandwidths.

An embodiment of the present invention will be described in detail below with reference to the drawings.

The transistor package of this embodiment includes a wafer 10 made of a highly thermally conductive ceramic such as beryllia, on which separate metal portions or pads are deposited according to known metallization techniques. This metal part includes a pair of input parts 12.14. Input terminals 16.18 are each attached to metal input portion 12.14. A pair of output portions 20.22 are also deposited on the wafer 10. The long axis of the output section 20.22 coincides with the corresponding long axis of the input section 12.14. Output terminals 24.26 are each attached to output portion 20.22. Furthermore, metallization portions 28, 30 for mounting a pair of transistor chips are also deposited on the wafer 10. Here, the metallized part 28 is between the input and output parts 12.20,
The metallized portion 30 is also arranged between the input and output portions 14.22. The common ground plane in this example consists of a pair of all-pole ground sections 32,34. These grounding portions are deposited on the wafer 10 and are located between the input portion and the output portion in a positional relationship substantially perpendicular to the longitudinal axis of the input and output portions. Further, the common ground portion 32.34 has through holes 36.34 provided in the wafer 10. ．． 38 allows for electrical connection to an external ground plane attached to the wafer 10. That is, in order to make the above connection possible, metallization is placed inside the through holes 36 and 38 on the wafer 10.
It is applied all the way to the bottom of the. Furthermore, a pair of transistor chips 40 are placed on each of the metallized portions 28 and 30.
. The pads and gates are connected to the ground portions 32 and 34. With this structure, the parasitic reactance at the ground portion is significantly reduced, and at the same time the stray 1 between the input and output is also reduced. It is also possible to effectively prevent signal leakage, interference, etc. that occur between the two.As a result, it is possible to achieve a wide band, high gain, and high input/output impedance with little power loss.

Incidentally, when the transistor chips 40, 42 are placed on the output conductive portion, the ground portion 1 portion 34 can be omitted.

[Brief explanation of drawings]

FIG. 1 shows a configuration diagram of a semiconductor device according to an embodiment of the present invention. 10... Motsumic wafer such as beryllia, 1
2゜14...Pair of conductive parts for input, 16.1
8...1 pair of input pull-out leads, 20.2
2... A pair of output conductive parts, 24.26...
...1 pair of output pull-out leads, 28.30...
...metalized part for mounting a pair of transistors, 32
．． 34... Common ground conductive part, 36, 38.
...Through hole, 40.42...Pair of transistor chips, 44...Bonding wire. Bracket / l

Claims (1)

[Claims] A plurality of sets in which an output conductor layer, a semiconductor chip, and an input conductor layer are arranged linearly on a dielectric substrate are separated from each other and arranged in parallel, and a grounding conductor layer commonly used for each set is provided. provided between the output conductor layer and the input conductor layer of each set, the ground conductor layer being connected to an external ground plane via a through hole provided in the dielectric substrate;
A semiconductor device, wherein each electrode of the semiconductor chip is electrically connected to a corresponding conductor layer.