JPH03217103A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH03217103A
JPH03217103A JP1415890A JP1415890A JPH03217103A JP H03217103 A JPH03217103 A JP H03217103A JP 1415890 A JP1415890 A JP 1415890A JP 1415890 A JP1415890 A JP 1415890A JP H03217103 A JPH03217103 A JP H03217103A
Authority
JP
Japan
Prior art keywords
source
capacitance
insulator
gate
insulators
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1415890A
Other languages
Japanese (ja)
Inventor
Yasuhisa Yamashita
泰久 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP1415890A priority Critical patent/JPH03217103A/en
Publication of JPH03217103A publication Critical patent/JPH03217103A/en
Pending legal-status Critical Current

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  • Microwave Amplifiers (AREA)

Abstract

PURPOSE:To obtain a small-sized transmission power amplifier element superior in stability by arranging a dielectric material just under or on the external lead part enclosed in a package and forming a matching capacitor with both of them. CONSTITUTION:The package consists of a gate lead 1, a drain lead 2, a heat sink 3 used as the source terminal, an insulator 4 which insulates the source and the gate and forms a capacitor, an insulator 5 which insulates the source and the drain, and a GaAs power FET chip 6. Normally, several pF capacitance is connected between the gate and the source in the case of an FET. The value of the capacitance is determined by areas on insulators of leads and materials (dielectric constance) and thickness of insulators. Insulators are separated from each other by the heat sink at the center for the purpose of reducing the freed back capacitance of input/output to optimize the input capacity.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、移動無線機の送信電力増幅用に好適な半導体
装置に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device suitable for amplifying the transmission power of a mobile radio.

従来の技術 従来、この種の送信電力増幅用の半導体素子は、小さな
増幅素子を多数並列に動作させて高出力を得ており、入
力インピーダンスは、非常に小さい。
2. Description of the Related Art Conventionally, this type of semiconductor device for transmitting power amplification has obtained a high output by operating a large number of small amplification elements in parallel, and has an extremely small input impedance.

したがって、増幅用素子チップの近傍に容量を付加する
ことが、高出力化、安定性の面で有利である。第2図(
a)は従来の電力増幅素子の等価回路、第2図(b)は
平面図で、パッケージ内部に増幅用素子チップとは別の
チップで形成した容量部をマウントした構成になってい
た。
Therefore, adding a capacitor near the amplification element chip is advantageous in terms of higher output and stability. Figure 2 (
FIG. 2(b) is a plan view of the equivalent circuit of a conventional power amplification element, in which a capacitor formed of a chip other than the amplification element chip is mounted inside the package.

発明が解決しようとする課題 このような従来の構成では、2個の半導体チップを使用
するため、パッケージを小型化することが困難であった
。また、小型化のため、容量を取り除いた構成にした場
合、外部整合回路が複雑になったり、安定性が悪くなる
という課題があった。
Problems to be Solved by the Invention In such a conventional configuration, since two semiconductor chips are used, it is difficult to miniaturize the package. Further, when a configuration is adopted in which the capacitance is removed for miniaturization, there are problems in that the external matching circuit becomes complicated and stability deteriorates.

本発明はこのような課題を解決するもので、小型で安定
な高周波電力増幅用半導体装置を提供することを目的と
するものである。
The present invention solves these problems, and aims to provide a small and stable semiconductor device for high frequency power amplification.

課題を解決するための手段 この課題を解決するために本発明は容量をノくツケージ
の金属リードと絶縁部で形成する構成としたものである
Means for Solving the Problems In order to solve this problem, the present invention has a structure in which a capacitor is formed by a metal lead of a socket cage and an insulating part.

作用 この構成により、小型で安定性にすぐれた高周波送信用
電力増幅半導体装置を提供することとなる。
Effect: This configuration provides a compact and highly stable power amplification semiconductor device for high frequency transmission.

実施例 第1図(alは本発明の一実施例による900MHz帯
,2W出力用GaAsバワーFET半導体装置の断面図
、第1図偽》は同平面図である。
Embodiment FIG. 1 (Al is a sectional view of a GaAs power FET semiconductor device for 900 MHz band and 2 W output according to an embodiment of the present invention, and FIG. 1 (false) is a plan view of the same.

第1図(a),第1図(b)において、パッケージは、
ゲートリード1,ドレインリード2、ソース端子として
用いるヒートシンク3、ソースとゲートを絶縁し容量を
形成する絶縁物4、ソースとドレインを絶縁する絶縁物
5、GaAsパワーFETチップ6からなる。
In FIG. 1(a) and FIG. 1(b), the package is
It consists of a gate lead 1, a drain lead 2, a heat sink 3 used as a source terminal, an insulator 4 that insulates the source and gate and forms a capacitor, an insulator 5 that insulates the source and drain, and a GaAs power FET chip 6.

通常、上記のFETの場合、数pFの容量をゲート・ソ
ース間に入れる。
Normally, in the case of the above FET, a capacitance of several pF is inserted between the gate and source.

容量の大きさは、リードの絶縁物上の面積、絶縁物の材
質(誘電率)及び厚さで決定される。
The size of the capacitance is determined by the area of the lead on the insulator, the material (permittivity) and thickness of the insulator.

例えば、リード面積:7+mmX1mm絶縁物:アルミ
ナ(誘電率9.6) 厚さ 0.5+m の場合、容量は約8. 3 p Fとなる。
For example, if the lead area is 7+mm x 1mm, the insulator is alumina (dielectric constant 9.6), and the thickness is 0.5+m, the capacitance is approximately 8. 3 pF.

また、絶縁物の誘電率は、アルミナの他にベリリア(B
ed)       6.7窒化アルミニウム(A I
 N)  4. 2〜4.53 ヒタセラA (S ic/BeO)  40等があり、
用途により使い分けられる。
In addition to alumina, the dielectric constant of insulators is beryllia (B).
ed) 6.7 Aluminum nitride (A I
N) 4. 2-4.53 Hitacera A (Sic/BeO) 40 etc.
Can be used depending on the purpose.

また、入出力の帰還容量を低減し、入力容量を最適化す
るため、絶縁物はヒートシンクで中央を分離した形状で
構成される。
Additionally, in order to reduce input/output feedback capacitance and optimize input capacitance, the insulator is separated in the center by a heat sink.

なお、このパッケージは、同じ用途のStバイポーラト
ランジスタにも用いることができる。
Note that this package can also be used for St bipolar transistors for the same purpose.

発明の効果 以上の実施例から明らかなように、本発明によれば、パ
ッケージに用いる絶縁物を容量として用いるため、小型
で安定性にすぐれた送信用電力増幅素子が構成される。
Effects of the Invention As is clear from the above embodiments, according to the present invention, since the insulator used in the package is used as a capacitor, a small and highly stable transmission power amplification element is constructed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(alは本発明の一実施例による半導体装置の断
面図、第1図(blは同平面図、第2図Talは従来の
FET半導体装置の等価回t第2図(blは同平面図で
ある。 1・・・・・・ゲートリード、2・・・・・・ドレイン
リード、3・・・・・・ヒートシンク(ソース)、4・
・・・・・容量を形成する絶縁物、5・・・・・・絶縁
物、6・・・・・・GaAs FET4 チップ。
Figure 1 (al is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, Figure 1 (bl is a plan view of the same, and Figure 2 Tal is an equivalent circuit diagram of a conventional FET semiconductor device. 1 is a plan view. 1... Gate lead, 2... Drain lead, 3... Heat sink (source), 4...
...Insulator forming capacitor, 5...Insulator, 6...GaAs FET4 chip.

Claims (1)

【特許請求の範囲】[Claims]  パッケージ内に収納される外部リード部の直下または
直上に誘電体物質を配設し、両者で整合容量を形成した
ことを特徴とする半導体装置。
A semiconductor device characterized in that a dielectric material is disposed directly below or directly above an external lead section housed in a package, and a matching capacitance is formed between the two.
JP1415890A 1990-01-23 1990-01-23 Semiconductor device Pending JPH03217103A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1415890A JPH03217103A (en) 1990-01-23 1990-01-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1415890A JPH03217103A (en) 1990-01-23 1990-01-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH03217103A true JPH03217103A (en) 1991-09-24

Family

ID=11853343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1415890A Pending JPH03217103A (en) 1990-01-23 1990-01-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH03217103A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0524763A3 (en) * 1991-07-22 1994-02-16 Motorola Inc
JPH06268092A (en) * 1993-03-17 1994-09-22 Rohm Co Ltd High-frequency fet and package therefor
JP2007267026A (en) * 2006-03-28 2007-10-11 Fujitsu Ltd High output amplifier

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0524763A3 (en) * 1991-07-22 1994-02-16 Motorola Inc
JPH06268092A (en) * 1993-03-17 1994-09-22 Rohm Co Ltd High-frequency fet and package therefor
JP2007267026A (en) * 2006-03-28 2007-10-11 Fujitsu Ltd High output amplifier

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