JPH06169064A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the chip occupation area ratio of a matching circuit in the chip of a microwave semiconductor device. CONSTITUTION:An MIM capacitor composed of a lower layer electrode 7, a capacitor insulating film 8 and an upper electrode 9 is formed above a via-hole 1a. Further, a spiral inductor 11 and a metal resistor 12 are formed on the MIM capacitor with an insulating film 10 therebetween. With this constitution, the number of logic chips for one wafer is increased and the number of non- defective chips can be increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a microwave integrated circuit (MMI) using a GaAs substrate.
It relates to the reduction of the chip size of C).

[0002]

2. Description of the Related Art FIG. 5 shows an MMI which is a conventional semiconductor device.
The top view of C is shown. Generally, G is used as the MMIC substrate.
An aAs substrate is used, a circuit element is formed on one main surface thereof, and a back surface metallization is applied to the entire other main surface, and the circuit element and the metallization formed on the one main surface side by using a via hole. Are connected. That is, in FIG. 5, reference numeral 1 is a via hole (hereinafter, V / H) upper surface electrode formed on the surface of the GaAs substrate 6a, 6b, which is formed on each circuit element on the surface of the GaAs substrate and on the back surface side of the substrate 6a, 6b. Also plays a role of connecting to a back surface metal (not shown). Reference numeral 2 denotes a metal insulator metal (MIM) capacitor, which is a GaAs substrate 6a, 6b.
It is configured by stacking a plurality of conductors and insulators on top. 3 is a semiconductor resistor formed by implanting ions into a specific region of the GaAs substrate 6a to increase the resistance of the region, 4a and 4b are front and rear FETs serving as amplifiers, and 5 is a spiral inductor, FE
T4a and 4b are formed on a GaAs substrate 6b different from the GaAs substrate 6a, and the circuits of the GaAs substrate 6a on which the FETs 4a and 4b are formed are connected by wires 14 on the respective substrates 6a and 6b. It is electrically connected by connecting the electrode pad 16e.

Further, 16a is a signal input pad which serves as an input terminal for a high frequency signal, 16b is an electrode pad which serves as a drain bias terminal of each FET 4a, 4b, and 16c is an F of the preceding stage.
16 electrode pads serving as gate bias terminals of ET4a
Reference numeral d is an electrode pad that serves as a gate bias terminal of the two FETs 4b in the subsequent stage, and 17 is an output pad from which the output of the FET 4b in the subsequent stage is taken out. Reference numeral 15 is a passivation film that covers the circuit formation region of the GaAs substrate 6.

Next, the operation will be described. GaAsMM
The IC is a microwave amplification element and has a function of amplifying a high frequency input. That is, when a high frequency signal is input to the electrode pad 16a which is an input terminal on the substrate 6b, the FET of the previous stage is
The input impedance is matched by the MIM capacitor 2 and the spiral inductor 5 existing in the path leading to 4a, amplified by the FET 4a, further amplified by the FET 4b in the subsequent stage, and output from the FET 4b to the output pad 17 which is an output terminal. The amplified high frequency signal is output, and the reflection of the signal at the input terminal of the amplifier circuit is suppressed in this way.

Generally, in GaAsMMIC,
In order to perform amplification efficiently, the highest performance as an amplifier can be obtained by using the capacitor 4, the spiral inductor 5, which becomes the impedance matching circuit, the V / H1, the semiconductor resistor 3, etc., which becomes the inter-FET coupling circuit, around the FET 4. Therefore, it is necessary to arrange them on the same plane.

[0006]

A conventional semiconductor device (G
aAsMMIC) is configured as described above, and since the back surface of the substrate is entirely metallized, a method of forming elements on both sides of the substrate, which is a well-known technique for improving the degree of integration. Can not be adopted, V
Each component such as / H, MIM capacitor, spiral inductor, and semiconductor resistor has to be formed on the same plane, which makes it difficult to reduce the chip size.

The present invention has been made in order to solve the above problems, and in the MMIC, V / H, M
An object of the present invention is to obtain a semiconductor device capable of reducing the chip size even if elements such as an IM capacitor, a spiral inductor, and a semiconductor resistor are formed on the same substrate.

[0008]

In the semiconductor device according to the present invention, an FET, a MIM capacitor, a V / H, a spiral inductor, a semiconductor resistor, a metal resistor and the like used in a matching circuit of FETs and a coupling circuit between FETs are desired. The respective circuits are combined and laminated.

In addition, a via hole is formed as the coupling circuit, a base electrode of the MIM capacitor and a capacitor insulating film are arranged on the via hole, and a ground electrode is arranged around the via hole except the upper part of the via hole. It was done.

[0010]

In the present invention, the amplifier, the matching circuit, and the FE
By combining and stacking circuit elements (FET, MIM capacitor, V / H, spiral inductor, semiconductor resistor, metal resistor, etc.) used in the T-to-T coupling circuit,
The degree of integration of the device is improved.

Further, when a capacitor is laminated on the via hole, the capacitor upper electrode is disposed around the via hole except the upper part of the via hole, so that the stress applied from the via hole side destroys the capacitor insulating film. Can be less.

[0012]

【Example】

Example 1. Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 show an MMI according to a first embodiment of the present invention.
6 is a cross-sectional view and a plan configuration diagram of C, the same reference numerals as those in FIG. 5 denote the same or corresponding portions, 7 is a base electrode of a MIM capacitor formed on a GaAs substrate 6, and 8 is a capacitor insulation corresponding to an insulator of MIM. A film, 9 is an MIM top metal electrode formed on the capacitor insulating film 8, 1
Reference numeral 0 is an insulating film formed on the MIM upper electrode 9, 11 is a spiral inductor formed on the insulating film 10, 12 is a metal resistor formed on the insulating film 10, 13 is an MIM base electrode 7 on the surface of the substrate 6. And a back surface metal that connects the back surface side of the substrate via the via hole 1a. Note that the passivation film is not shown in FIGS.
Then, the capacitor insulating film 8 and the insulating film 10 are omitted.

Next, the function and effect will be described. In order to make the FET function as a microwave amplification element, the FET is
Although it is necessary to provide a matching circuit and a coupling circuit between FETs around this, in this embodiment, M is provided on V / H1a.
An MIM capacitor including an IM base electrode 7, a capacitor insulating film 8 and an MIM upper electrode 9, and an insulating film 1 on the MIM capacitor.
0 through spiral inductor 11 and metal resistor 12
The matching circuit and the inter-FET coupling circuit, which are conventionally arranged independently of each other in a plane, are three-dimensionally arranged because of the laminated structure.
The area occupied by the ET-to-ET coupling circuit on the chip is reduced, the element size can be reduced, and the degree of integration of elements can be improved.

Example 2. Next, a second embodiment of the present invention will be described. 3 and 4 are a sectional view and a plan view of an MMIC according to a second embodiment of the present invention, respectively.
In the first embodiment described above, the MIM base electrode 7, the capacitor insulating film 8 and the MIM upper electrode 9 are laminated right above the V / H 1a to form the MIM capacitor. However, in this embodiment, the MIM capacitor is formed. The upper electrode is formed so as to avoid the via hole 1a.

That is, as shown in the figure, as in the first embodiment, the MIM base electrode 7 and the capacitor insulating film 8 are laminated directly on the V / H 1a, and the via hole 1 is further formed thereon.
A frame-shaped MIM upper electrode 9a is formed so as to avoid the upper portion.

Next, the function and effect will be described. As described above, by arranging the MIM upper electrode 9a while avoiding the upper part of the via hole 1a, in addition to the effect of the first embodiment, the MIM is caused by heat or the like at the time of forming V / H1a.
Even when the lower electrode 7 of the capacitor is thermally expanded, the stress generated by the thermal expansion causes the capacitor insulating film 8
Is not compressed by being sandwiched between the electrodes, and therefore it is possible to prevent defective MIM capacitors from occurring due to destruction of the capacitor insulating film 8.

In each of the above-mentioned embodiments, the MIM capacitor and the spiral inductor are formed on the V / H 1a, and
Although the three circuit components are arranged three-dimensionally, the combination of the three-dimensionally arranged circuit elements and the number of arranged circuit elements are not limited to this. For example, a capacitor or an inductor is laminated on the FET. Alternatively, only the spiral inductor may be formed on the MIM capacitor.

[0018]

As described above, according to the semiconductor device of the present invention, the amplifier, the matching circuit, and the inter-FET coupling circuit, which are required, are combined and laminated, so that the degree of integration is improved. There is an effect that it can be improved, the chip size can be reduced, and the theoretical number of chips per wafer can be increased.

Further, when the MIM capacitor is laminated on the via hole, the upper metal electrode of the MIM capacitor is arranged so as to avoid the upper portion of the via hole, so that the MIM is caused by stress caused by thermal expansion or the like when the via hole is formed. The insulating film of the capacitor can be prevented from being destroyed, and the reliability of the device can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view of the semiconductor device according to the above embodiment.

FIG. 3 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a plan view of the semiconductor device according to the above embodiment.

FIG. 5 is a plan view showing a conventional semiconductor device.

[Explanation of symbols]

 1a Via hole 3 Semiconductor resistance 4 FET 6 GaAs substrate 7 MIM capacitor base electrode 8 Capacitor insulating film 9 MIM capacitor upper electrode 9a Frame-shaped MIM capacitor upper electrode 10 Insulating film 11 Spiral inductor 12 Metal resistance 13 Backside metal

Claims (2)

[Claims] 1. An amplifier for amplifying a high frequency signal,
In a semiconductor device comprising a matching circuit for matching the impedance of input / output signals of the amplifier and a coupling circuit for connecting between the amplifiers, a plurality of the matching circuits or coupling circuits are combined,
Alternatively, a semiconductor device in which a plurality of matching circuits, coupling circuits, and amplifiers are arbitrarily combined and these are stacked. 2. The semiconductor device according to claim 1, wherein a via hole is formed as the coupling circuit, and when a metal insulator metal capacitor is formed as a matching circuit on the via hole, the upper electrode thereof is used as the via hole. A semiconductor device, characterized in that it is arranged in the periphery of the semiconductor device except above.