JPS58101465A - Field effect transistor - Google Patents

Abstract

PURPOSE:To reduce the number of assembling steps and to increase the efficiency of the characteristics of a field effect transistor by forming the electrodes of a gate and a drain in a beam lead structure, and forming the source electrode in the structure capable of being thermally press-bonding directly to a heat sink metal. CONSTITUTION:An electrode metal seat 16 is formed by plating on the source electrode of a GaAs substrate 14, gate and drain electroes 17, 18 are formed at the symmetrical positions to the seat, and beam lead electrodes 19, 20 are attached by thick plating. The base 16 is thermally press-bonded to a heat sink metal 21, thereby press-donding the leads 19, 20 to output metallized layers 24, 25 on the metal 21. The heat from the substrate 14 is conducted through the base 16 directly to the metal 21, the temperature distribution in the substrate is uniformly performed, the saturated output power is increased, thereby improving the linearity of the output and obtaining the highly efficient characteristics with high gain. Further, the line junction is made unnecessary, and the number of steps can be accordingly largely reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a field effect transistor, and particularly to a gallium arsenide field effect transistor for high output microphone four-wave band.

There is a demand for compound semiconductor devices to be integrated into ICs to achieve smaller size, higher reliability, lower cost, and higher performance, and GaA
Development of sICs, centering on logic elements, is progressing rapidly. GaAs FF as a microwave band amplification element
Attempts have been made to develop 1T ICs, and various studies have been made for use in small signal amplification, ranging from hybrid integrated ICs to monolithic ICs.

On the other hand, it is difficult to integrate high-output GaAs FETs into ICs due to problems such as heat dissipation and matching circuits, and at present the IC is limited to a so-called chip carrier in which a chip is mounted on a substrate.

The present invention uses GaA having a structure that is easy to handle and can achieve high performance when integrated into an IC as described above.
s FET.

In the all-GaAs FET according to the present invention, the gate and drain electrodes have a beam-lead structure, and the source electrode has a structure that can be thermocompressed directly to the heat dissipation metal, which reduces thermal resistance and resistance, and allows for grounding. As the inductance is reduced, the saturated output power increases and output linearity characteristics are improved, while at the same time achieving high gain.

Highly efficient characteristics can be obtained. In addition, by using beam leads for the input and output electrode terminals, element mounting is simplified.
Wire bonding, which was required when connecting conventional device containers and chips, is no longer necessary, making it possible to significantly reduce the number of man-hours.

The present invention will be explained in detail below using drawings to better understand the present invention.

Figure 1 shows the structure of a conventional high-output potassium arsenide FIT, in which 4 FET chips 1 are mounted on a heat dissipating metal 2, and the gate and drain electrodes 3.4 of the chip 1 are used for input and output, respectively. Metallized layer 7.8 of dielectric substrate 5°6
are connected by bonding wires 9.10. In the front, the source electrode 11 of the chip 1 is connected to the protrusion 12 of the heat dissipating metal 2.
is connected to by a bonding wire 13.

In the above structure, the heat generated in the center near the surface of the FIiST chip is conducted to the heat dissipating metal 2 through the GaAsF substrate 1, which has poor thermal conductivity compared to Cricon. In order to achieve this, it is necessary to increase the size of the chip by lowering the arrangement density of the gate portion, which serves as a heat source, and to reduce the thickness of the GaAs substrate 1 as much as possible. Further, the protrusion 1 is connected to the source electrode 11 by the bonding line 13.
2, the inductance component due to this bonding line 13 reduces the power gain. Therefore, it is necessary to take precautions such as using a wide tape instead of the bonding wire 13 and performing chip machining by placing the chip 1 as close as possible to the protrusion metal 12, which requires advanced assembly technology and assembly man-hours. It was needed.

FIG. 2 shows the structure of an FIT chip according to an embodiment of the present invention, in which a source electrode 15 is formed in the center of a GaAs substrate 14, and a nine-electrode metal pedestal 16 is plated to a thickness of KFilO~20 cm on the source electrode ls. is formed.

Furthermore, a gate electrode 17. Drain electrodes 18 are formed, and each electrode is provided with beam lead electrode metal 19, 20, also formed by plating with a thickness of 10 to 20 microns.

Figure 3 shows a beam-lead type GaA easy F according to the present invention]1
3T is shown, the source electrode entertainment pedestal 16 is thermocompression bonded to the heat dissipation metal 21, and the beam lead metals 19 and 20 of the gate and drain electrodes are attached to the input and output dielectrics on the heat dissipation metal 21. They are each connected by thermocompression to input and output metallization layers 24.25 formed on substrates 22.23. Main beam lead type G
aAs FETs can be installed in an element container as in the past, when mounted inside a MIC hybrid integrated circuit, and even in a small element container as a single power stage of a mono IC preamplifier section. Any implementation of K is applicable. Furthermore, in order to achieve high output, K is realized by connecting the present FETs in parallel.With the structure of the present invention, the heat generated in the channel part of the G1As substrate 14 is directly transferred to the heat dissipating metal via the source electrode metal pedestal 16. 21, the thermal resistance decreases and at the same time the temperature fI! inside the channel is reduced, which equalizes the temperature distribution and enables stable RF operation.This rounding increases the saturated output power and at the same time increases the The linearity of the output power is increased, and cross-modulation distortion is reduced.At the same time as the above-mentioned improvement in heat dissipation, the grounding inductance of the source is also extremely small, which improves the power gain, resulting in higher efficiency. Furthermore, although the structure of the present invention is a single-attached three-terminal electrode element, the source electrode is the only electrode that applies weight to the chip itself as an Aritz chip. A pole similar to a two-terminal electrode element such as a diode (can be assembled using general assembly technology, and the other gate and drain electrodes are connected using a beam lead structure, so GaA
@ Chips are rounded with no load applied, and there is less possibility of cracks, distortions, etc. occurring in the GaAs substrate, and a highly reliable device can be realized. Furthermore, in contrast to the conventional chip mounting and wire bonding processes that were required for chip assembly, the structure of the present invention allows bonding of chips and beam leads to be performed using the same bonding equipment and in one factory. ), and the number of bonding steps can be significantly reduced compared to conventional methods.

As described above, the structure of the present invention can be extremely suitable for future high frequency and high output MICs. Although the above description has been made using gallium arsenide as an example of a compound semiconductor, it is clear that the content of the present invention is not limited by the material of the semiconductor.

[Brief explanation of the drawing]

FIG. 1 is a perspective view showing an assembly diagram of a conventional GaAs FF5T, and FIG. 2 is a beam lead type G according to an embodiment of the present invention.
FIG. 3 is a perspective view showing the structure of mAs PET, and FIG. 3 is a sectional view showing the mounting structure of the FET of the present invention. l...FET nap, 2.21... Heat dissipation metal. 3.17...Gate electrode, 4.18...
・Drain electrode, 5...Input dielectric substrate, 6.
...Output dielectric substrate, 7,2T...Input metallization layer, 8.25...Output metalization layer,
9, 10, 13... Bonding wire, 11.1
5... Source electrode, 12... Heat radiation metal protrusion, 14... GaAs substrate, 16...
...Electrode metal pedestal% 19.20...Beam lead electrode metal. Figure 3

Claims (1)

[Claims] A source electrode is formed on the entire surface of a semiconductor substrate, a pedestal-like member made of a conductor is formed on the source electrode,
A gate electrode and a drain electrode are formed on the semiconductor substrate with the source electrode sandwiched therebetween. The field effect transistor further comprises a beam-shaped electrode terminal fixedly formed on the upper surface of each of the gate electrode and the drain electrode.