JPH10242377A - High-frequency power amplifier module - Google Patents
High-frequency power amplifier moduleInfo
- Publication number
- JPH10242377A JPH10242377A JP9040371A JP4037197A JPH10242377A JP H10242377 A JPH10242377 A JP H10242377A JP 9040371 A JP9040371 A JP 9040371A JP 4037197 A JP4037197 A JP 4037197A JP H10242377 A JPH10242377 A JP H10242377A
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- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はＵＨＦからマイクロ
波帯の信号の増幅を行う高周波電力増幅器モジュールに
係り、特に誘電体基板を多層に用いた高周波電力増幅器
モジュールの構成に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency power amplifier module for amplifying a microwave band signal from UHF, and more particularly to a high-frequency power amplifier module using a dielectric substrate in a multilayer structure.
【０００２】[0002]
【従来の技術】半導体トランジスタを用いた高周波電力
増幅器モジュールは移動体通信の携帯電話機のキーデバ
イスであり、その需要は近年急激に伸びている。上記用
途に適した高周波電力増幅器モジュールとしては移動体
通信システムに対する高周波特性の仕様を満足すること
はもちろんであるが、これに加えて小型，低コストであ
ることが要求されている。これらの要求を満たすため、
従来提案されていた高周波電力増幅器モジュールの一例
としてはIEEE 1996 Microwave and Millimeter−Wave M
onolithic Circuit Symposium, pp.13−16,“A Miniatu
rized GaAs PowerAmplifier for 1.5 GHz Digital Cell
ular Phones”(従来例１）において論じられている。2. Description of the Related Art A high-frequency power amplifier module using a semiconductor transistor is a key device of a mobile telephone for mobile communication, and the demand thereof has been rapidly increasing in recent years. As a high-frequency power amplifier module suitable for the above-mentioned application, it is not only required to satisfy the specifications of the high-frequency characteristics for the mobile communication system, but also small and low-cost. To meet these requirements,
An example of a conventionally proposed high-frequency power amplifier module is IEEE 1996 Microwave and Millimeter-Wave M.
onolithic Circuit Symposium, pp.13-16, “A Miniatu
rized GaAs PowerAmplifier for 1.5 GHz Digital Cell
ular Phones "(conventional example 1).
【０００３】従来例１の高周波電力増幅器モジュールは
図２に示すように、アルミナからなる誘電体基板５１，
５２，５３，５４，５５を多層に用い、それらの層間お
よび表面に金属配線を設けることによりストリップ線路
を多層に形成して小型化を図っている。これらのストリ
ップ線路はバイアス回路および整合回路の一部を構成し
ている。金属配線５０１，５０２，５０３はストリップ
線路を構成するストリップ線路、金属配線５６，５７，
５８は接地導体である。５９はチップ抵抗あるいはチッ
プコンデンサである。能動素子であるＧａＡｓ ＦＥＴ
を形成したＧａＡｓチップ５０４は多層基板の中に形成
されたキャビティ中に挿入される形で、アルミナ誘電体
基板５１の上面に実装されている。多層基板の上部を金
属キャップ５００によって覆い、１個のモジュールを形
成している。この高周波電力増幅器モジュールは裏面電
極５６を介してマザーボードに接合され、ＧａＡｓチッ
プ５０４において発生した熱は主にアルミナ誘電体基板
５１を通じてマザーボードに放熱されている。As shown in FIG. 2, a high-frequency power amplifier module according to Conventional Example 1 has a dielectric substrate 51 made of alumina,
52, 53, 54, 55 are used in multiple layers, and strip wiring is formed in multiple layers by providing metal wirings between the layers and on the surface to achieve miniaturization. These strip lines form part of a bias circuit and a matching circuit. The metal wirings 501, 502, 503 are strip lines constituting the strip line, the metal wirings 56, 57,
58 is a ground conductor. Reference numeral 59 denotes a chip resistor or a chip capacitor. GaAs FET as active element
Is mounted on the upper surface of the alumina dielectric substrate 51 so as to be inserted into a cavity formed in the multilayer substrate. The upper part of the multilayer substrate is covered with a metal cap 500 to form one module. This high-frequency power amplifier module is bonded to the motherboard via the back electrode 56, and the heat generated in the GaAs chip 504 is radiated to the motherboard mainly through the alumina dielectric substrate 51.
【０００４】この従来例１では出力電力１.１Ｗ クラス
の高周波電力増幅器モジュールを上記構成により小型化
し、その面積を１cm×１cmまで縮小していた。In the prior art 1, a high-frequency power amplifier module having an output power of 1.1 W class was downsized by the above configuration, and its area was reduced to 1 cm × 1 cm.
【０００５】上記従来例１では受動素子の一つとしてス
トリップ線路が用いられているが、これに替えてスパイ
ラルインダクタを用いることによって、モジュールをさ
らに小型化する提案がなされており、例えば１９９５年
電子情報通信学会エレクトロニクスソサエティ大会講演
論文集Ｃ−４３頁“オンチップ高誘電体キャパシタを用
いた移動体通信用超小型フロントエンドＨＩＣ”（従来
例２）において論じられている。[0005] In the above prior art example 1, a strip line is used as one of the passive elements. However, a proposal has been made to further reduce the size of the module by using a spiral inductor instead. This is discussed in the Proceedings of the IEICE Electronics Society Conference, page C-43, "Ultra-small front-end HIC for mobile communication using on-chip high-dielectric capacitors" (Conventional Example 2).
【０００６】従来例２の高周波モジュールは図３に示す
ように、セラミックからなる誘電体基板６１上にＧａＡ
ｓ ＩＣチップ６４をフリップチップ方式によって接続
し、スパイラルインダクタ６２は誘電体基板６１上の金
属パタン６０により形成してＨＩＣ（ハイブリッド集積
回路）モジュールを構成している。ＧａＡｓ ＩＣチッ
プ６４の主面（図３では下面）にはＧａＡｓ ＦＥＴ
(電界効果トランジスタ)およびキャパシタが形成され、
これらはＣＣＢ（Controlled Collapse Bonding)バンプ
６５によって誘電体基板６１上の金属パタン６０に接続
されている。スパイラルインダクタ６２の一端は誘電体
基板６１の表面の金属パタン６０へ、他の一端はスルー
ホール６３を介して基板裏面の金属パタン６６に接続さ
れている。As shown in FIG. 3, a high-frequency module according to Conventional Example 2 has GaAs on a dielectric substrate 61 made of ceramic.
s An IC chip 64 is connected by a flip chip method, and a spiral inductor 62 is formed by a metal pattern 60 on a dielectric substrate 61 to constitute a HIC (hybrid integrated circuit) module. A GaAs FET is provided on the main surface (the lower surface in FIG. 3) of the GaAs IC chip 64.
(Field effect transistor) and a capacitor are formed,
These are connected to a metal pattern 60 on a dielectric substrate 61 by CCB (Controlled Collapse Bonding) bumps 65. One end of the spiral inductor 62 is connected to a metal pattern 60 on the front surface of the dielectric substrate 61, and the other end is connected to a metal pattern 66 on the back surface of the substrate via a through hole 63.
【０００７】この従来例２では比較的大きな面積を必要
とするスパイラルインダクタを安価な誘電体基板上への
印刷技術により形成したこと、および高価なＧａＡｓ
ＩＣチップの面積を少なくしたことにより、高周波半導
体装置の製造コストを低減している。また、ＧａＡｓ
ＩＣチップをフリップチップ方式により接続したことに
よりワイヤボンディング方式に比べて高さを縮小し、高
周波モジュールの小型化を図っている。In the prior art 2, a spiral inductor requiring a relatively large area is formed by a printing technique on an inexpensive dielectric substrate, and expensive GaAs is used.
By reducing the area of the IC chip, the manufacturing cost of the high-frequency semiconductor device is reduced. In addition, GaAs
By connecting the IC chips by the flip chip method, the height is reduced as compared with the wire bonding method, and the high frequency module is downsized.
【０００８】[0008]
【発明が解決しようとする課題】上記従来技術ではさら
に出力電力の大きな電力増幅器に対してその技術を適用
し、モジュールの小型化を図った場合、高出力トランジ
スタの放熱が不十分となり電力増幅器の特性が劣化する
問題があった。たとえば欧州のデジタルセルラであるＧ
ＳＭ(Global System for Mobile Communication）では
出力電力３.８Ｗ以上のクラスの電力増幅器が主に必要
とされている。例えばこのクラスの電力増幅器に上記従
来例１のモジュールを適用した場合、アルミナ誘電体基
板５１の熱抵抗を１５.６℃／Ｗ ，ＧａＡｓチップ５０
４上の高出力トランジスタの電力付加効率を４８％と仮
定するとＧａＡｓチップの温度は周囲の温度に比べ６４
℃上昇する。この温度上昇により高出力トランジスタの
相互コンダクタンスが低下し、出力電力値の低下や効率
の劣化が生じた。In the above prior art, when the technology is applied to a power amplifier having a larger output power and the module is downsized, the heat dissipation of the high output transistor becomes insufficient and the power amplifier is not used. There was a problem that the characteristics deteriorated. For example, G, the European digital cellular
In SM (Global System for Mobile Communication), a power amplifier of an output power of 3.8 W or more is mainly required. For example, when the module of the prior art 1 is applied to a power amplifier of this class, the thermal resistance of the alumina dielectric substrate 51 is 15.6 ° C./W, and the GaAs chip 50
Assuming that the power-added efficiency of the high-power transistor on 4 is 48%, the temperature of the GaAs chip is 64% lower than the ambient temperature.
℃ rise. Due to this rise in temperature, the transconductance of the high-output transistor is reduced, and the output power value is reduced and the efficiency is reduced.
【０００９】さらに電力増幅器モジュールを低コスト化
するという観点から、高出力トランジスタとして高価な
ＧａＡｓ ＦＥＴに替え、単価の安いシリコンＭＯＳＦ
ＥＴを採用することが望ましい。しかしシリコンＭＯＳ
ＦＥＴでは効率が低下するため、例えば電力付加効率を
３５％と仮定した場合、周囲温度が２５℃の場合でもＳ
ｉチップの温度は１３５℃にまで上昇する。この状態で
は、電力増幅器の動作が劣化するだけではなく、モジュ
ールにおけるハンダの信頼性も悪化するため、シリコン
ＭＯＳＦＥＴの採用による電力増幅器モジュールの低コ
スト化は困難であった。Further, from the viewpoint of reducing the cost of the power amplifier module, a high-output transistor is replaced with an expensive GaAs FET, and a low-cost silicon MOSF is used.
It is desirable to use ET. But silicon MOS
Since the efficiency is reduced in the FET, for example, assuming that the power added efficiency is 35%, even if the ambient temperature is 25 ° C., the S
The temperature of the i-chip rises to 135 ° C. In this state, not only does the operation of the power amplifier deteriorate, but also the reliability of the solder in the module deteriorates, so that it has been difficult to reduce the cost of the power amplifier module by employing silicon MOSFETs.
【００１０】上記従来例１の構造で放熱性を改善する方
法としてはアルミナ誘電体基板５１に替えて窒化アルミ
基板を採用し、熱抵抗を約１／１０まで低減することが
容易に考えつく。しかしこの場合窒化アルミ基板がアル
ミナ基板に対してはるかに高価なため、高周波電力増幅
器モジュールを低コストで提供することは困難になっ
た。As a method of improving the heat dissipation in the structure of the above-mentioned conventional example 1, it is easily conceivable to adopt an aluminum nitride substrate instead of the alumina dielectric substrate 51 and to reduce the thermal resistance to about 1/10. However, in this case, since the aluminum nitride substrate is much more expensive than the alumina substrate, it has been difficult to provide a high-frequency power amplifier module at low cost.
【００１１】上記従来例２の構造を電力増幅器に採用し
た場合、ＧａＡｓ ＩＣチップ６４で発生した熱は、Ｃ
ＣＢバンプ６５の接触面のみを通ってセラミック基板６
１に放熱されるため、ＧａＡｓ ＩＣチップ６４から基
板裏面６６までの熱抵抗は上記従来例１より比べて高く
なる。このため高出力トランジスタの放熱が不十分とな
り電力増幅器の特性が劣化した。When the structure of the above-mentioned conventional example 2 is adopted for a power amplifier, the heat generated in the GaAs IC chip 64 is C
The ceramic substrate 6 passes only through the contact surface of the CB bump 65
1, the thermal resistance from the GaAs IC chip 64 to the back surface 66 of the substrate is higher than that of the first conventional example. For this reason, the heat dissipation of the high-output transistor was insufficient, and the characteristics of the power amplifier deteriorated.
【００１２】本発明の目的は高出力トランジスタの放熱
性を改善するモジュールの構成を提案し、小型化および
低コスト化に最適な高周波電力増幅器モジュールを提供
することにある。An object of the present invention is to propose a module configuration that improves the heat dissipation of a high-output transistor, and to provide a high-frequency power amplifier module that is optimal for miniaturization and cost reduction.
【００１３】[0013]
【課題を解決するための手段】本目的は多層の誘電体基
板を用いた高周波電力増幅器モジュールにおいて、多層
誘電体基板の表面に樹脂層を設け、誘電体基板の層間に
第１の配線層を設け、その第１の配線層の下部に誘電体
層を貫く第１の穴または溝を設け、その第１の穴または
溝の内部に第１の配線層に接続した金属板を挿入し、そ
の金属板の下面の高さを多層誘電体基板の下面に対し±
５０μｍ以内で一致させ、第１の配線層の上部には誘電
体と樹脂層を貫く第２の穴を設け、第２の穴は第１の穴
または溝より小さく、第１の穴または溝の内側に位置さ
せ、その第２の穴の内部に半導体チップを挿入し、その
半導体チップの裏面を金属板に接合し、スパイラルイン
ダクタを含む受動素子を多層誘電体基板の表面および樹
脂層の表面に設けることにより達成できる。SUMMARY OF THE INVENTION An object of the present invention is to provide a high-frequency power amplifier module using a multilayer dielectric substrate, in which a resin layer is provided on the surface of the multilayer dielectric substrate, and a first wiring layer is provided between layers of the dielectric substrate. A first hole or groove penetrating the dielectric layer is provided below the first wiring layer, and a metal plate connected to the first wiring layer is inserted into the first hole or groove. The height of the lower surface of the metal plate is ±
Matching within 50 μm, a second hole penetrating the dielectric and the resin layer is provided above the first wiring layer, and the second hole is smaller than the first hole or the groove. A semiconductor chip is inserted inside the second hole, the back surface of the semiconductor chip is bonded to a metal plate, and a passive element including a spiral inductor is mounted on the surface of the multilayer dielectric substrate and the surface of the resin layer. This can be achieved by providing.
【００１４】第１の穴または溝の内部に第１の配線層に
接続した金属板を設けたことにより、この金属板の裏面
を接地電位に固定することで第１の配線層および金属板
の表面電位を高周波において良好に接地することが可能
になる。Since the metal plate connected to the first wiring layer is provided inside the first hole or the groove, the back surface of the metal plate is fixed at the ground potential, so that the first wiring layer and the metal plate are fixed. The surface potential can be satisfactorily grounded at a high frequency.
【００１５】その金属板の下面を多層誘電体基板の下面
に対し±５０μｍ以内で一致させて設けたことにより、
マザーボードに対し高周波電力増幅器モジュールをハン
ダなどにより接続が容易となる。By providing the lower surface of the metal plate within ± 50 μm with the lower surface of the multilayer dielectric substrate,
The connection of the high-frequency power amplifier module to the motherboard by soldering or the like becomes easy.
【００１６】半導体チップを金属板上に接合したことに
より、半導体チップの放熱を熱抵抗の非常に低い金属板
を通じてできるため、放熱性を著しく改善できる。さら
に高出力トランジスタのソース電極がチップ裏面にある
場合、例えば低コスト化する目的で高出力シリコンＭＯ
ＳＦＥＴを適用する場合には、半導体チップ裏面を高周
波的に良好に接地できる。これらの作用により高出力ト
ランジスタの高周波特性の劣化を最小に抑えられる。Since the semiconductor chip is bonded to the metal plate, heat can be radiated from the semiconductor chip through the metal plate having a very low thermal resistance, so that the heat radiation can be remarkably improved. Further, when the source electrode of the high-output transistor is on the back surface of the chip, for example, a high-output silicon
When an SFET is applied, the back surface of the semiconductor chip can be satisfactorily grounded at high frequencies. By these actions, deterioration of the high-frequency characteristics of the high-output transistor can be minimized.
【００１７】多層誘電体基板の表面および樹脂層の表面
に受動素子を設けることにより、チップ抵抗，チップコ
ンデンサをなくし、モジュールを小型化することができ
る。また受動素子は多数のモジュール基板上に一括プロ
セスで形成できるため、受動素子を含むモジュールを、
ばらつきの点で歩留まり良くかつ低コストに製造でき
る。By providing passive elements on the surface of the multilayer dielectric substrate and on the surface of the resin layer, chip resistors and chip capacitors can be eliminated, and the module can be downsized. In addition, since passive elements can be formed on a large number of module substrates in a batch process, modules containing passive elements
It can be manufactured with good yield and low cost in terms of variation.
【００１８】[0018]
＜実施例１＞本発明の実施例１を図１および図４を用い
て説明する。本実施例１は高出力トランジスタとしてシ
リコンＭＯＳＦＥＴを用いた高周波電力増幅器モジュー
ルである。図１はモジュールを側面から見た断面構造
図、図４はモジュールを下方から見た裏面レイアウトを
示す図である。<Embodiment 1> Embodiment 1 of the present invention will be described with reference to FIGS. The first embodiment is a high-frequency power amplifier module using a silicon MOSFET as a high-output transistor. FIG. 1 is a cross-sectional structural view of the module as viewed from the side, and FIG. 4 is a diagram illustrating a back surface layout of the module as viewed from below.
【００１９】図１を用いて高周波増幅器モジュールの構
造および製造方法を説明する。アルミナセラミックから
なる誘電体基板１１，１２に対し、配線層１８，１９，
２０を印刷技術により形成し、誘電体基板１１，１２を
貫き配線層をつなぐようにバイアホール２２をメッキ技
術により形成する。誘電体基板１１にはあらかじめ溝１
４をパターニングしておく。配線層１８，１９，２０の
材質としては通常は銅、あるいは銀と白金の積層膜を用
いる。これらの基板はおよび配線層は同時に焼結し、１
枚の多層アルミナセラミック基板を形成する。The structure and manufacturing method of the high-frequency amplifier module will be described with reference to FIG. For dielectric substrates 11 and 12 made of alumina ceramic, wiring layers 18 and 19,
20 is formed by a printing technique, and a via hole 22 is formed by a plating technique so as to penetrate the dielectric substrates 11 and 12 and connect the wiring layers. The dielectric substrate 11 has grooves 1 in advance.
4 is patterned. As a material of the wiring layers 18, 19, and 20, a copper or a laminated film of silver and platinum is usually used. These substrates and the wiring layer are sintered simultaneously,
A multi-layer alumina ceramic substrate is formed.
【００２０】次に誘電体基板１２上に薄膜容量２４およ
び薄膜抵抗２５を形成する。通常、薄膜容量２４の材料
としてはＴａ−Ｏ等、薄膜抵抗２５の材料としてはＴａ
−Ｎ等が選ばれる。Next, a thin film capacitor 24 and a thin film resistor 25 are formed on the dielectric substrate 12. Usually, the material of the thin film capacitor 24 is Ta-O or the like, and the material of the thin film resistor 25 is Ta.
-N or the like is selected.
【００２１】次に誘電体基板１２上にポリイミドからな
る樹脂膜１３およびバイアホール２３，配線層２１を形
成する。この時点では誘電体基板１２の表面に穴や溝が
形成されていないので、樹脂膜１３は平坦性よく、厚さ
をほぼ一定に形成できる。配線層２１の材質としては通
常銅とニッケルと金の積層膜あるいは銀と白金の積層膜
を用い、これらは主にメッキ技術により被着する。配線
層２１は素子間をつなぐ配線としてだけではなく、スパ
イラルインダクタを形成し、薄膜容量２４および薄膜抵
抗２５とともに整合回路の一部を構成する。Next, a resin film 13 made of polyimide, a via hole 23, and a wiring layer 21 are formed on the dielectric substrate 12. At this point, since no holes or grooves are formed on the surface of the dielectric substrate 12, the resin film 13 can be formed with good flatness and a substantially constant thickness. As a material of the wiring layer 21, a laminated film of copper, nickel, and gold or a laminated film of silver and platinum is generally used, and these are mainly applied by a plating technique. The wiring layer 21 forms a spiral inductor and forms a part of a matching circuit together with the thin film capacitor 24 and the thin film resistor 25, as well as a wiring connecting the elements.
【００２２】次にレーザー加工法により誘電体基板１２
および樹脂膜１３を貫く穴１５を形成する。この穴１５
のサイズは溝１４より小さくし、穴１５は上方から見て
溝１４の内部に位置するように設ける。Next, the dielectric substrate 12 is formed by a laser processing method.
Then, a hole 15 penetrating through the resin film 13 is formed. This hole 15
Is smaller than the groove 14, and the hole 15 is provided so as to be located inside the groove 14 when viewed from above.
【００２３】次に溝１４の中に金属板１６を挿入し、配
線層１９に接続する。そして穴１５の中にシリコンＭＯ
ＳＦＥＴを表面に形成した半導体チップ１７を挿入し、
その裏面を金属板１６に接続する。金属板１６の厚さ
は、金属板１６の下面の高さと誘電体基板１１の下面の
高さがほぼ一致するように選ぶ。その精度は±５０μｍ
以内にすることが好ましい。Next, a metal plate 16 is inserted into the groove 14 and connected to the wiring layer 19. And the silicon MO in the hole 15
Insert the semiconductor chip 17 having the SFET formed on the surface,
The back surface is connected to the metal plate 16. The thickness of the metal plate 16 is selected so that the height of the lower surface of the metal plate 16 and the height of the lower surface of the dielectric substrate 11 substantially match. Its accuracy is ± 50μm
It is preferable to set it within.
【００２４】次に半導体チップ１７と配線層２１をボン
ディングワイヤ２６で接続し、メタルキャップ２７でふ
たをすることにより高周波電力増幅器モジュールが完成
する。Next, the semiconductor chip 17 and the wiring layer 21 are connected by bonding wires 26 and covered with a metal cap 27 to complete a high-frequency power amplifier module.
【００２５】次に図４を用いて高周波電力増幅器モジュ
ールへの信号の出し入れおよび電源の供給の方法を説明
する。まず接地電位ＧＮＤは金属板１６および必要に応
じて配線層１８からなる電極に接続する。電源電圧Ｖdd
は配線層１８からなる電極（Ｖdd）に接続し、バイアホ
ール２２等を通じて高出力トランジスタのドレインに電
流を供給する。出力制御電圧Ｖapc は配線層１８からな
る電極（Ｖapc ）に接続し、バイアホール２２等を通じ
て高出力トランジスタのゲートに電圧を印加する。入力
高周波電力Ｐinは配線層１８からなる電極（Ｐin）に接
続し、バイアホール２２等を通じて基板表面に形成した
薄膜容量，スパイラルインダクタからなる入力整合回路
に送られる。電力増幅器で増幅された出力高周波電力Ｐ
out はバイアホール２２等を通じて配線層１８からなる
電極（Ｐout ）より取り出す。以上の様に全ての信号お
よび電源はリードレスの状態のまま与えることができ、
高周波電力モジュールの面積を最小にすることができ
る。Next, a method for inputting / outputting signals to / from the high-frequency power amplifier module and supplying power will be described with reference to FIG. First, the ground potential GND is connected to an electrode composed of the metal plate 16 and, if necessary, the wiring layer 18. Power supply voltage Vdd
Is connected to the electrode (Vdd) formed of the wiring layer 18 and supplies a current to the drain of the high-power transistor through the via hole 22 and the like. The output control voltage Vapc is connected to an electrode (Vapc) formed of the wiring layer 18 and applies a voltage to the gate of the high output transistor through the via hole 22 or the like. The input high-frequency power Pin is connected to an electrode (Pin) composed of the wiring layer 18 and sent to an input matching circuit composed of a thin film capacitor and a spiral inductor formed on the substrate surface through the via hole 22 and the like. Output high frequency power P amplified by power amplifier
out is taken out from the electrode (Pout) composed of the wiring layer 18 through the via hole 22 or the like. As described above, all signals and power can be given in a leadless state,
The area of the high-frequency power module can be minimized.
【００２６】本実施例１によれば、高周波電力増幅器モ
ジュールの低コスト化の観点から高出力トランジスタと
してシリコンＭＯＳＦＥＴを採用した場合にも充分な放
熱性を確保でき、発熱量の増大による性能劣化を対策で
きる。また半導体チップ裏面を高周波的に良好な接地が
できるため、シリコンＭＯＳＦＥＴの高周波特性の劣化
を最小に抑えられる。以上の作用によりシリコンＭＯＳ
ＦＥＴを適用でき、低コスト化に適した電力増幅器モジ
ュールを実現できる。According to the first embodiment, from the viewpoint of reducing the cost of the high-frequency power amplifier module, sufficient heat dissipation can be ensured even when a silicon MOSFET is used as a high-output transistor, and performance degradation due to an increase in the amount of heat generated is prevented. Can take measures. In addition, since the back surface of the semiconductor chip can be grounded with good frequency in terms of high frequency, deterioration of the high frequency characteristics of the silicon MOSFET can be minimized. With the above operation, silicon MOS
An FET can be applied, and a power amplifier module suitable for cost reduction can be realized.
【００２７】また図４において、金属板１６の上下には
溝１４の余白部分（誘電体基板１２が表出している部
分）を設けているが、この溝１４の余白部分はそこにメ
タルキャップ２７に設けたフックまたは突起部分２００
を引っかけ、モジュール基板に対するメタルキャップ２
７の容易な取り付けを実現できる効果を持つ。In FIG. 4, blank portions of the groove 14 (portions where the dielectric substrate 12 is exposed) are provided above and below the metal plate 16, and the blank portion of the groove 14 is provided with a metal cap 27. Hook or projection 200 provided on
To the metal cap 2 for the module board.
7 has the effect of realizing easy mounting.
【００２８】上記従来例１において１４の形状を溝型と
したが、これはキャビティ状の穴としてもよい。また樹
脂膜１３の材質はポリイミドとしたがＢＣＢ（ベンゾシ
クロブデン）を用いてもよい。この場合には、ＢＣＢ樹
脂膜１３の誘電率がポリイミドより小さくなるため、受
動素子の寄生容量を低減でき、高周波特性を改善する効
果を有する。また半導体チップ１７はシリコンＭＯＳＦ
ＥＴを形成したシリコンチップとしたが、これはもちろ
んＧａＡｓ ＦＥＴを形成したＧａＡｓチップやシリコ
ンバイポーラトランジスタを形成したシリコンチップで
あってもよい。また配線層２１によりスパイラルインダ
クタを形成したが、さらに配線層２１によりマイクロス
トリップ線路を形成し、整合回路の一部を構成してもよ
い。この場合モジュールの面積は多少増大するものの、
出力整合回路による電力損失を低減し、電力増幅器モジ
ュールの電力効率を向上する効果を持つ。In the above-mentioned conventional example 1, the shape of the groove 14 is used, but it may be a cavity-like hole. Although the material of the resin film 13 is polyimide, BCB (benzocyclobutene) may be used. In this case, the dielectric constant of the BCB resin film 13 is smaller than that of polyimide, so that the parasitic capacitance of the passive element can be reduced, and the effect of improving high-frequency characteristics can be obtained. The semiconductor chip 17 is a silicon MOSF
Although the silicon chip has the ET formed thereon, it may be, of course, a GaAs chip having a GaAs FET formed thereon or a silicon chip having a silicon bipolar transistor formed thereon. Although the spiral inductor is formed by the wiring layer 21, a microstrip line may be further formed by the wiring layer 21 to constitute a part of the matching circuit. In this case, although the area of the module is slightly increased,
This has the effect of reducing power loss due to the output matching circuit and improving the power efficiency of the power amplifier module.
【００２９】[0029]
【発明の効果】本発明によれば、高出力トランジスタで
生じる熱を熱抵抗の小さな金属板を通じて放熱するた
め、放熱性が良好なモジュールを構成でき、さらに薄膜
受動素子の適用により小型化および低コスト化に最適な
高周波電力増幅器モジュールを実現できる。According to the present invention, the heat generated by the high-output transistor is radiated through the metal plate having a small thermal resistance, so that a module having good heat radiation can be constructed. A high-frequency power amplifier module optimal for cost reduction can be realized.
【図１】本発明による実施例１の高周波増幅器モジュー
ルの断面図。FIG. 1 is a sectional view of a high-frequency amplifier module according to a first embodiment of the present invention.
【図２】従来例１の高周波増幅器モジュールの断面図。FIG. 2 is a cross-sectional view of a high-frequency amplifier module of Conventional Example 1.
【図３】従来例２のハイブリッド集積回路モジュールの
断面図。FIG. 3 is a cross-sectional view of a hybrid integrated circuit module of Conventional Example 2.
【図４】本発明による実施例１の高周波増幅器モジュー
ルの裏面レイアウト図。FIG. 4 is a back layout diagram of the high-frequency amplifier module according to the first embodiment of the present invention.
１１，１２…誘電体基板、１３…樹脂膜、１４…溝、１
５…穴、１６…金属板、１７…半導体チップ、１８〜２
１…配線層、２２…バイアホール、２３…バイアホー
ル、２４…薄膜容量、２５…薄膜抵抗、２６…ボンディ
ングワイヤ、２７…メタルキャップ、５１〜５５…誘電
体基板、５６〜５８…接地導体、５９…チップ抵抗ある
いはチップコンデンサ、６０…金属パタン、６１…誘電
体基板、６２…スパイラルインダクタ、６３…スルーホ
ール、６４…ＧａＡｓ ＩＣチップ、６５…ＣＣＢバン
プ、６６…金属パタン、２００…メタルキャップのフッ
クまたは突起部分、５００…金属キャップ、５０１〜５
０３…金属配線、５０４…ＧaＡsチップ。11, 12: dielectric substrate, 13: resin film, 14: groove, 1
5 ... Hole, 16 ... Metal plate, 17 ... Semiconductor chip, 18-2
DESCRIPTION OF SYMBOLS 1 ... Wiring layer, 22 ... Via hole, 23 ... Via hole, 24 ... Thin film capacitor, 25 ... Thin film resistance, 26 ... Bonding wire, 27 ... Metal cap, 51-55 ... Dielectric substrate, 56-58 ... Ground conductor, 59: chip resistor or chip capacitor, 60: metal pattern, 61: dielectric substrate, 62: spiral inductor, 63: through hole, 64: GaAs IC chip, 65: CCB bump, 66: metal pattern, 200: metal cap Hook or projection, 500 ... metal cap, 501-5
03: metal wiring, 504: GaAs chip.
Claims (4)
誘電体基板と、上記第１の誘電体基板上に形成した第１
の配線層と上記第１の誘電体基板上に積層した単一ある
いは多層の誘電体からなる第２の誘電体基板を有する高
周波電力増幅器モジュールにおいて、第１の誘電体基板
を貫く第１の穴もしくは溝を設け、第１の穴もしくは溝
の内部に第１の配線層に接続した金属板を設け、上記金
属板の下面の高さを上記第１の誘電体基板の下面の高さ
に対し±５０μｍ以内で一致させ、上記第２の誘電体基
板を貫き、その側面が上記第１の穴もしくは溝の側面よ
り内側に位置し、その大きさが上記第１の穴もしくは溝
より小さな第２の穴を設け、上記金属板に対し裏面を接
続した半導体チップを第２の穴の内部に設け、上記半導
体チップの表面に能動素子を形成し、上記第２の誘電体
基板上にインダクタを含む受動素子を設けたことを特徴
とする高周波電力増幅器モジュール。A first dielectric substrate formed of a single or multi-layer dielectric; and a first dielectric substrate formed on the first dielectric substrate.
A high frequency power amplifier module having a second dielectric substrate made of a single or multilayer dielectric laminated on the first dielectric substrate, and a first hole penetrating the first dielectric substrate. Alternatively, a groove is provided, a metal plate connected to the first wiring layer is provided inside the first hole or the groove, and the height of the lower surface of the metal plate is made higher than the height of the lower surface of the first dielectric substrate. Aligned within ± 50 μm, penetrated the second dielectric substrate, the side surface of which is located inside the side surface of the first hole or groove, and the second side of which is smaller than the first hole or groove. A semiconductor chip having a back surface connected to the metal plate is provided in the second hole, an active element is formed on the surface of the semiconductor chip, and an inductor is provided on the second dielectric substrate. High frequency power increase characterized by the provision of passive elements Breadth module.
誘電体基板と、上記第１の誘電体基板上に形成した第１
の配線層と上記第１の誘電体基板上に積層した単一ある
いは多層の誘電体からなる第２の誘電体基板と上記第２
の誘電体基板上に積層した樹脂層を有する高周波電力増
幅器モジュールにおいて、第１の誘電体基板を貫く第１
の穴もしくは溝を設け、第１の穴もしくは溝の内部に第
１の配線層に接続した金属板を設け、上記金属板の下面
の高さを上記第１の誘電体基板の下面の高さに対し±５
０μｍ以内で一致させ、上記第２の誘電体基板および上
記樹脂層を貫き、その側面が上記第１の穴もしくは溝の
側面より内側に位置し、その大きさが上記第１の穴もし
くは溝より小さな第２の穴を設け、上記金属板に対し裏
面を接続した半導体チップを第２の穴の内部に設け、上
記半導体チップの表面に能動素子を形成し、上記樹脂層
上および上記第２の誘電体基板上にインダクタを含む受
動素子を設けたことを特徴とする高周波電力増幅器モジ
ュール。2. A first dielectric substrate comprising a single or multi-layer dielectric, and a first dielectric substrate formed on the first dielectric substrate.
A second dielectric substrate composed of a single or multi-layer dielectric laminated on the first dielectric substrate and the second dielectric substrate;
A high frequency power amplifier module having a resin layer laminated on the first dielectric substrate, wherein the first dielectric substrate penetrates the first dielectric substrate.
And a metal plate connected to the first wiring layer is provided inside the first hole or groove, and the height of the lower surface of the metal plate is set to the height of the lower surface of the first dielectric substrate. ± 5 for
Aligned within 0 μm, penetrated the second dielectric substrate and the resin layer, the side face was located inside the side face of the first hole or groove, and the size was larger than that of the first hole or groove. A small second hole is provided, a semiconductor chip having a back surface connected to the metal plate is provided inside the second hole, an active element is formed on a surface of the semiconductor chip, and a second chip is provided on the resin layer and the second chip. A high-frequency power amplifier module comprising a passive element including an inductor provided on a dielectric substrate.
て、上記第１の配線層を接地導体とし、上記第２の誘電
体基板上に形成した第２の配線層をストリップ導体とし
たマイクロストリップ線路を有し、上記マイクロストリ
ップ線路が電力増幅器の出力整合回路の一部をなすこと
を特徴とする高周波電力増幅器モジュール。3. A microstrip according to claim 1, wherein said first wiring layer is a ground conductor, and said second wiring layer formed on said second dielectric substrate is a strip conductor. A high frequency power amplifier module having a line, wherein the microstrip line forms a part of an output matching circuit of a power amplifier.
誘電体基板、および上記第１の誘電体基板上に形成した
第１の配線層、および上記第１の誘電体基板上に積層し
た単一あるいは多層の誘電体からなる第２の誘電体基板
を同時に焼結して形成し、上記第１の誘電体基板を貫く
第１の穴もしくは溝は焼結前にパターニングし、上記第
２の誘電体基板上に樹脂層を形成した後にレーザー加工
により上記第２の誘電体基板および上記樹脂層を貫く穴
を形成し、第１の穴もしくは溝の内部に第１の配線層に
接続した金属板を設け、上記金属板に裏面を接続した半
導体チップを接続し、上記樹脂層上および上記第２の誘
電体基板上にインダクタを含む受動素子を設けたことを
特徴とする高周波電力増幅器モジュールの製造方法。4. A first dielectric substrate made of a single or multi-layer dielectric, a first wiring layer formed on the first dielectric substrate, and laminated on the first dielectric substrate. A second dielectric substrate made of a single or multi-layered dielectric is sintered and formed at the same time, and a first hole or groove penetrating the first dielectric substrate is patterned before sintering. After forming a resin layer on the second dielectric substrate, a hole is formed through the second dielectric substrate and the resin layer by laser processing, and connected to the first wiring layer inside the first hole or groove. A high-frequency power amplifier, comprising: a metal plate, a semiconductor chip having a back surface connected to the metal plate, and a passive element including an inductor provided on the resin layer and the second dielectric substrate. Module manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9040371A JPH10242377A (en) | 1997-02-25 | 1997-02-25 | High-frequency power amplifier module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9040371A JPH10242377A (en) | 1997-02-25 | 1997-02-25 | High-frequency power amplifier module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10242377A true JPH10242377A (en) | 1998-09-11 |
Family
ID=12578796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9040371A Pending JPH10242377A (en) | 1997-02-25 | 1997-02-25 | High-frequency power amplifier module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10242377A (en) |
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|---|---|---|---|---|
| KR20010055094A (en) * | 1999-12-09 | 2001-07-02 | 조덕수 | Hybrid amplifier module integrated circuit for used in a handset and method for fabricating the same |
| WO2002078086A3 (en) * | 2001-03-27 | 2003-07-31 | Ericsson Inc | Power transistor package with integrated flange for surface mount heat removal |
| JP2005500685A (en) * | 2001-08-14 | 2005-01-06 | スカイワークス ソリューションズ，インコーポレイテッド | Structure of leadless chip carrier with embedded inductor and method for its fabrication |
| KR100618759B1 (en) * | 1998-10-26 | 2006-08-31 | 다이요 유덴 가부시키가이샤 | Hybrid module |
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1997
- 1997-02-25 JP JP9040371A patent/JPH10242377A/en active Pending
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|---|---|---|---|---|
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| KR20010055094A (en) * | 1999-12-09 | 2001-07-02 | 조덕수 | Hybrid amplifier module integrated circuit for used in a handset and method for fabricating the same |
| WO2002078086A3 (en) * | 2001-03-27 | 2003-07-31 | Ericsson Inc | Power transistor package with integrated flange for surface mount heat removal |
| JP2005500685A (en) * | 2001-08-14 | 2005-01-06 | スカイワークス ソリューションズ，インコーポレイテッド | Structure of leadless chip carrier with embedded inductor and method for its fabrication |
| US8736034B2 (en) | 2005-02-24 | 2014-05-27 | Freescale Semiconductor, Inc. | Lead-frame circuit package |
| WO2006090204A1 (en) * | 2005-02-24 | 2006-08-31 | Freescale Semiconductor, Inc. | Lead-frame circuit package |
| JP2009071016A (en) * | 2007-09-13 | 2009-04-02 | Ibiden Co Ltd | Electronic component and manufacturing method thereof |
| EP2575167A2 (en) | 2011-09-30 | 2013-04-03 | Fujitsu Limited | Electronic device |
| JP2013077746A (en) * | 2011-09-30 | 2013-04-25 | Fujitsu Ltd | Electronic device |
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| JP2014175409A (en) * | 2013-03-07 | 2014-09-22 | Toshiba Corp | Package for high frequency semiconductor |
| US11437362B2 (en) | 2015-03-31 | 2022-09-06 | Wolfspeed, Inc. | Multi-cavity package having single metal flange |
| US10468399B2 (en) | 2015-03-31 | 2019-11-05 | Cree, Inc. | Multi-cavity package having single metal flange |
| US9629246B2 (en) | 2015-07-28 | 2017-04-18 | Infineon Technologies Ag | PCB based semiconductor package having integrated electrical functionality |
| US9997476B2 (en) | 2015-10-30 | 2018-06-12 | Infineon Technologies Ag | Multi-die package having different types of semiconductor dies attached to the same thermally conductive flange |
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| WO2017200561A1 (en) * | 2016-05-18 | 2017-11-23 | Macom Technology Solutions Holdings, Inc. | High-power amplifier package |
| US9960127B2 (en) | 2016-05-18 | 2018-05-01 | Macom Technology Solutions Holdings, Inc. | High-power amplifier package |
| US10700023B2 (en) | 2016-05-18 | 2020-06-30 | Macom Technology Solutions Holdings, Inc. | High-power amplifier package |
| US11367674B2 (en) | 2016-08-10 | 2022-06-21 | Macom Technology Solutions Holdings, Inc. | High power transistors |
| US10134658B2 (en) | 2016-08-10 | 2018-11-20 | Macom Technology Solutions Holdings, Inc. | High power transistors |
| US11862536B2 (en) | 2016-08-10 | 2024-01-02 | Macom Technology Solutions Holdings, Inc. | High power transistors |
| FR3094565A1 (en) * | 2019-03-28 | 2020-10-02 | Stmicroelectronics (Grenoble 2) Sas | Cooling of electronic devices |
| US12080660B2 (en) | 2021-04-13 | 2024-09-03 | Macom Technology Solutions Holdings, Inc. | Package with different types of semiconductor dies attached to a flange |
| CN114613751A (en) * | 2022-03-01 | 2022-06-10 | 中国电子科技集团公司第十研究所 | High-power three-dimensional stacked three-dimensional integrated radio frequency front end micro-system |
| CN114613751B (en) * | 2022-03-01 | 2023-11-07 | 中国电子科技集团公司第十研究所 | High-power three-dimensional stacked three-dimensional integrated radio frequency front end microsystem |
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