JPH07321130A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a field effect transistor structure which is lessened in unwanted coupling between input and output and capable of operating stably in a semiconductor device which contains field effect transistors used for a high-frequency power amplifier that is of UHF band, small in size, and easily assembled. CONSTITUTION:Field effect transistors 20 and 30 which are provided to regions located on the prime surface of a semiconductor substrate 10, equipped with a gate electrode composed of gate electrode fingers 21 and 31 respectively, and cascade-connected together through an outer circuit are provided in a semiconductor device, wherein a groove 11 is provided between the above regions on the prime surface of the substrate 10.

Description

Detailed Description of the Invention

[0001]

The present invention relates to the UHF band (0.3 to 3).
(GHz) multi-stage high-frequency power amplifier field effect transistor structure.

[0002]

2. Description of the Related Art As a UHF band high frequency power amplifier used for mobile communication or the like, a multi-stage source grounded circuit using a GaAs field effect transistor (FET) is used. GaAsFETs have excellent gain in power amplification in the UHF band, but are used in cascade connection in two or more stages when the required output power cannot be obtained by only one-stage amplification. In this case, a matching circuit is required for connection between the FETs and impedance matching with the input / output. Further, since the output power of the GaAs FET is proportional to its gate width, a gate width of several mm or more is usually required to obtain the output power of several hundred mW or more. In order to obtain such a long gate width, a planar structure of an FET called a comb structure in which a gate electrode is divided into a plurality of gate electrode fingers and connected in parallel is used.

For such a UHF band high frequency power amplifier, downsizing and simplification of assembly are desired.
However, in the conventional structure, a matching circuit for impedance matching is required before and after the FET.
Since the distributed constant circuit is used in the F band, there is a limit to miniaturization. In addition, the FE not included in the package
Although it is possible to reduce the size by using T, in this case, the FET, particularly the GaAs FET, is liable to damage the semiconductor chip itself, and the assembling process is difficult. On the other hand, an MMI in which an FET and a matching circuit are integrated on a semiconductor substrate
C (Microwave Monolithic Integrated Circuit) is known. However, in the UHF band, the size of the matching circuit is relatively large and the substrate area is large, resulting in high cost and difficulty in assembly and adjustment, which is not suitable for a mass production process.

In order to solve such a problem, an amplifier using a special FET (hereinafter referred to as cascade multi-stage FET) in which a plurality of FETs connected in series on a single semiconductor substrate is independently provided has been studied. ing. An example of this cascaded multi-stage FET and an amplifier using the same will be described with reference to FIG. The cascade multi-stage FET 1 is composed of a front stage FET 20 and a rear stage FET.
30 is provided on the same substrate and is packaged. The front stage drain terminal 3 of the front stage FET 20 and the rear stage FE
The rear gate terminal 4 of T30 is provided adjacent to one side of the package, and the front gate terminal 2 of the front FET 20 is provided.
And the rear-stage drain terminal 5 of the rear-stage FET 30 is provided close to the other side opposite to the one side thereof.
The common source terminal 6 common to the latter stage FET 30 is provided on the back surface of the package. The illustrated power amplifier circuit 4
0 is composed of a cascaded multi-stage FET 1, an input matching circuit 50 on the dielectric substrate 41, an inter-stage matching circuit 60, and an output matching circuit 70.

The input signal of the power amplification circuit 40 is input to the front stage FET 20 via the input matching circuit 50. That is, the input signal of the power amplifier circuit 40 is input to the input strip line 51 matched to the input characteristic impedance and guided to the front gate terminal 2 via the input matching strip line 52. Input matching strip line 52
Is connected to the input strip line 51 via a DC cut capacitor 53, and is also connected to one end of a bias supply strip line 54. The other end of the bias supply strip line 54 is connected to the dielectric substrate 4
The ground plane 42 above 1 is grounded via the bypass capacitor 55, and the gate bias voltage of the preceding FET 20 is supplied. The input characteristic impedance and the input of the preceding stage FET 20 are matched by the input matching strip line 52, the bias supply strip line 54, and the like.
Although not shown, the common source terminal 6 of the cascade multi-stage FET 1 is the back surface ground plate 48 on the back surface of the dielectric substrate 41.
It is connected to the.

The output signal of the front stage FET 20 is input to the rear stage FET 30 via the interstage matching circuit 60. That is, the output signal of the front stage FET 20 is output from the front stage drain terminal 3 and guided to the rear stage gate terminal 4 via the interstage matching strip line 62. The inter-stage matching strip line 62 is separated in terms of direct current by a matching capacitor 63 arranged in the middle thereof, and one end of the bias supplying strip lines 64 and 66 is connected to each. The other ends of the bias supply strip lines 64 and 66 are grounded to the ground planes 43 and 44 on the dielectric substrate 41 via the bypass capacitors 65 and 67, and the front-stage FET
The drain voltage of 20 and the gate bias voltage of the post-stage FET 30 are supplied.

The output signal of the post-stage FET 30 is obtained as the output of the power amplification circuit 40 through the output matching circuit 70.
That is, the output signal of the post-stage FET 30 is output from the post-stage drain terminal 5, and the output of the power amplification circuit 40 is obtained from the output stripline 71 matched to the output characteristic impedance via the output matching stripline 72. Output matching strip line 72 and dielectric substrate 41
A matching capacitor 78 between the upper ground planes 45, 46,
79 is arranged. One end of the output matching strip line 72 is connected to the output strip line 71 via the DC cutting capacitor 73, and is also connected to one end of the bias supplying strip line 74. The other end of the bias supply strip line 74 is connected to the dielectric substrate 41.
The upper ground plane 45 is grounded via the bypass capacitor 75, and the drain voltage of the post-stage FET 20 is supplied. The output matching strip line 72, the bias supply strip line 74, and the like match the output of the post-stage FET 30 with the output characteristic impedance.

In the above amplifier, the FET elements forming the two-stage amplifier circuit are provided on one semiconductor substrate, and the output of the preceding stage is provided adjacent to the input of the following stage. Can be provided adjacent to one FET device. Therefore, since the matching circuit is not provided between the two separate FET elements, the amplifier can be downsized and the mounting becomes easy.

[0009]

However, in the above-mentioned cascaded multi-stage FET, when the output of the preceding stage and the input of the succeeding stage are brought close to each other, the input of the preceding stage and the output of the succeeding stage are necessarily brought close to each other. Therefore, there are problems that the input side and the output side of the multistage amplifier circuit come close to each other, electrical coupling occurs, unnecessary feedback is applied, and the operation becomes unstable.
The present invention has solved such a problem, and an object of the present invention is to provide a semiconductor device including a field effect transistor used in a UHF band high frequency power amplifier having a structure capable of downsizing and facilitating assembly. An object of the present invention is to provide a structure of a field effect transistor that operates stably with less unnecessary coupling between outputs.

[0010]

According to the present invention, there are provided a plurality of gate electrodes each provided in a plurality of regions on one main surface of a semiconductor substrate, the gate electrodes being composed of a plurality of gate electrode fingers, and connected in cascade by an external circuit. A semiconductor device including the field effect transistor, wherein a groove is provided on the one main surface between the regions, and / or a gate electrode finger included in the one field effect transistor and another field effect transistor. The directions in which the gate electrode fingers included in are extending are orthogonal to each other. A semiconductor device including a plurality of field effect transistors, each of which is provided in each of a plurality of regions on one main surface of a semiconductor substrate, has a gate electrode formed of a plurality of gate electrode fingers, and is cascade-connected by an external circuit. The source electrode of the field effect transistor is connected to a back surface electrode on the other main surface of the semiconductor substrate via a conductive portion provided inside the semiconductor substrate, or the source electrode of the field effect transistor is It is desirable that they are provided so as not to be connected to each other on the one main surface but to be connected to the external circuit by independent wirings.

Further, it is preferable that the semiconductor substrate is made of GaAs, and the gate electrode, the drain electrode and the source electrode constitute a Schottky junction type field effect transistor. The direction in which the gate electrode fingers extend is orthogonal to each other, and the angle may be not only 90 degrees but also 80 to 100 degrees.

[0012]

[Advantageous Effects] With the above structure, since the groove is provided on the front surface of the semiconductor substrate between the regions where the FETs are provided, the electric field, especially the capacitance, of the substrate surface between the FETs is provided. Coupling can be reduced. Alternatively and / or additionally, since the extending directions of the gate electrode fingers are orthogonal to each other, it is possible to reduce the electrical, particularly electromagnetic inductive coupling between the FETs on the substrate surface. Therefore, in the field effect transistor used in the amplifier having a structure that can be downsized and can be easily assembled, unnecessary coupling between input and output is reduced, and stable operation is possible.

Furthermore, by connecting the source electrode to the back electrode through a conductive portion called a via hole provided inside the semiconductor substrate, wiring for connecting to an external circuit does not intersect on the surface of the semiconductor substrate. , The electrical coupling is reduced and the mechanical stability is improved. In addition, the source electrodes are not connected to each other on the surface of the semiconductor substrate, but by connecting to an external circuit by independent wiring, different circuit elements are added to the source electrodes of each stage according to the design conditions of the amplifier. Therefore, the multistage amplifier can be stably operated according to the purpose.

Therefore, by using the semiconductor device according to the present invention, the semiconductor device can be easily mounted on the amplifier, the amplifier can be miniaturized, and at the same time, stable operation can be achieved. In addition, the substrate area of the semiconductor device can be reduced as compared with the case where the two elements are separated, and the cost of the semiconductor device can be reduced.

Further, the semiconductor substrate is made of GaAs,
When the FET element constitutes a Schottky junction field effect transistor, a high amplification gain is obtained in the UHF band, and the effect of cost reduction due to the reduction of the substrate area is remarkable. Further, when the matching circuit includes a distributed constant circuit, it is useful in the UHF band where the mounting area is relatively large.

[0016]

First Embodiment A GaAs field effect transistor according to the first embodiment of the present invention will be described with reference to FIG. 1 which is a plan view thereof. On a semiconductor substrate 10 made of semi-insulating GaAs, a front stage FET 20 constituting a front stage of a two-stage power amplifier for amplifying a signal of about 1 GHz and a rear stage FET 30 constituting a rear stage thereof.
Are formed. This front FET20, rear FET3
0 is an input of 7 dBm in the front stage FET 20 and is connected to the rear stage FET 30 by impedance matching and cascade connection.
It is designed so that an output of 31 dBm and a power gain of 24 dB can be obtained.

The pre-stage FET 20 is arranged on the right side of the semiconductor substrate 10 and has ten gate electrode fingers 22 which serve as gate electrodes on the active layer region 21 formed by the ion implantation method.
And the drain electrode 23 and the source electrode 2 sandwiching it
It is composed of 4. Gate electrode finger 22, drain electrode 2
3 and the source electrode 24 are connected to the gate pad 25, the drain pad 26, and the source pad 27, which are the respective lead-out regions. Similarly, the latter stage FET
30 is arranged on the left side of the semiconductor substrate 10 and is composed of 34 gate electrode fingers 32 which are gate electrodes on the active layer region 31 formed by the ion implantation method, and a drain electrode 33 and a source electrode 34 sandwiching the gate electrode fingers 32. To be done. The gate electrode finger 32, the drain electrode 33, and the source electrode 34 are connected to a gate pad 35, a drain pad 36, and a source pad 37, which are respective lead regions. The length of the front gate electrode finger 22 is 0.2 mm, the gate width of the front FET 20 is 2.0 mm, and the length of the rear gate electrode finger 32 is about 0.35 mm.
The gate width of the post-stage FET 30 is 12 mm.

The gate electrode fingers 22 and 32 have a gate length of 0.8 μm and are made of a Ti metal layer formed by vapor deposition and form Schottky junctions with the active regions 21 and 31. Drain electrodes 23 and 33 and source electrode 2
4, 34 comprises a metal layer formed by successive vapor deposition of AuGe / Ni / Au in ohmic contact with the active regions 21, 31, at the same time the metal layer comprises gate pads 25, 35, drain pads 26, 36 and sources. The pads 27 and 37 are formed. The gate electrode fingers 22 and 32 and the gate pads 25 and 35 are M formed by vapor deposition.
It is connected by gate buses 28 and 38 made of an o / Au metal layer. The source electrodes 24 and 34 intersect the gate buses 28 and 38 in the air by air bridges and are connected to the source pads 27 and 37, but the semiconductor substrate 10 is formed by other wire wiring, multilayer wiring via insulating layers, or the like.
You can also connect on the main surface of.

The main surface of the semiconductor substrate 10 is rectangular,
It is divided by one long side 12, another long side 13 facing it, a short side 15, and another short side 16 facing it. The gate electrode fingers 22 and 32 extend in a direction perpendicular to the long side 12, that is, in a direction parallel to the short side 15,
It is arranged in the central portion of the semiconductor substrate 10. The drain electrodes 23 and 33 and the source electrodes 24 and 34 are adjacent to each other so as to sandwich the gate electrode fingers 22 and 32 and extend in a strip shape in a direction perpendicular to the long side 12. The gate pad 25 of the front FET 20 includes the gate electrode finger 22 and the other long side 13
And the drain pad 26 is arranged between the gate electrode finger 22 and the long side 12. Second stage FET
The gate pad 35 of 30 includes the gate electrode finger 32 and the long side 1
2 and the drain pad 36 thereof is arranged between the gate electrode finger 32 and the other long side 13. The source pads 27 and 37 are the gate pads 2 respectively.
It is arranged so as to surround 5, 35.

A groove 11 is provided in a region between the source electrodes 27 and 37 between the front FET 20 and the rear FET 30. The groove 11 has a width of 30 μm and a depth of 20 μm, and is provided parallel to the short side 15. This groove 11
Thus, the electrical coupling between the gate electrode finger 22, the gate pad 25 and the drain electrode 33, the drain pad 36 can be weakened. The width and depth of the groove 11 are preferably about 0.2 to 0.4 times the thickness of the semiconductor substrate 10,
If it is about 0.2 times or less, the electric coupling cannot be sufficiently weakened, and if it is about 0.4 times or more, the semiconductor substrate 10
It becomes difficult to handle because the mechanical strength of is weakened. By setting the groove 11 in a direction parallel to any side of the semiconductor substrate 10, the groove 11 can be formed at the same time when the semiconductor substrate 10 is cut, and the manufacturing is easy.

The field effect transistor according to the first embodiment is used in the amplifying circuit shown in FIG. 4, and the gate pads 25 and 35 are used as the front gate terminal 2, the rear gate terminal 4, the front drain terminal 3 and the rear drain terminal 5. By using the drain pad and the drain pad, respectively, not only the amplifier can be downsized and the mounting can be simplified, but also the electrical coupling between the gate of the front-stage FET 20 and the drain of the rear-stage FET 30 can be suppressed low. Therefore, the operation of the amplifier becomes stable. The source pads 27 and 37 are connected to the ground plane on the dielectric substrate 41 by independent bonding wires. By adjusting the length of this bonding wire,
It is possible to adjust the amount of inductance connected between the source electrode of 20 and the FET 30 of the subsequent stage and the ground at the time of assembly.
This makes it possible to make adjustments according to variations between FET elements and the purpose of use of the amplifier circuit.

[0022]

Second Embodiment A GaAs field effect transistor according to a second embodiment of the present invention will be described with reference to FIG. 2 (a) which is a plan view thereof and FIG. 2 (b) which is a sectional view thereof. In the second embodiment, the source electrodes 24 and 34 and the source pad 27,
The second embodiment is similar to the first embodiment except that 37 is connected to the back surface electrode 19 of the semiconductor substrate 10 by the via holes 29 and 39, and the description of the same parts is omitted. For the via holes 29 and 39, after all the electrodes on the front surface side are formed, the back surface of the semiconductor substrate 10 is thinly polished to form the source pads 27, 3
A region where 7 is formed is provided with a through hole having a diameter of 50 μm from the back surface side by dry etching or the like, and then the inside of this through hole is filled with a highly conductive metal such as gold (Au) by electrolytic plating. To be done. At that time, the back surface electrode 19 can be provided at the same time. The back surface electrode 19 is provided on the entire back surface of the semiconductor substrate 10.
It is common to T20 and the post-stage FET 30.

The field effect transistor according to the second embodiment is used in the amplifier circuit shown in FIG. 4 described above, and the gate pads 25 and 35 are used as the front gate terminal 2, the rear gate terminal 4, the front drain terminal 3 and the rear drain terminal 5. By using the drain pad and the drain pad, respectively, not only the size of the amplifier can be reduced and the mounting can be simplified, but also the source electrode and the source electrode can be connected to the via holes and 39.
By connecting to the back surface electrode 19, an unnecessary inductance component is not inserted between the source and the ground, and excellent high frequency characteristics can be obtained at a relatively high frequency. Since it is not necessary to dispose the bonding wire for connecting the source on the semiconductor substrate 10, there is no restriction on the disposition, electrical coupling between the electrodes can be avoided, and mechanically stable. It becomes a structure.

[0024]

[Embodiment 3] A GaAs field effect transistor according to a third embodiment of the present invention will be described with reference to FIG. 3 which is a plan view thereof. The third embodiment is the same as the first embodiment except that the electrodes forming the pre-stage FET 20 are arranged rotated by 90 degrees, and the groove 11 is not provided. The description is omitted. The gate electrode finger 22 of the front FET 20 extends in the direction parallel to the long side 12, and the gate electrode finger 32 of the rear FET 30 extends in the direction perpendicular to the long side 12. The drain electrodes 23 and 33 and the source electrode 24,
34 extend adjacent to each other so as to sandwich the gate electrode fingers 22 and 32 in a strip shape. The gate pad 25 of the front FET 20 is arranged between the gate electrode finger 22 and the short side 15, and the drain pad 26 thereof is arranged between the gate electrode finger 22 and the gate electrode finger 23 of the rear FET 30. The gate pad 35 of the post-stage FET 30 is arranged between the gate electrode finger 32 and the long side 12, and the drain pad 36 thereof is arranged between the gate electrode finger 32 and the other long side 13.

The field effect transistor according to the third embodiment is used in the amplifying circuit shown in FIG. 4, and the gate pads 25 and 35 are used as the front gate terminal 2, the rear gate terminal 4, the front drain terminal 3 and the rear drain terminal 5, respectively. By using the drain pad and the drain pad, respectively, not only the size of the amplifier can be reduced and the mounting can be simplified, but also the gate electrode fingers 22 and 32 are made orthogonal to each other, and the gate of the front-stage FET 20 and the drain of the rear-stage FET 30 are connected. Since the distance can be increased, the electrical coupling can be suppressed to a low level, and the operation of the amplifier becomes stable. In this case, by providing the groove 11 as in the first embodiment,
Furthermore, the electrical coupling can be lowered. The source electrodes 24 and 34 are connected to the ground plane on the dielectric substrate 41 by independent bonding wires.
It is also possible to connect to the back surface electrode 19 by 39.

In the above embodiments, the GaAs field effect transistor which is not housed in the package has been described. However, the same structure is adopted even if the field effect transistor is housed in a package made of ceramics or the like for easy handling. It is clear that you can do it. Further, the length, width, number, constituent materials, and the like of the source electrode, the drain electrode, and the gate electrode finger can be appropriately selected so as to form a multistage amplifier.

[Brief description of drawings]

FIG. 1 shows a grooved GaAs according to a first embodiment of the present invention.
It is a top view which shows the structure of a field effect transistor.

FIG. 2 is a plan view (a) and a sectional view (b) showing a structure of a GaAs field effect transistor having a via hole connection according to a second embodiment of the present invention.

FIG. 3 is a plan view showing the structure of a GaAs field effect transistor in which the gate electrode fingers are orthogonal to each other according to the third embodiment of the present invention.

FIG. 4 is a plan view showing the structure of a power amplifier circuit using cascaded multi-stage FETs.

[Explanation of symbols]

 10 Semiconductor Substrate 11 Groove 12 Long Side 13 Other Long Side 15 Short Side 16 Other Short Side 19 Back Side Electrode 20 Front Stage FET 30 Post Stage FET 21, 31 Active Layer Region 22, 32 Gate Electrode Finger 23, 33 Drain Electrode 24, 34 Source electrode 25,35 Gate pad 26,36 Drain pad 27,37 Source pad 28,38 Gate bus 29,39 Via hole

Front page continuation (72) Inventor Masanori Ejima 3-17-35, Shinsōnan, Toda City, Saitama Prefecture, Japan Energy Co., Ltd.

Claims (5)

[Claims] 1. A semiconductor device including a plurality of field effect transistors, each of which is provided in a plurality of regions on one main surface of a semiconductor substrate, has a gate electrode composed of a plurality of gate electrode fingers, and is cascade-connected by an external circuit. The semiconductor device according to claim 1, wherein a groove is provided on the one main surface between the regions. 2. A semiconductor device including a plurality of field effect transistors, each of which is provided in each of a plurality of regions on one main surface of a semiconductor substrate, has a gate electrode composed of a plurality of gate electrode fingers, and is cascade-connected by an external circuit. 2. The semiconductor device according to claim 1, wherein the extending directions of the gate electrode fingers included in one of the field effect transistors and the gate electrode fingers included in the other of the field effect transistors are orthogonal to each other. 3. The semiconductor device according to claim 2, wherein a groove is provided on the one main surface between the regions. 4. The source electrodes of at least two field effect transistors are connected to a back surface electrode on the other main surface of the semiconductor substrate via a conductive portion provided inside the semiconductor substrate. The semiconductor device according to claim 1, wherein 5. The source electrode of the field effect transistor is not connected to each other on the one main surface, but is provided so as to be connected to the external circuit by independent wirings. The semiconductor device according to claim 1.