JP2003115732A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2003115732A JP2003115732A JP2001307358A JP2001307358A JP2003115732A JP 2003115732 A JP2003115732 A JP 2003115732A JP 2001307358 A JP2001307358 A JP 2001307358A JP 2001307358 A JP2001307358 A JP 2001307358A JP 2003115732 A JP2003115732 A JP 2003115732A
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- semiconductor device
- matching circuit
- impedance
- output
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- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2924/161—Cap
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- Microwave Amplifiers (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、内部整合回路を有
する半導体装置に関し、特に、増幅用素子として低イン
ピーダンスの高周波、高出力用トランジスタを実装する
半導体装置に適用して有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an internal matching circuit, and more particularly to a technique effective when applied to a semiconductor device having a low impedance high frequency and high output transistor mounted as an amplifying element. is there.
【０００２】[0002]
【従来の技術】現在マイクロ波用のトランジスタは、高
周波化、高出力化が進んでおり、様々な通信機器に実装
されて広く使われている。特に、携帯電話等の移動体通
信用基地局に用いられる高出力アンプに要求される出力
パワーは、近年大幅に増加している。2. Description of the Related Art At present, microwave transistors are being used in various communication devices and are being widely used because of higher frequency and higher output. In particular, the output power required for a high-power amplifier used in a mobile communication base station such as a mobile phone has greatly increased in recent years.
【０００３】前記高出力アンプに用いられているＦＥＴ
では、高出力化に対処するために有効であることから、
トランジスタのゲート幅を増加させているが、こうした
ゲート幅の増加に伴いトランジスタの入出力のインピー
ダンスが低下している。FET used in the high-power amplifier
Then, since it is effective for dealing with higher output,
Although the gate width of the transistor is increased, the input / output impedance of the transistor is reduced as the gate width is increased.
【０００４】このため入出力インピーダンスの低下に対
処して、インピーダンスの整合をはかるために、半導体
装置外部の整合回路だけではなく、半導体装置内部に整
合回路を内蔵した構成が主流となっている。For this reason, in order to cope with the decrease of the input / output impedance and to perform the impedance matching, not only the matching circuit external to the semiconductor device but also the structure incorporating the matching circuit inside the semiconductor device is predominant.
【０００５】このような内部整合回路を内蔵した半導体
装置に関しては、例えば、特開平４−３２１３０８号公
報、特開平７−７４５５７号公報に開示されており、図
１は、こうした従来の内部整合回路を有する半導体装置
の構成を示している。Semiconductor devices incorporating such an internal matching circuit are disclosed in, for example, Japanese Patent Laid-Open Nos. 4-321308 and 7-74557, and FIG. 1 shows such a conventional internal matching circuit. 1 illustrates a configuration of a semiconductor device having a.
【０００６】図１に示す例では、ＦＥＴ１が実装される
パッケージ２内に、入力側と出力側のメタライズパター
ン３により形成される内部整合回路を実装し、ＦＥＴ１
とメタライズパターン３とをボンディングワイヤ４によ
って接続し、メタライズパターン３を入出力のリード５
と接続する構成となっている。このメタライズパターン
３は、ＦＥＴ１の入出力のインピーダンスを変換し、外
部回路によるインピーダンス整合を容易として、外部整
合回路とともに、ＦＥＴ１の性能を引き出す構成となっ
ている。In the example shown in FIG. 1, the internal matching circuit formed by the input side and output side metallized patterns 3 is mounted in the package 2 in which the FET 1 is mounted, and
And the metallization pattern 3 are connected by a bonding wire 4, and the metallization pattern 3 is connected to the input / output lead 5
It is configured to connect with. The metallized pattern 3 converts the input / output impedance of the FET 1 to facilitate impedance matching by an external circuit and bring out the performance of the FET 1 together with the external matching circuit.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、近年の
基地局用トランジスタでは、大幅な高出力化の要求に伴
い、更にゲート幅の大きなトランジスタが必要とされて
おり、入出力共にインピーダンスは更に小さくなってき
ている。このため、従来の内部整合回路を実装した構成
としても、半導体装置のインピーダンスを十分に増加さ
せて整合をとることが困難になってきている。However, in the recent transistor for base station, a transistor having a larger gate width is required in accordance with the demand for a significantly high output, and the impedance of both input and output is further reduced. Is coming. For this reason, even with the configuration in which the conventional internal matching circuit is mounted, it is becoming difficult to sufficiently increase the impedance of the semiconductor device to achieve matching.
【０００８】例えば、１００Ｗ以上の出力のトランジス
タとしてＦＥＴを用いた場合には、そのゲート幅は数十
ｃｍとなり、そのインピーダンスは０．１Ω程度とな
る。このような非常に低いインピーダンスの場合には、
従来の半導体装置のパッケージ内に整合回路を設けた構
成にしても、インピーダンス変換が困難となる。For example, when an FET is used as a transistor having an output of 100 W or more, its gate width is several tens of cm and its impedance is about 0.1Ω. With such a very low impedance,
Impedance conversion becomes difficult even if the matching circuit is provided in the package of the conventional semiconductor device.
【０００９】これは、一般に、整合回路に求められる性
能として、インピーダンス変換比と周波数比帯域があ
り、これらの特性は構成回路素子数をパラメータとして
トレードオフの関係にあるためである。整合回路素子数
を増やせば帯域を広くすることはできるが、回路規模が
大きくなるため、内部整合回路として用いるには、パッ
ケージサイズの制約もあり実用的ではない。また、デバ
イスのインピーダンスが低くなるにつれて、整合に用い
る素子の寄生抵抗の影響が強くなるため、ゲート幅に比
例して出力電力の増加させるのが難しくなっている。This is because the impedance conversion ratio and the frequency ratio band are generally required as performances of the matching circuit, and these characteristics have a trade-off relationship with the number of constituent circuit elements as a parameter. Although it is possible to widen the band by increasing the number of matching circuit elements, the circuit scale becomes large, so that it is not practical to use it as an internal matching circuit due to package size restrictions. Further, as the impedance of the device becomes lower, the influence of the parasitic resistance of the element used for matching becomes stronger, which makes it difficult to increase the output power in proportion to the gate width.
【００１０】以上のように、インピーダンスが非常に小
さい高出力ＦＥＴに対して、内部整合回路を実装して半
導体装置を構成する手法をとっても、広い周波数帯域と
低損失性を同時に確保するのは難しくなってきている。
即ち、インピーダンス変換の機能を内部整合回路にもた
せ、外部整合回路の負担を減らし、整合回路全体の損失
低減、高帯域化を図ることで、ＦＥＴの特性を十分に引
き出すことが困難になってきている。As described above, it is difficult to secure a wide frequency band and low loss at the same time even if a semiconductor device is constructed by mounting an internal matching circuit on a high-power FET whose impedance is very small. It has become to.
That is, it is difficult to bring out the FET characteristics sufficiently by providing the internal matching circuit with the function of impedance conversion, reducing the load on the external matching circuit, reducing the loss of the entire matching circuit, and increasing the bandwidth. There is.
【００１１】このため、内部整合回路を実装できる領域
を有し、インピーダンス変換の機能をもたせた図２に示
す半導体装置が考えられた。Therefore, the semiconductor device shown in FIG. 2 having an area for mounting an internal matching circuit and having a function of impedance conversion has been considered.
【００１２】この半導体装置では、ＦＥＴが形成された
半導体チップ１１と容量チップ６とが金属板を用いたス
テム７に固定されており、半導体チップ１１と容量チッ
プ６とはセラミック等の絶縁材を用いた矩形環状の枠体
８に周囲を囲まれており、この枠体８にリード５が固定
されている。In this semiconductor device, a semiconductor chip 11 on which an FET is formed and a capacitor chip 6 are fixed to a stem 7 using a metal plate, and the semiconductor chip 11 and the capacitor chip 6 are made of an insulating material such as ceramic. The periphery is surrounded by the rectangular annular frame body 8 used, and the lead 5 is fixed to the frame body 8.
【００１３】リード５と容量チップ６とはボンディング
ワイヤ４によって電気的に接続され、容量チップ６と半
導体チップ１１のゲートパッド或いはドレインパッドと
はボンディングワイヤ９によって接続され、半導体チッ
プ１１のドレインパッドと出力用のリード５とはボンデ
ィングワイヤ１０によって接続されている。The lead 5 and the capacitance chip 6 are electrically connected by the bonding wire 4, the capacitance chip 6 and the gate pad or drain pad of the semiconductor chip 11 are connected by the bonding wire 9, and the drain pad of the semiconductor chip 11 is connected. The output lead 5 is connected by a bonding wire 10.
【００１４】図３はこの半導体装置の等価回路図であ
る。ソース接地されたＦＥＴのゲート電極と入力端子Ｉ
Ｎとの間及びドレイン電極と出力端子ＯＵＴとの間に、
夫々信号を効率良く伝達するための整合回路（図２中破
線図示）が実装されている。FIG. 3 is an equivalent circuit diagram of this semiconductor device. Source grounded FET gate electrode and input terminal I
Between N and between the drain electrode and the output terminal OUT,
Matching circuits (shown by broken lines in FIG. 2) for efficiently transmitting signals are mounted.
【００１５】入力側の整合回路はリード５と接続したボ
ンディングワイヤ４による直列インダクタＬ１と、容量
チップ６による並列キャパシタＣ１と、半導体チップ１
１と接続するボンディングワイヤ９による直列インダク
タＬ２とから構成され、リード５は、枠体８のセラミッ
クを介して接地されているステム７との間に並列キャパ
シタＣｉｎが並列に接続されていることになる。The matching circuit on the input side has a series inductor L1 formed by a bonding wire 4 connected to a lead 5, a parallel capacitor C1 formed by a capacitance chip 6, and a semiconductor chip 1.
The parallel capacitor Cin is connected in parallel between the lead 5 and the stem 7 grounded via the ceramic of the frame body 8. Become.
【００１６】この半導体装置では、リード５をキャパシ
タとしても利用することによって、インピーダンス変換
を効率化することができるが、リードの大きさには制限
があるため、その制限によってキャパシタの容量に限界
がある。In this semiconductor device, impedance conversion can be made more efficient by using the lead 5 also as a capacitor. However, since the size of the lead is limited, the capacitance of the capacitor is limited by the limitation. is there.
【００１７】本発明は上述した問題点を解決することを
目的としてなされたものであり、性能の劣化が少ないイ
ンピーダンス変換機能をもつ整合回路によって、大きな
ゲート幅を有する高出力ＦＥＴの高周波、高出力特性を
十分に引き出すことのできる半導体装置を提供すること
にある。本発明の前記ならびにその他の課題と新規な特
徴は、本明細書の記述及び添付図面によって明らかにな
るであろう。The present invention has been made for the purpose of solving the above-mentioned problems, and a matching circuit having an impedance conversion function with less deterioration in performance is provided with a high-power FET having a large gate width at high frequencies and high outputs. An object of the present invention is to provide a semiconductor device which can sufficiently bring out the characteristics. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【００１８】[0018]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。半導体チップと電気的に接続され
た入力用或いは出力用のリードが、前記半導体チップを
収容する絶縁材の枠体に固定されている半導体装置にお
いて、前記入力用或いは出力用リードの少なくとも何れ
かが、前記枠体に固定される部位に、前記枠体により支
持される端面開放の線路と接続され、前記リードがオー
プンスタブを備える構成となる整合回路を有する。Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows. In a semiconductor device in which an input or output lead electrically connected to a semiconductor chip is fixed to a frame of an insulating material that accommodates the semiconductor chip, at least one of the input or output lead is A matching circuit, which is connected to a line whose end face is open and is supported by the frame, and the lead includes an open stub, is provided at a portion fixed to the frame.
【００１９】上述した本発明によれば、オープンスタブ
により、インピーダンス変換が行われているので、リー
ドは、インピーダンス変換の機能が強化されていること
になり、内部整合回路に要求されるインピーダンス変換
比を小さくすることが可能となる。According to the present invention described above, since the impedance conversion is performed by the open stub, the lead has an enhanced function of impedance conversion, and the impedance conversion ratio required for the internal matching circuit. Can be reduced.
【００２０】以下、本発明の実施の形態を説明する。な
お、実施の形態を説明するための全図において、同一機
能を有するものは同一符号を付け、その繰り返しの説明
は省略する。The embodiments of the present invention will be described below. In all the drawings for explaining the embodiments, the same reference numerals are given to those having the same function, and the repeated description thereof will be omitted.
【００２１】[0021]
【発明の実施の形態】（実施の形態１）図４は、本発明
の一実施の形態である半導体装置を示す平面図であり、
図５は図４中のａ‐ａ線に沿った縦断面図である。本実
施の形態の高周波高出力用半導体装置は、ＦＥＴが形成
された半導体チップ１１と入力用の整合回路を構成する
容量が形成された容量チップ１２ａと出力用の整合回路
を構成する容量が形成された容量チップ１２ｂとが金属
板を用いたステム１３に固定されている。(First Embodiment) FIG. 4 is a plan view showing a semiconductor device according to an embodiment of the present invention.
FIG. 5 is a vertical sectional view taken along the line aa in FIG. In the semiconductor device for high frequency and high output of the present embodiment, the semiconductor chip 11 in which the FET is formed, the capacitor chip 12a in which a capacitor forming the matching circuit for input is formed, and the capacitor forming the matching circuit for output are formed. The formed capacitance chip 12b is fixed to the stem 13 using a metal plate.
【００２２】半導体チップ１１に形成されたＦＥＴは、
ＧａＡｓ等を用い高周波・高出力の信号を処理するため
に、ＦＥＴのゲート幅の拡大を目的としてマルチフィン
ガ等の構成が採用されており、複数並設されたゲートが
一体化されてゲートパッドに接続され、同様に複数並設
されたドレインが一体化されてドレインパッドに接続さ
れている。複数並設されたソースは一体化されて裏面電
極に接続されステム１３と導通し、接地されている。The FET formed on the semiconductor chip 11 is
In order to process high-frequency, high-power signals using GaAs etc., a structure such as a multi-finger is adopted for the purpose of expanding the gate width of the FET, and a plurality of gates arranged in parallel are integrated into a gate pad. Similarly, a plurality of drains arranged in parallel are integrated and connected to the drain pad. A plurality of sources arranged side by side are integrated and connected to the back surface electrode, are electrically connected to the stem 13, and are grounded.
【００２３】半導体チップ１１と容量チップ１２ａ，１
２ｂとはセラミック等の絶縁材を用いた矩形環状の枠体
１４に周囲を囲まれており、この枠体１４には入出力の
信号を外部回路に伝達するために金属製の入力用のリー
ド１５ａ及び出力用のリード１５ｂが固定されている。
入力側リード１５ａからの高周波信号を半導体チップ１
１のＦＥＴが電力増幅して出力側リード１５ｂに出力す
る構成となっている。更に本実施の形態では、リード１
５ａ，１５ｂは、固定されている枠体１４上にて端面が
開放の線路１６ａ，１６ｂが直交して接続され、リード
１５ａ，１５ｂが夫々オープンスタブを備える構成とな
っている。The semiconductor chip 11 and the capacitive chips 12a, 1
2b is surrounded by a rectangular annular frame body 14 made of an insulating material such as ceramic. The frame body 14 is made of a metal input lead for transmitting an input / output signal to an external circuit. 15a and output lead 15b are fixed.
The high frequency signal from the input side lead 15a is transferred to the semiconductor chip 1
The first FET is configured to amplify the power and output the amplified power to the output side lead 15b. Further, in the present embodiment, the lead 1
5a and 15b are configured such that lines 16a and 16b having open end faces are orthogonally connected to each other on a fixed frame body 14, and leads 15a and 15b each include an open stub.
【００２４】入力用のリード１５ａと容量チップ１２ａ
とはボンディングワイヤ１７によって電気的に接続さ
れ、入力用の容量チップ１２ａと半導体チップ１１のゲ
ートパッドとはボンディングワイヤ１８によって接続さ
れ、半導体チップ１１のドレインパッドと出力用の容量
チップ１２ｂとはボンディングワイヤ１９によって接続
され、半導体チップ１１のドレインパッドと出力用のリ
ード１５ｂとはボンディングワイヤ２０によって接続さ
れている。Input lead 15a and capacitance chip 12a
Are electrically connected by a bonding wire 17, the input capacitance chip 12a and the gate pad of the semiconductor chip 11 are connected by a bonding wire 18, and the drain pad of the semiconductor chip 11 and the output capacitance chip 12b are bonded. The wire 19 is connected, and the drain pad of the semiconductor chip 11 and the output lead 15b are connected by a bonding wire 20.
【００２５】枠体１４の上縁には樹脂層２１を介してリ
ッド２２が固定されており、ステム１３、枠体１４、樹
脂層２１及びリッド２２によって構成される空間に、半
導体チップ１１、容量チップ１２ａ，１２ｂ、リード１
５ａ，１５ｂの内端及びボンディングワイヤ１７，１
８，１９，２０が気密封止されている。A lid 22 is fixed to the upper edge of the frame body 14 via a resin layer 21, and a semiconductor chip 11 and a capacitor are placed in a space formed by the stem 13, the frame body 14, the resin layer 21 and the lid 22. Chip 12a, 12b, lead 1
Inner ends of 5a and 15b and bonding wires 17 and 1
8, 19, 20 are hermetically sealed.
【００２６】図６は本実施の形態の半導体装置の等価回
路図である。本実施の形態では、ソース接地されたＦＥ
Ｔのゲート電極と入力端子ＩＮとの間及びドレイン電極
と出力端子ＯＵＴとの間に、夫々信号を効率良く伝達す
るための整合回路（図４中破線図示）が実装されてい
る。FIG. 6 is an equivalent circuit diagram of the semiconductor device of this embodiment. In this embodiment, the FE whose source is grounded
A matching circuit (shown by a broken line in FIG. 4) for efficiently transmitting a signal is mounted between the gate electrode of T and the input terminal IN and between the drain electrode and the output terminal OUT.
【００２７】入力側の整合回路はリード１５ａと接続し
たボンディングワイヤ１７による直列インダクタＬ１
と、容量チップ１２ａによる並列キャパシタＣ１と、半
導体チップ１１と接続するボンディングワイヤ１８によ
る直列インダクタＬ２とから構成され、入力のリード１
５ａは、低インピーダンスの伝送線路として働いている
ため、等価的に枠体１４のセラミックを介して接地され
ているステム１３との間に並列キャパシタＣｉｎが並列
に接続されていることになる。The matching circuit on the input side is a series inductor L1 formed by a bonding wire 17 connected to the lead 15a.
And a parallel capacitor C1 formed by the capacitance chip 12a and a series inductor L2 formed by a bonding wire 18 connected to the semiconductor chip 11, and the input lead 1
Since 5a acts as a low-impedance transmission line, the parallel capacitor Cin is equivalently connected in parallel with the stem 13 which is equivalently grounded via the ceramic of the frame body 14.
【００２８】更に、リード１５ａは、前記セラミックの
枠体１４上に端面開放の線路１６ａが接続されている形
態となっており、オープンスタブｏｓの機能を備えてい
るために、インピーダンス変換の機能を加えている。Further, the lead 15a has a form in which a line 16a having an open end face is connected to the ceramic frame 14 and has a function of open stub os, and therefore has a function of impedance conversion. In addition.
【００２９】出力側の整合回路は半導体チップ１１と接
続したボンディングワイヤ１９による直列インダクタＬ
３と、直流成分をカットするための容量チップ１２ｂに
よる並列キャパシタＣ２と、リード１５ｂへ接続するボ
ンディングワイヤ２０による直列インダクタＬ４とから
構成され、出力のリード１５ｂは、枠体１４のセラミッ
クを介して接地されているステム１３との間に並列キャ
パシタＣｏｕｔが並列に接続されていることになる。The matching circuit on the output side is a series inductor L formed by a bonding wire 19 connected to the semiconductor chip 11.
3, a parallel capacitor C2 formed by a capacitive chip 12b for cutting a direct current component, and a series inductor L4 formed by a bonding wire 20 connected to the lead 15b. The output lead 15b is provided with the ceramic of the frame body 14 interposed therebetween. The parallel capacitor Cout is connected in parallel with the grounded stem 13.
【００３０】更に、リード１５ｂは、前記セラミックの
枠体１４上に端面開放の線路１６ｂが接続されている形
態となっており、オープンスタブｏｓの機能を備えてい
るために、インピーダンス変換の機能を加えている。Further, the lead 15b has a form in which a line 16b having an open end face is connected to the ceramic frame body 14 and has a function of open stub os, and therefore has a function of impedance conversion. In addition.
【００３１】ここで、例えば、出力９０Ｗ級に相当する
総ゲート幅１５ｃｍのＦＥＴの入力インピーダンス（約
０．１５Ω）を、図６に示す入力側内部整合回路と、パ
ッケージのリードが有するインピーダンス変換機能によ
り、２ＧＨｚで４Ωに変換する場合について説明する。Here, for example, the input impedance (about 0.15Ω) of the FET having a total gate width of 15 cm corresponding to the output 90 W class is converted into the impedance conversion function of the input side internal matching circuit shown in FIG. 6 and the package lead. A case of converting to 4Ω at 2 GHz will be described.
【００３２】図７は、インピーダンス変換の経路を示す
ための、回路の切断面Z1,Z2,Z3,Z4,Z5,Z6を示してお
り、切断面Z1はデバイスのインピーダンス、切断面Z2は
切断面Z1を直列インダクタＬ２で変換後のインピーダン
ス、切断面Z3は切断面Z2を並列キャパシタＣ１で変換後
のインピーダンス、切断面Z4は切断面Z3を直列インダク
タＬ１で変換後のインピーダンス、切断面Z5はリード１
５ａのオープンスタブｏｓで変換後のインピーダンス、
切断面Z6はリード１５ａの引き出し部分に対応する伝送
線路で変換後のインピーダンスを示す。FIG. 7 shows cut surfaces Z1, Z2, Z3, Z4, Z5, Z6 of the circuit for showing the path of impedance conversion, where cut surface Z1 is the impedance of the device and cut surface Z2 is the cut surface. Z1 is the impedance after conversion by the series inductor L2, cut plane Z3 is the impedance after cut plane Z2 is converted by the parallel capacitor C1, cut plane Z4 is the impedance after cut plane Z3 is converted by the series inductor L1, and cut plane Z5 is the lead. 1
Impedance after conversion with open stub os of 5a,
The cut surface Z6 is the transmission line corresponding to the lead portion of the lead 15a and shows the impedance after conversion.
【００３３】図８は、インピーダンスの変換経路の概略
を、図７に示す各回路切断面Z1,Z2,Z3,Z4,Z5,Z6でのイ
ンピーダンスを４Ωに規格化したスミスチャート上に示
したものである。このとき内部整合回路のボンディング
ワイヤ１８（Ｌ２）は０．０３ｎＨ、容量チップ１２ａ
のキャパシタＣ１は１８０ｐＦ、ボンディングワイヤ１
７（Ｌ２）は０．１４ｎＨとなり、更に、オープンスタ
ブｏｓは、誘電率２０のセラミック部材上に、長さ４．
０ｍｍ、幅２．８ｍｍとなっている。FIG. 8 shows an outline of the impedance conversion path on a Smith chart in which the impedance at each circuit section Z1, Z2, Z3, Z4, Z5, Z6 shown in FIG. 7 is standardized to 4Ω. Is. At this time, the bonding wire 18 (L2) of the internal matching circuit is 0.03 nH, and the capacitance chip 12a.
Capacitor C1 is 180pF, bonding wire 1
7 (L2) is 0.14 nH, and the open stub os has a length of 4.
The width is 0 mm and the width is 2.8 mm.
【００３４】ここで、リード１５ａではセラミックを介
してステム１３との間に、等価的には並列キャパシタＣ
ｉｎとオープンスタブｏｓにより、インピーダンス変換
が行われているので、内部整合回路に要求されるインピ
ーダンス変換比を小さくすることができる。つまり、リ
ード１５ａは、インピーダンス変換の機能が強化されて
いることになり、これはリード１５ｂについても同様で
ある。Here, the lead 15a is equivalent to the parallel capacitor C between the lead 15a and the stem 13 via the ceramic.
Since impedance conversion is performed by in and open stub os, the impedance conversion ratio required for the internal matching circuit can be reduced. In other words, the lead 15a has an enhanced impedance conversion function, and the same applies to the lead 15b.
【００３５】こうして、リード１５ａ，１５ｂに付随す
るキャパシタＣｉｎ，Ｃｏｕｔによるインピーダンス変
換が、オープンスタブｏｓにより補償されているため、
リード１５ａ，１５ｂの設計の自由度が増している。特
に、インピーダンス変換機能が強化されているリード１
５ａ，１５ｂにおいて、変換されるインピーダンスが低
い場合には、リード１５ａ，１５ｂのサイズを大きくし
なくても、インピーダンスの変換が可能となる。In this way, the impedance conversion by the capacitors Cin and Cout attached to the leads 15a and 15b is compensated by the open stub os.
The degree of freedom in designing the leads 15a and 15b is increased. In particular, the lead 1 with enhanced impedance conversion function
When the impedance to be converted is low in 5a and 15b, the impedance can be converted without increasing the size of the leads 15a and 15b.
【００３６】（実施の形態２）図９は、本発明の他の実
施の形態である半導体装置を示す平面図である。本実施
の形態の半導体装置は、ステム１３、枠体１４、樹脂層
２１及びリッド２２によって構成される空間に、半導体
チップ１１、容量チップ１２ａ，１２ｂ、リード１５
ａ，１５ｂの内端及びボンディングワイヤ１７，１８，
１９，２０が夫々２組気密封止されている。(Second Embodiment) FIG. 9 is a plan view showing a semiconductor device according to another embodiment of the present invention. In the semiconductor device of this embodiment, the semiconductor chip 11, the capacitance chips 12a and 12b, and the leads 15 are provided in the space formed by the stem 13, the frame body 14, the resin layer 21, and the lid 22.
a, 15b inner ends and bonding wires 17, 18,
Two sets of 19 and 20 are hermetically sealed.
【００３７】即ち、前述した実施の形態の半導体装置と
同様の構成に接続された各素子を２組有する構成とされ
ており、夫々の素子は、入力と出力の方向が一致する線
対称の位置に平行に実装される形態となっている。That is, the semiconductor device of the above-described embodiment has two sets of elements connected to each other in the same configuration, and each of the elements has a line-symmetrical position in which the input and output directions match. It is mounted in parallel with.
【００３８】夫々のリード１５ａ，１５ｂについても、
前述した実施の形態と同様に、端面開放の線路が接続さ
れた形態となっている。そして、入力側に平行に配置さ
れたリード１５ａ，１５ａと出力側に平行に配置された
リード１５ｂ，１５ｂが、それに接続されている線路１
６ａ，１６ａの開放されている端面が互いに対向した状
態に配置されており、その端面はセラミックの枠体１４
上で隣接し、リード１５ａ，１５ａ或いはリード１５
ｂ，１５ｂが備える２つの線路１６ａ，１６ａ或いは線
路１６ｂ，１６ｂの端面が互いに隣接し、キャパシタＣ
Ｌにより結合された構成となっているため、キャパシタ
ＣＬによりリード１５ａ，１５ｂに接続されている線路
１６ａ，１６ｂが接地されていることになる。Regarding the leads 15a and 15b,
Similar to the above-described embodiment, the open end face line is connected. The leads 15a, 15a arranged parallel to the input side and the leads 15b, 15b arranged parallel to the output side are connected to the line 1
The open end surfaces of 6a and 16a are arranged so as to face each other, and the end surfaces thereof are made of ceramic frame 14
Adjacent to each other, the leads 15a, 15a or the lead 15
The end faces of the two lines 16a, 16a or the lines 16b, 16b of the capacitors b, 15b are adjacent to each other, and the capacitor C
Since the structure is coupled by L, the lines 16a, 16b connected to the leads 15a, 15b by the capacitor CL are grounded.
【００３９】図１０は図９に示す半導体装置の２つの入
力側リード１５ａに、互いに位相反転された性質の信号
を入力するプッシュ・プル動作の状態を示す等価回路図
である。本実施例の形態のリード１５ａ，１５ｂについ
ても、前述した実施形態と同様の効果を奏し、インピー
ダンス変換が行われているので、内部整合回路に要求さ
れるインピーダンス変換比を小さくすることができる。FIG. 10 is an equivalent circuit diagram showing a push-pull operation state in which signals having a phase-inverted nature are input to the two input-side leads 15a of the semiconductor device shown in FIG. The leads 15a and 15b of this embodiment also have the same effects as those of the above-described embodiment and undergo impedance conversion, so that the impedance conversion ratio required for the internal matching circuit can be reduced.
【００４０】更に、プッシュ・プル動作では、キャパシ
タＣＬによりリード１５ａ，１５ｂに接続されている線
路１６ａ，１６ｂが接地されていることになる。そのた
め、リード１５ａ，１５ｂに接続された線路１６ａ，１
６ｂを、ショートスタブとして活用することができる。
即ち、線路１６ａ，１６ｂのサイズを変更することによ
り、ドレイン、ゲート端でのインピーダンスを、偶数次
高調波に対してはショート、奇数次高調波に対してはオ
ープンにすることができる。また、本構成においては、
ショートスタブとしての機能をリード１５ａ，１５ｂに
もたせるにあたり、それぞれのリード１５ａ，１５ｂに
新たな容量を付加する必要がない。このように、上記２
つの実施形態では、内部整合回路のインピーダンス変換
比が、オープンスタブ或いはショートスタブのサイズに
より調整可能となり、パッケージ全体としての周波数帯
域の向上、若しくはインピーダンス変換比増加が可能と
なる。また、インピーダンス変換の設計の自由度が増し
ているため、パッケージの小型化にも有効に働く。更
に、オープンスタブ或いはショートスタブはセラミック
等の低損失な部材上に形成されているため、損失の点で
も有利である。Further, in the push-pull operation, the lines 16a and 16b connected to the leads 15a and 15b by the capacitor CL are grounded. Therefore, the lines 16a, 1 connected to the leads 15a, 15b
6b can be utilized as a short stub.
That is, by changing the sizes of the lines 16a and 16b, the impedances at the drain and gate ends can be made short for even harmonics and open for odd harmonics. In addition, in this configuration,
In providing the leads 15a and 15b with the function as the short stub, it is not necessary to add new capacitance to the leads 15a and 15b. Thus, the above 2
In one embodiment, the impedance conversion ratio of the internal matching circuit can be adjusted by the size of the open stub or the short stub, and the frequency band of the entire package can be improved or the impedance conversion ratio can be increased. Further, since the degree of freedom in designing impedance conversion is increased, it also works effectively for downsizing of the package. Further, since the open stub or the short stub is formed on a low loss member such as ceramic, it is advantageous in terms of loss.
【００４１】また、セラミック部材についても、その性
質、形状を変えることにより、リードによる対地容量の
値と、オープンスタブのインピーダンス、電気長が変更
できるため、実装されるデバイスのインピーダンスに応
じて、半導体装置全体として適したインピーダンス変換
となるように設計することが容易になる。これにより、
インピーダンスの変換の際に生じる特性の劣化を抑制す
ることができる。Also, regarding the ceramic member, the value of the capacitance to ground by the lead, the impedance of the open stub, and the electrical length can be changed by changing the property and shape of the ceramic member. Therefore, the semiconductor member can be changed according to the impedance of the mounted device. It becomes easy to design the impedance conversion suitable for the entire device. This allows
It is possible to suppress the deterioration of the characteristics that occurs when the impedance is converted.
【００４２】以上、本発明を、前記実施の形態に基づき
具体的に説明したが、本発明は、前記実施の形態に限定
されるものではなく、その要旨を逸脱しない範囲におい
て種々変更可能であることは勿論である。Although the present invention has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Of course.
【００４３】例えば、前述した説明ではリードにマイク
ロストリップラインのオープンスタブ或いはショートス
タブを接続した構成としたが、これに限定されるもので
なく、ストリップライン、コプレーナライン等の線路で
もよい。For example, in the above description, the lead is connected to the open stub or the short stub of the microstrip line, but the present invention is not limited to this, and may be a line such as a strip line or a coplanar line.
【００４４】[0044]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。
（１）本発明によれば、半導体装置のリードが、整合用
のオープンスタブを備えているので、効果的にインピー
ダンスの変換ができるという効果がある。
（２）本発明によれば、上記効果（１）により、半導体
装置に内蔵される内部整合回路に要求されるインピーダ
ンス変換比、周波数帯域特性が緩和できるという効果が
ある。
（３）本発明によれば、上記効果（２）により、整合回
路の設計の自由度が増すために、整合回路の低損失化が
可能になるという効果がある。
（４）本発明によれば、上記効果（１）により、リード
に接続されるオープンスタブの形状を変更することによ
り、高調波の制御も可能となり、高効率化が可能になる
という効果がある。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, the leads of the semiconductor device are provided with the open stub for matching, so that there is an effect that the impedance can be effectively converted. (2) According to the present invention, due to the effect (1), the impedance conversion ratio and the frequency band characteristic required for the internal matching circuit built in the semiconductor device can be relaxed. (3) According to the present invention, since the degree of freedom in designing the matching circuit is increased due to the effect (2), there is an effect that the loss of the matching circuit can be reduced. (4) According to the present invention, due to the above effect (1), it is possible to control harmonics by changing the shape of the open stub connected to the lead, and it is possible to achieve high efficiency. .
【図１】従来の半導体装置を示す平面図である。FIG. 1 is a plan view showing a conventional semiconductor device.
【図２】従来の半導体装置を示す平面図である。FIG. 2 is a plan view showing a conventional semiconductor device.
【図３】従来の半導体装置を示す等価回路図である。FIG. 3 is an equivalent circuit diagram showing a conventional semiconductor device.
【図４】本発明の一実施の形態である半導体装置を示す
平面図である。FIG. 4 is a plan view showing a semiconductor device according to an embodiment of the present invention.
【図５】図４中のａ‐ａ線に沿った縦断面図である。5 is a vertical cross-sectional view taken along the line aa in FIG.
【図６】図４及び図５に示す半導体装置の等価回路図で
ある。6 is an equivalent circuit diagram of the semiconductor device shown in FIGS. 4 and 5. FIG.
【図７】本発明の一実施の形態である半導体装置の整合
回路のインピーダンス変換経路を説明するための回路切
断面を示す図である。FIG. 7 is a diagram showing a circuit cross section for explaining an impedance conversion path of a matching circuit of a semiconductor device according to an embodiment of the present invention.
【図８】本発明の一実施の形態である半導体装置の整合
回路のインピーダンス変換経路を図６の回路切断面につ
いて示す図である。8 is a diagram showing an impedance conversion path of a matching circuit of the semiconductor device according to the exemplary embodiment of the present invention with respect to a circuit cut surface of FIG. 6;
【図９】本発明の他の実施の形態である半導体装置を示
す平面図である。FIG. 9 is a plan view showing a semiconductor device according to another embodiment of the present invention.
【図１０】図９に示す半導体装置の等価回路図である。FIG. 10 is an equivalent circuit diagram of the semiconductor device shown in FIG.
１…ＦＥＴ、２…パッケージ、３…メタライズパター
ン、４，９，１０，１７，１８，１９，２０…ボンディ
ングワイヤ、５，１５ａ，１５ｂ…リード、６，１２
ａ，１２ｂ…容量チップ、７，１３…ステム、８，１４
…枠体、１１…半導体チップ、１６ａ，１６ｂ…線路、
２１…樹脂層、２２…リッド。1 ... FET, 2 ... Package, 3 ... Metallized pattern, 4, 9, 10, 17, 18, 19, 20, ... Bonding wire, 5, 15a, 15b ... Lead, 6, 12
a, 12b ... Capacitance chip, 7, 13 ... Stem, 8, 14
... frame body, 11 ... semiconductor chip, 16a, 16b ... line,
21 ... Resin layer, 22 ... Lid.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 吉田 功 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体グループ内 (72)発明者 伊藤 護 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体グループ内 Ｆターム(参考） 5J067 AA04 AA41 CA75 FA16 HA09 KA29 KA68 KS11 LS11 QS03 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Isao Yoshida 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock Ceremony Company within Hitachi Semiconductor Group (72) Inventor Mamoru Ito 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock Ceremony Company within Hitachi Semiconductor Group F term (reference) 5J067 AA04 AA41 CA75 FA16 HA09 KA29 KA68 KS11 LS11 QS03
Claims (5)
用或いは出力用のリードが、前記半導体チップを収容す
る絶縁材の枠体に固定されている半導体装置において、 前記入力用或いは出力用リードの少なくとも何れかが、
前記枠体に固定される部位に、前記枠体により支持され
る端面開放の線路と接続され、前記リードがオープンス
タブを備える構成となる整合回路を有することを特徴と
する半導体装置。1. A semiconductor device in which an input or output lead electrically connected to a semiconductor chip is fixed to a frame of an insulating material that accommodates the semiconductor chip, wherein the input or output lead is provided. At least one of
A semiconductor device having a matching circuit connected to a line having an open end face supported by the frame and having a configuration in which the lead includes an open stub, at a portion fixed to the frame.
は出力用リードの少なくとも何れかが、複数設けられて
おり、前記リードの内の隣接するリードを通過する信号
が互いに１８０°位相反転の状態となるように構成され
ており、前記複数のリードのオープンスタブの端面を近
接させて配置し、ショートスタブとして機能させること
を特徴とする請求項１に記載の半導体装置。2. A plurality of at least one of an input lead and an output lead provided with the open stub are provided, and signals passing through adjacent ones of the leads are 180 ° phase-inverted with each other. The semiconductor device according to claim 1, wherein the open stubs of the plurality of leads are arranged close to each other to function as a short stub.
Ｔを有することを特徴とする請求項１又は請求項２に記
載の半導体装置。3. The high-frequency and high-power FE as the semiconductor chip
The semiconductor device according to claim 1 or 2, further comprising T.
テムに固定されていることを特徴とする請求項１乃至請
求項３の何れか一項に記載の半導体装置。4. The semiconductor device according to claim 1, wherein the semiconductor chip and the frame body are fixed to a stem made of a conductive material.
とを特徴とする請求項１乃至請求項４の何れか一項に記
載の半導体装置。5. The semiconductor device according to claim 1, wherein the insulating material of the frame is ceramic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001307358A JP2003115732A (en) | 2001-10-03 | 2001-10-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001307358A JP2003115732A (en) | 2001-10-03 | 2001-10-03 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003115732A true JP2003115732A (en) | 2003-04-18 |
Family
ID=19126832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001307358A Pending JP2003115732A (en) | 2001-10-03 | 2001-10-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003115732A (en) |
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