JP2839023B2 - Semiconductor package and amplifier using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and an amplifier using the same, and more particularly, to a high-frequency semiconductor package containing a semiconductor chip capable of handling a high-frequency signal and an amplifier using the same.

[0002]

2. Description of the Related Art Recently, GaAs FETs are mostly used in microwave high-power amplifiers. High output Ga
AsFETs are used in various types of wireless devices, whether fixed or mobile, including repeaters for communication satellites. In the consumer field, GaAs FETs have higher output power than Si bipolar transistors.
Attention has been paid to the high efficiency of ET, which has recently been used in large quantities in the transmission stage of mobile phones. NEC Technical Report Vol. 44 (199
According to Nov. 2001), a high-power amplifier used in a transmission stage of a mobile phone is a GaAs FET one-stage or two-stage cascade connection structure, and a F-film with a chip component is mounted on a thick film substrate.
It has a module structure equipped with ET. A GaAs FET chip constituting a two-stage cascade connection is usually housed in a high-frequency package and sealed in order to ensure reliability and facilitate mounting. Therefore, in the configuration of the two-stage cascade connection, two FET packages are individually mounted on one module (National Technical Report).
port Vol. 36 No. 4 Aug. 1990
p. Technical Information Panasonic News No. 34-38. 75 p. 14-16).

[0003] In the specification of the present application, a "package" is a device on which at least one type of element containing no circuit is mounted, and a "module" is a hybrid integrated circuit on which a package is mounted. Considering the ease of cascade connection, a high-frequency package having a structure as shown in FIG. 6 has been devised and used. Hereinafter, the structure of a high-frequency package used in the related art will be described with reference to FIG.

In the prior art, a GaAs FET chip 2 is mounted on a copper base 1 for radiating heat, and a ceramic plate (Al 2 O 3) 4 having a hollow central portion is installed.
Input / output leads 5, 8 are soldered on the ceramic plate 4. After the wire bonding of the FET2, the airtight sealing was performed using an epoxy resin.

[0005]

In a conventional semiconductor package, when a circuit such as an amplifier having two or more connected stages is modularized, a plurality of semiconductor packages are mounted in one module structure. It was difficult to reduce the size.

Furthermore, when a plurality of individually packaged products are used, manufacturing costs are increased, and it is difficult to reduce product costs.

Further, when semiconductor devices having different device structures and different transistor characteristics are housed in the same package, they tend to interfere with each other, causing problems such as oscillation, and cannot be packaged together. .

[0008]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor chip having an island portion having first and second sides parallel to each other, and first and second terminals mounted on the island portion and arranged along the first side of the island portion A first lead extending from a center of the first side of the island portion in a direction perpendicular to the first side; and a first lead disposed on one side of the first lead and spaced apart from the island portion A second lead extending along the first side of the island portion and electrically connected to the first terminal of the semiconductor chip; and a second lead disposed on the other side of the first lead. A third extending away from the island portion along the first side of the island portion and electrically connected to the second terminal of the semiconductor chip;
Wherein the first lead is disposed between the first and second leads and the second and third leads.

In the above-mentioned semiconductor device, the semiconductor chip further has third and fourth terminals arranged along the second side of the island portion, and the third and fourth terminals are arranged along the second side of the island portion. A fourth lead extending from a central portion in a direction perpendicular to the second side; and a fourth lead disposed on one side of the fourth lead and spaced apart from the island section on the second side of the island section. A fifth lead extending along and electrically connected to the third terminal of the semiconductor chip; and a fifth lead disposed on the other side of the fourth lead and spaced apart from the island. A sixth lead extending along a second side and electrically connected to the fourth terminal of the semiconductor chip, whereby the fourth lead is connected to the fifth and sixth terminals. It is arranged between the lead.

Further, according to the present invention, an island portion having a first side and a second side parallel to each other, and the first portion of the island portion disposed close to the first side of the island portion. First and second leads extending in opposite directions along the side, and in a direction perpendicular to the first side of the island so as to be sandwiched between the first and second leads. A third lead derived from a part of the first side of the island portion, and a third lead disposed close to the second side of the island portion along the second side of the island portion; Fourth and fifth leads extending in opposite directions, and the first and second sides of the island portion interposed between the fourth and fifth leads in a direction perpendicular to the first side of the island portion. Derived from part of the second side A semiconductor mounted on the island portion and having first, second, third and fourth terminals electrically connected to the first, second, fourth and fifth leads, respectively; A semiconductor device including the chip is obtained. In the semiconductor device, the fourth and fifth
Is bent in a direction perpendicular to the second side of the island portion and forms a first portion parallel to the second side of the island portion and a second portion parallel to the sixth lead, respectively. It is desirable to have.

A semiconductor package according to the present invention is a semiconductor package having a module structure of a circuit formed by connecting a plurality of packaged semiconductor elements, wherein a plurality of the semiconductor elements having the same device structure are mounted on the semiconductor package. A first input lead and a first output lead of one semiconductor element, a second input lead and a second output lead of the second semiconductor element, wherein the first input lead and the second output are provided. Leads are arranged on a first side surface of the semiconductor package, and the first output lead and the second input lead are arranged on a second side surface of the semiconductor package facing the first side surface. It is characterized by being.

It is desirable that the first input lead and the second output lead are installed in parallel with the first side surface.

[0013] Between the first input lead and the second output lead and between the first output lead and the second input lead,
It is also desirable to have each mounting lead connected to a metal base.

An insulator is provided on the outer periphery of a plurality of semiconductor elements on a metal base, and a first input lead, a first output lead, a second input lead, a second output lead, and an installation are provided on the insulator. A first input lead and a first output lead connected to the first semiconductor device by a bonding wire; and a second input lead and a second output lead connected to the second semiconductor by a bonding wire. It is also preferable that the caster is connected to the element and has a castellation on the inner side wall of the insulator, the castellation is metal-plated, and the installation lead and the metal base are connected by metal plating.

Further, a first insulator is provided on the outer periphery of the plurality of semiconductor elements on the metal base, a metal layer is provided on the first insulator, and a second insulator is provided on the metal layer. The first input lead, the first output lead, the second input lead, the second output lead, the first input lead and the first output lead are formed on the second insulator by bonding wires. It is also preferable that the second input lead and the second output lead are connected to the second semiconductor element by a bonding wire, and the metal layer is connected to a metal base.

An amplifier according to the present invention is an amplifier configured by cascading a plurality of packaged semiconductor elements, wherein the plurality of semiconductor elements are housed in the same semiconductor package, and the semiconductor package includes external input leads,
An external output lead, an intermediate input lead, and an intermediate output lead, wherein the external input lead is connected to a first electrode of a first semiconductor device, and the intermediate input lead is a second electrode of the first semiconductor device. The intermediate output lead is connected to the first electrode of the second semiconductor element, the external output lead is connected to the second electrode of the second semiconductor element, and the external output lead is connected to the outside of the semiconductor package. The input lead is connected to an input stage of the amplifier, the intermediate output lead and the intermediate input lead are connected via an interstage circuit, and the external output lead is connected to an output stage of the amplifier. .

Further, it is preferable that the input stage, the interstage circuit, and the output stage are provided on a module substrate, and the semiconductor package is mounted on the module substrate.

The third electrode of the first semiconductor element and the third electrode of the second semiconductor element are commonly grounded, and the first and second electrodes of the first and second semiconductor elements are located inside a semiconductor package. Are more preferably not electrically connected to each other.

[0019]

FIG. 1 shows a first embodiment of the present invention. FIG. 1A is a plan view, and FIG.
FIGS. 3A and 3B are a cross-sectional view and a side view at A ′ and BB ′, respectively, and FIG. 3C is a cross-sectional view and a side view at CC ′ and DD ′ in FIG.

In the first embodiment, GaAs is formed on a 0.4 mm thick copper or other conductor base 1 for heat dissipation.
The FET chip 2 is mounted, and a ceramic substrate (Al2 O3, etc.) 4 whose center is hollowed out is installed.
Input / output leads 5, 6, 7, 8 (made of copper or another conductor) are brazed on a ceramic substrate 4 made of 2 O3 or another material. The lead is preferably T-shaped,
The thickness is 0.1 to 0.2 mm. Tip length is 0.3
mm and leads 5 and 8 and leads 6 and 7 are 1.5
It is preferable to be apart by ~ 2.0 mm.

When two high-output GaAs FET chips 2 are housed in a high-frequency package as shown in FIG. 1 to form a two-stage cascade amplifier, the gate terminal and external input lead 5 of the first-stage GaAs FET 2 and the first-stage GaAs FET 2
Terminal and intermediate output lead 6, final GaAs F
Gate terminal of ET3, intermediate input lead 7, final stage FET3
And the external output lead 8 are connected by gold bonding wires 9, respectively. First-stage GaAs FE
At T2, the source terminal of the last-stage GaAs FET 3 is connected to the copper base 1 and grounded via the side metallized portion and the back metallized portion of each chip. There is a reason that the intermediate output lead 6 and the intermediate input lead 7 are arranged on the same side of the high frequency package and are arranged in parallel with each other. In a two-stage cascade-connected high-power amplifier module used in a transmission stage of a mobile phone, an impedance matching circuit is formed at each input and output of two GaAs FETs as shown in the equivalent circuit diagram of FIG. . In particular, a matching circuit between the drain (intermediate output) of the first-stage FET 2 and the gate (intermediate input) of the last-stage FET 3 is called an inter-stage circuit, and highly integrates and miniaturizes the entire high-output amplifier module including the inter-stage circuit. For this purpose, it is most efficient to arrange the intermediate output lead 6 and the intermediate input lead 7 on the same side as shown in FIG. Furthermore, since the package lead frame is easier to make when the leads are arranged symmetrically in the vertical and horizontal directions, and the productivity is improved, the external input lead 5 and the external output lead 8 are also placed on the same side of the high frequency package (the intermediate output lead 6, the intermediate input lead). 7), and are arranged in parallel with each other.

Next, the amplifier of the present invention will be described.
FIG. 5 is a circuit diagram showing a first embodiment of the amplifier according to the present invention.

An input terminal is connected to the resistor R1, and R1 is
The other ends of the capacitors C1 and C2 are grounded. The other end of C2 is connected to the external input leads 5, R2, and R3 of the first-stage GaAs FET 2, and R3 is R
4 and C3. R3 and C3 are grounded in parallel. The other end of R2 is connected to C7, one end of which is grounded, and R5 and VGG, one end of which is connected to contact D.

R1 to R7 are, for example, 5.1Ω, 1000
Ω, 510Ω, 150Ω, 1000Ω, 510Ω, 15
0 Ω, C1 to C14 are 6 pF, 15 pF, 1
000pF, 2pF, 8pF, 15pF, 1000p
F, 1000pF, 56pF, 1pF, 1pF, 12p
F, 4 pF, and 4 pF.

The source terminal of the first-stage GaAs FET 2 is grounded, and the intermediate output lead 6 is connected to one end of C5 through the contact A. At the contact A, the C4, one of which is grounded, and the contact B are further connected to the intermediate output lead 6. The contact B is connected to C3 and VDD1, one of which is grounded.

The other end of C5 passes through the contacts C and D and the final stage G
aAs Connected to the intermediate input lead 7 of the FET 3.
The contact C is connected to C6, one end of which is grounded.
Is connected to one end of R6, and the other end of R6 is connected to R7 and C
8 is connected to one end. The other ends of R7 and C8 are each grounded.

The source terminal of the last-stage GaAs FET 3 is grounded, and the external output lead 8 is connected through the contacts E and F to C12.
Is connected to one end. C1 with one end grounded to contact E
0 and one end of C9 are connected, and the other end of C9 is connected to the ground potential and VDD2. C11, one end of which is grounded, is connected to the contact F.

The other end of C12 passes through the contacts G and H and is connected to the output terminal. The contact G is connected to C13 having one end grounded, and the contact H is connected to C14 having one end grounded. .

At this time, the first-stage GaAs F surrounded by a broken line
The ET and the last-stage GaAs FET have the same device structure and have the same transistor characteristics. Since they have the same transistor characteristics, they can be housed in the same package without interfering with each other.
As a result, the cost is reduced, and the size of the package and the entire amplifier can be reduced.

That is, in a multi-stage amplifier, a plurality of FETs are housed in the same package, the external input lead of the package is connected to the input stage of the amplifier, and the intermediate output lead and the intermediate input lead of the package are interstage. If a circuit is connected and the external output lead of the package is connected to the output stage of the amplifier, the size can be reduced. At this time, an input stage, an interstage circuit, and an output stage are formed on a module substrate, and F
If the ET package is incorporated, further miniaturization becomes possible.

FIGS. 6A to 6C show FIGS.
FIG. 3C shows a structure after the structure of FIG. The resin 20 uses an epoxy or other thermosetting resin.

FIG. 4 shows the frequency characteristics of the isolation between the external input lead 5 and the external output lead 8 in the high-frequency package. For a high-frequency signal with a frequency of 0.5 GHz or more, the isolation becomes -33 dB or more, and it can be used with a low-output (about 0.1 W or less) amplifier, but a high-output amplifier (1. 5
W or more), the external input / output isolation is -38.
In the case of the isolation 2 larger than dB, negative feedback occurs from the output lead to the input lead, and the stability is increased, but the gain is reduced. Therefore, it cannot be said that it is very suitable for a high-output amplifier of a domestic digital cellular phone system using a frequency band around 1.5 GHz.

The reason why the isolation between the input and output leads is deteriorated is that the portion where the external input lead 5 and the external output lead 8 are arranged in parallel to each other is long, and the propagation direction is reversed in each portion. This is because the magnetic fields generated when the high-frequency signal passes through the transmission line are easily coupled to each other. If the magnetic field coupling does not occur, the isolation does not deteriorate. The magnetic field coupling is weakened by increasing the distance between the input and output leads, but it is contrary to the downsizing of the high frequency package.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 2 shows a second embodiment of the present invention.
1 is a lead frame for a plastic package showing an embodiment of the present invention. GaAs FET chip 10 in which two FETs at the first and last stages are arranged on one chip
Is mounted on the island portion 11, and a heat sink 13 made of a conductor such as copper is provided below the island portion 11 in order to improve heat radiation characteristics. Second
The feature of this embodiment is that the external input lead 5 and the external output lead 8
Are arranged so that the portions that are parallel to each other are as small as possible. That is, the external input lead 5 is arranged on one side of the outer shape of the high-frequency package so as to be parallel to the side, and the external output lead 8 is also arranged on the same side in parallel with the side. As a result, the area where the magnetic field generated from the input / output leads is coupled is minimized, and the deterioration of isolation due to the magnetic field coupling can be prevented. The width of the input / output lead is 0.2 to 0.4 mm, and is installed at a distance of 1.5 mm or more. Further, a bonding wire 9 connected to the external input lead 5 and the external output lead 8
A ground lead 12 is provided between the external input lead 5 and the external output lead 8 in order to prevent magnetic field coupling between them. The ground lead 12 is electrically connected to the island portion 11 and has two FEs of the GaAs FET chip 10.
Since the source terminal of T is connected to the island portion 11 by the metallized layers on the side and back surfaces of the chip, the ground lead 12 itself is the source terminal. The width of the grounding lead 12 is 0.2 to 0.4 mm, and is approximately 0.5
mm apart. In the lead frame of FIG.
After mounting and bonding the FET chip 10,
Finally, a plastic package is obtained by transfer molding (FIGS. 7A to 7C).

As a result of several trials, when amplifying a high frequency signal of 1.5 GHz, the isolation between input and output was reduced.
In order to secure 40 dB, it has been found that the distance 14 between the external input lead 5 and the external output lead 8 needs to be 1.5 mm and the height 15 of the heat sink needs to be 0.6 mm or less.

FIG. 4 shows the frequency characteristics of the isolation between the external input lead 5 and the external output lead 8 in the high frequency package using the second embodiment of the present invention shown in FIG. In the second embodiment, the frequency is 1.5
An isolation of about −40 dB is ensured at GHz or higher. In a high power amplifier having an output of 1.5 W or more, the isolation between the input and output leads is −38 dB.
With the above, a desired gain (20 dB or more) can be obtained. Therefore, if the second embodiment of the present invention is used, a sufficiently practical high-frequency amplifier package for a high-output amplifier can be formed.

The isolation frequency characteristic of the second embodiment shown in FIG. 2 is a result when the heat sink height 15 is 0.6 mm, but by further reducing the heat sink height 15. It has been confirmed that the isolation is further improved. The reason is that by reducing the heat sink height 15, the ground plane becomes closer,
This is because the lines of magnetic force generated from the bonding wires 9 are easily terminated at the ground plane, and magnetic field coupling is less likely to occur.

Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a structural diagram of a ceramic package showing a third embodiment of the present invention.
G in which two FETs in the first and last stages are arranged on one chip
aAs FET chip 10 is mounted, and ceramic plates (Al2 O3) 16 and 17 whose central portions are hollowed out are placed on a copper base 1 for radiating heat. I have attached. The arrangement of the external input lead 5 and the external output lead 8 is the same as that of the first embodiment of the present invention, and the external input lead 5 is installed on one side of the ceramic plate 16 so as to be parallel to the side. External output leads 8 are also arranged on the side in parallel with the side. Further, a ground lead 12 is provided between the external input lead 5 and the external output lead 8. The ground lead 12 is electrically connected to the copper base 1 via gold-plated portions on the side walls of the castellations 18 provided on the ceramic plates 16 and 17. The ceramic plate is 0.2m thick
2 of the lower layer 17 having the same thickness of 0.2 mm as the upper layer 16
The ceramic plate has an upper layer 16 and a lower layer 17
A silver / copper brazing material 19 is applied to and adhered to one surface between them, and the silver / copper brazing material 19 is electrically connected to the copper base 1 through a side gold-plated portion of the castellation 18.

FIGS. 8A to 8C show FIGS. 3A to 3C.
2 shows the structure after resin molding. As the resin 20, a thermosetting resin such as epoxy is used.

In the second embodiment, since the side wall of the castellation 18 is electrically connected to the copper base 1, it is in a ground state. Further, a silver / copper brazing material surface 19 electrically connected to the copper base 1 is also provided between the ceramic plates 16 and 17 and also serves as a grounding surface. As a result, the lines of magnetic force emitted from the bonding wire 9, the external input lead 5, and the external output lead 8 are terminated more than in the first embodiment of the present invention. Accordingly, the magnetic field coupling is more effectively prevented, so that the deterioration of the isolation of the input / output lead is suppressed as compared with the first embodiment.

FIG. 4 shows the isolation frequency characteristics between the input and output leads in the high-frequency package using the third embodiment. Isolation of -50 db is obtained at a frequency of 1.5 GHz, and the isolation is further improved as compared with the first embodiment.

FIGS. 9A and 9B are a plan view and a sectional view showing a high-output amplifier module according to the present invention. Terminals 22, 23 (VGG), 24 (VDD1), 25 (VDD2)
) And 26 are drawn out, and a heat sink 27 is formed on the back surface of the printed circuit board 28. Semiconductor package 29
Is mounted with a GaAs FET package according to the present invention.

[0043]

The first effect is that the semiconductor package and the amplifier can be reduced in size and cost.

Another advantage is that the lead arrangement can prevent deterioration of isolation between input and output due to magnetic field coupling. As a result, a decrease in the gain of the high-output amplifier can be suppressed.

The reason is that the part where the external input lead and the external output lead are parallel to each other is changed to
This is because the lead arrangement is devised. In addition, a ground plane and a ground part are provided so as to terminate the lines of magnetic force.

[Brief description of the drawings]

FIGS. 1A and 1B are structural views showing a first embodiment of the present invention, in which FIG. 1A is a plan view, FIG. 1B is a sectional view taken along line AA ′ of FIG. Figure, (c) is (a)
3A and 3B are a sectional view taken along the line CC ′ and a side view taken along the line DD ′.

FIGS. 2A and 2B are structural views showing a second embodiment of the present invention, wherein FIG. 2A is a plan view, and FIGS. 2B and 2C are model sectional views of a heat sink portion.

3A and 3B are structural views showing a third embodiment of the present invention, in which FIG. 3A is a plan view, FIG. 3B is a sectional view taken along line AA ′ of FIG. Figure, (c) is (a)
3A and 3B are a sectional view taken along the line CC ′ and a side view taken along the line DD ′.

FIG. 4 is a graph showing input / output isolation frequency characteristics in the first, second, and third embodiments of the present invention.

FIG. 5 is a circuit diagram of a high-output amplifier for a mobile phone transmission stage according to the present invention.

FIGS. 6A and 6B are diagrams showing a structure after resin molding of the package of FIG. 1, wherein FIG. 6A is a plan view and FIG.
A sectional view at -A 'and a side view at BB';
(C) is a cross-sectional view taken along CC ′ of (a) and DD ′.
FIG.

FIGS. 7A and 7B are diagrams showing a structure after resin molding of the package of FIG. 2, wherein FIG. 7A is a plan view and FIG.
A sectional view at -A 'and a side view at BB';
(C) is a cross-sectional view taken along CC ′ of (a) and DD ′.
FIG.

FIGS. 8A and 8B are views showing a structure after the package of FIG. 3 is resin-molded, wherein FIG. 8A is a plan view and FIG.
A sectional view at -A 'and a side view at BB';
(C) is a cross-sectional view taken along CC ′ of (a) and DD ′.
FIG.

9A is a plan view and FIG. 9B is a sectional view showing a high-output amplifier module according to the present invention.

FIG. 10 is a plan view showing a conventional GaAs FET package.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Copper base 2 First stage GaAs FET chip 3 Final stage GaAs FET chip 4 Ceramic plate 5 External input lead 6 Intermediate output lead 7 Intermediate input lead 8 External output lead 9 Bonding wire 10 GaAs FET chip 11 Island part 12 Ground lead 13 Heat sink 14 Distance between input and output leads 15 Heat sink height 16 Upper ceramic plate 17 Lower ceramic plate 18 Castellation 19 Silver / copper brazing material R1 to R7 Resistance C1 to C14 Capacitor A to G Contact

Claims (12)

(57) [Claims] A first side and a second side parallel to each other;
An island portion, mounted on the island portion,
A first portion arranged along the first side of the island portion;
Semiconductor chip having a first terminal and a second terminal;
Perpendicular to the first side from the center of the first side of the
A first lead extending in a predetermined direction;
The eye is arranged on one side and separated from the island portion.
The semiconductor chip extends along the first side of the land portion.
A second lead electrically connected to the first terminal of the
And the island disposed on the other side of the first lead.
Along the first side of the island portion apart from the island portion
Extending to electrically connect to the second terminal of the semiconductor chip.
A third lead connected thereto, whereby the third lead
The first lead is disposed between the second and third leads.
A semiconductor device characterized by being performed. 2. The semiconductor chip according to claim 1, wherein
Third and fourth terminals arranged along the second side
And a center of the second side of the island portion.
A fourth lead extending from the portion in a direction perpendicular to the second side.
And the air switch disposed on one side of the fourth lead.
Along the second side of the island portion away from the land portion.
Extending to the third terminal of the semiconductor chip.
And the other of the fourth lead
Side and the island part
Extending along the second side of the semiconductor chip,
A sixth lead electrically connected to the fourth terminal;
Further comprising: the fourth lead is connected to the fifth lead.
And a sixth lead.
2. The semiconductor device according to claim 1, wherein 3. It has first and second sides parallel to each other.
The island portion and the first side of the island portion
It is arranged in a straight line close to the
A first and a second side extending in opposite directions along the first side;
Between the first and second leads and the first and second leads
The first side of the island portion so as to sandwich
From a part of the first side of the island portion in a straight direction
A third lead that is derived and the third lead of the island portion.
The island is arranged in a straight line adjacent to side 2
Extending in opposite directions along the second side of the portion
The fourth and fifth leads and the fourth and fifth leads
The first portion of the island portion is sandwiched between
Of the second side of the island portion in a direction perpendicular to the side of
A sixth lead derived from a part thereof and the island portion
Mounted on the first , second , fourth and fifth leads
First , second , third and fourth respectively electrically connected
A semiconductor chip having terminals of
Semiconductor device . 4. The apparatus according to claim 1, wherein the fourth and fifth leads are connected to the eye.
Bent in the direction perpendicular to the second side of the land,
A first portion of the land portion parallel to the second side and a front portion;
The second lead has a second portion parallel to the sixth lead.
4. The semiconductor device according to claim 3, wherein: 5. A plurality of packaged semiconductor elements are connected.
Package with module structure
The semiconductor package has a device structure.
A plurality of the same semiconductor elements are mounted, and the semiconductor device includes a first input lead and a first output lead of a first semiconductor element, a second input lead and a second output lead of a second semiconductor element,
The first input lead and the second output lead are arranged on a first side surface of the semiconductor package, and the first input lead and the second output lead
Wherein the output lead and the second input lead are disposed on a second side surface of the semiconductor package opposite to the first side surface. 6. The semiconductor package according to claim 5, wherein said first input lead and said second output lead are installed in parallel with said first side surface. 7. A ground lead is provided between the first input lead and the second output lead and between the first output lead and the second input lead. The semiconductor package according to claim 5. 8. A semiconductor device comprising: an insulator on a metal base at an outer peripheral portion of the plurality of semiconductor elements; and a first input lead, a first output lead, and a second input lead on the insulator. The second input lead and the installation lead, wherein the first input lead and the first output lead are connected to the first semiconductor element by a bonding wire; A second output lead is connected to the second semiconductor element by a bonding wire, has a castellation on an inner side wall of the insulator, and the castellation is metal-plated, and the mounting lead and the metal 6. The semiconductor package according to claim 5, wherein said base is connected to said base by said metal plating. 9. A semiconductor device comprising: a first insulator on an outer periphery of the plurality of semiconductor elements on the metal base; a metal layer on the first insulator; and a second insulator on the metal layer. Having an insulator,
The first input lead on the second insulator, the first input lead;
The output lead, the second input lead, the second output lead, the first input lead and the first output lead are connected to the first semiconductor element by a bonding wire; 6. The semiconductor package according to claim 5 , wherein the input lead and the second output lead are connected to the second semiconductor element by a bonding wire, and the metal layer is connected to the metal base. 10. A plurality of packaged semiconductor devices.
In the amplifier configured by cascade connection,
Are housed in the same semiconductor package, the semiconductor package has an external input lead, an external output lead, an intermediate input lead, and an intermediate output lead, and the external input lead is a first electrode of the first semiconductor element. Are connected, and the intermediate input lead is connected to the second of the first semiconductor element.
The intermediate output lead is connected to the first electrode of the second semiconductor element, the external output lead is connected to the second electrode of the second semiconductor element, and the external output lead is connected to the outside of the semiconductor package. The external input lead is connected to an input stage of an amplifier, the intermediate output lead and the intermediate input lead are connected via an interstage circuit, and the external output lead is connected to an output stage of the amplifier. And amplifier. 11. The amplifier according to claim 10, wherein the input stage, the interstage circuit, and the output stage are provided on a module substrate, and the semiconductor package is mounted on the module substrate. 12. A third electrode of the first semiconductor element and a third electrode of the second semiconductor element are commonly grounded,
The amplifier according to claim 10, wherein the first and second electrodes of the first and second semiconductor elements are not electrically connected in the semiconductor package, respectively.