JP2549574B2 - Monolithic integrated circuit - Google Patents
Monolithic integrated circuitInfo
- Publication number
- JP2549574B2 JP2549574B2 JP2136858A JP13685890A JP2549574B2 JP 2549574 B2 JP2549574 B2 JP 2549574B2 JP 2136858 A JP2136858 A JP 2136858A JP 13685890 A JP13685890 A JP 13685890A JP 2549574 B2 JP2549574 B2 JP 2549574B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- integrated circuit
- monolithic integrated
- semi
- passive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Waveguides (AREA)
- Microwave Amplifiers (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、衛星通信，移動体通信，レーダ等におい
て、増幅器，移相器，スイッチ，ミクサ，てい倍器など
に使用するモノリシック集積回路に関するものである。TECHNICAL FIELD The present invention relates to a monolithic integrated circuit used for an amplifier, a phase shifter, a switch, a mixer, a multiplier, etc. in satellite communication, mobile communication, radar and the like. It is a thing.
〔従来の技術〕 第２図は例えば高木直他、帰還抵抗内蔵分割形FETを
用いたＬ帯広地帯高出力モノリシック増幅器′電子情報
通信学会春季全国大会,C−724,P2−533,1989に示された
従来のモノリシック集積回路を示す等価回路図、第３図
はモノリシックマイクロ波集積回路の具体的構成を示す
構成図であり、図において、16は信号の入力端子、17は
信号の出力端子、18は第１のゲートバイアス印加端子、
19は第２のゲートバイアス印加端子、20は第３のゲート
バイアス印加端子、21はドレインバイアス印加端子、22
は１段目半導体素子、23は２段目半導体素子、24は３段
目半導体素子、25は第１のインダクタ、26は第２のイン
ダクタ、27は第３のインダクタ、28はキャパシタであ
り、これらは半導体プロセス技術を用いて、半絶縁体基
板29上に形成される。また、各半導体素子22〜24は能動
回路素子を構成し、各インダクタ25〜27やキャパシタ28
などは受動回路素子を構成している。[Prior Art] FIG. 2 is shown in, for example, Naoki Takagi et al., L-band wide-area high-output monolithic amplifier using split FET with built-in feedback resistor, IEICE Spring National Convention, C-724, P2-533, 1989. FIG. 3 is an equivalent circuit diagram showing a conventional monolithic integrated circuit, and FIG. 3 is a configuration diagram showing a specific configuration of the monolithic microwave integrated circuit. In the figure, 16 is a signal input terminal, 17 is a signal output terminal, 18 is the first gate bias application terminal,
Reference numeral 19 is a second gate bias application terminal, 20 is a third gate bias application terminal, 21 is a drain bias application terminal, 22
Is a first stage semiconductor element, 23 is a second stage semiconductor element, 24 is a third stage semiconductor element, 25 is a first inductor, 26 is a second inductor, 27 is a third inductor, 28 is a capacitor, These are formed on the semi-insulating substrate 29 by using semiconductor process technology. In addition, each semiconductor element 22-24 constitutes an active circuit element, and each inductor 25-27 and capacitor 28
Etc. constitute a passive circuit element.
次に動作について説明する。 Next, the operation will be described.
第１のゲートバイアス印加端子18,第２のゲートバイ
アス印加端子19,第３のゲートバイアス印加端子20およ
びドレインバイアス印加端子21には、１段目半導体素子
22,2段目半導体素子23および３段目半導体素子24を動作
させるための直流電圧が印加される。このとき、第１の
インダクタ25,第２のインダクタ26,第３のインダクタ27
およびキャパシタ28は整合回路素子としての役割ととも
に、信号が各バイアス印加端子18〜21にもれ込むことを
防止する。また、入力端子16から入力した信号は、１段
目半導体素子22,2段目半導体素子23,3段目半導体素子24
で増幅され、出力端子17から出力される。The first gate bias applying terminal 18, the second gate bias applying terminal 19, the third gate bias applying terminal 20 and the drain bias applying terminal 21 are the first stage semiconductor device.
A DC voltage for operating the second, second, and third stage semiconductor elements 23, 24 is applied. At this time, the first inductor 25, the second inductor 26, the third inductor 27
The capacitor 28 also functions as a matching circuit element and prevents signals from leaking into the bias applying terminals 18 to 21. In addition, the signals input from the input terminal 16 are the first stage semiconductor element 22, the second stage semiconductor element 23, and the third stage semiconductor element 24.
Amplified by and output from the output terminal 17.
従来のモノリシック集積回路は以上のように構成され
ているので、各半導体素子22〜24や各インダクタ25〜2
7,キャパシタ28などの受動回路素子の数が増大すると、
半絶縁体基板29が大型化し、歩留りが悪くなるほか、コ
ストが高くなり、また、半導体基板29が割れたり、反っ
たりするなどの課題があった。Since the conventional monolithic integrated circuit is configured as described above, each semiconductor element 22-24 and each inductor 25-2
7, as the number of passive circuit elements such as capacitors 28 increases,
There are problems that the semi-insulating substrate 29 is increased in size, the yield is deteriorated, the cost is increased, and the semiconductor substrate 29 is cracked or warped.
この発明は上記のような課題を解消するためになされ
たもので、歩留りを高く維持し、コストを安くすること
ができるとともに、半導体基板の割れおよび反り等を防
止できるモノリシック集積回路を得ることを目的とす
る。The present invention has been made to solve the above problems, and to obtain a monolithic integrated circuit capable of maintaining a high yield, reducing the cost, and preventing the semiconductor substrate from cracking and warping. To aim.
この発明に係るモノシリック集積回路は、能動素子お
よびその能動素子に対する接続線路と外部との電気接続
を行う接続部からなる第１の基板と、受動素子およびそ
の受動素子と上記第１の基板の接続部との電気接続を行
う接続部からなる第２の基板と、上記第１の基板の接続
部と上記第２の基板の接続部同士を接続する接続手段と
を備え、上記第１の基板と上記第２の基板は共に上向き
にしたものである。A monolithic integrated circuit according to the present invention includes a first substrate including an active element and a connection line for electrically connecting the active element and a connection line to the active element, a passive element and a connection between the passive element and the first substrate. A second substrate including a connecting portion for electrically connecting the connecting portion and a connecting portion for connecting the connecting portion of the first substrate and the connecting portion of the second substrate to each other; The second substrates are both facing upward.
［作用］ この発明におけるモノシリック集積回路は、第１の基
板と第２の基板とに分割したことにより、基板を小型化
し、その割れや反りを防止して歩留を向上する。また、
第２の基板は受動素子のみを有することから、半導体プ
ロセスに要するマスクの枚数低減による大幅な歩留向上
を実現する。これにより、第１の基板と第２の基板で構
成されるモノシリックマイクロ波集積回路の歩留を向上
し、コストを大幅に低減可能にする。[Operation] Since the monolithic integrated circuit according to the present invention is divided into the first substrate and the second substrate, the substrate is miniaturized, and cracks and warps thereof are prevented to improve the yield. Also,
Since the second substrate has only passive elements, the yield can be significantly improved by reducing the number of masks required for the semiconductor process. As a result, the yield of the monolithic microwave integrated circuit composed of the first substrate and the second substrate can be improved, and the cost can be significantly reduced.
［発明の実施例］ 以下、この発明の一実施例を図について説明する。第
１図において、１はFET,ダイオード、トランジスタ等の
能動回路素子（能動素子）22〜24と受動回路素子の一部
を有する第１の半絶縁体基板（第１の基板）、２はスパ
イラルインダクタ，ループインダクタ，多層コンデン
サ，インタディジタルキャパシタ，折れ曲がり線路，抵
抗等の受動回路素子（受動素子）25〜28のみを有する第
２の半導体基板（第２の基板）、３〜６はそれぞれ能動
回路素子22〜24に接続された第１のボンディングパッド
（接続部）、７〜10はそれぞれ受動回路素子25〜28に接
続された第２のボンディングパッド（接続部）、11,12,
13,14はそれぞれ対応する第1,第２のボンディングパッ
ドどうしを接続する金ワイヤ，金リボン等の接続手段、
15はソース抵抗である。また、第１のボンディングパッ
ド３〜６は第１の半絶縁体基板１に形成され、第２のボ
ンディングパッド７〜10は第２の半絶縁体基板２に形成
される。なお、ソース抵抗15は第２の半絶縁体基板２上
にユピ抵抗あるいはイオン注入抵抗などとして生成され
る。[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a first semi-insulating substrate (first substrate) 2 having active circuit elements (active elements) 22 to 24 such as FETs, diodes, and transistors and a part of passive circuit elements, and 2 is a spiral. Second semiconductor substrate (second substrate) 3 to 6 having only passive circuit elements (passive elements) 25 to 28, such as inductors, loop inductors, multilayer capacitors, interdigital capacitors, bent lines, and resistors, are active circuits. First bonding pads (connecting portions) connected to the elements 22 to 24, 7 to 10 are second bonding pads (connecting portions) connected to the passive circuit elements 25 to 28, 11, 12,
13, 14 are connecting means such as gold wires or gold ribbons for connecting the corresponding first and second bonding pads,
15 is a source resistance. Further, the first bonding pads 3 to 6 are formed on the first semi-insulating substrate 1, and the second bonding pads 7 to 10 are formed on the second semi-insulating substrate 2. Note that the source resistance 15 is generated on the second semi-insulating substrate 2 as an Upi resistance or an ion implantation resistance.
次に動作について説明する。 Next, the operation will be described.
この発明のマイクロ波集積回路は、上記のような２分
割構造をなすが、基本的に第２図に示すものと同一の等
価回路を実現しており、従来と同様の動作を実行する。
すなわち、第１のゲートバイアス印加端子18,第２のゲ
ートバイアス印加端子19,第３のゲートバイアス印加端
子20およびドレインバイアス印加端子21には、１段目半
導体素子22,2段目半導体素子23および３段目半導体素子
24を動作させるための直流電圧が印加される。このと
き、第１のインダクタ25,第２のインダクタ26,第３のイ
ンダクタ27およびキャパシタ28は整合回路素子としての
役割とともに、信号が各バイアス印加端子18〜21にもれ
込むことを防止する。また、入力端子16から入力した信
号は、１段目半導体素子22,2段目半導体素子23,3段目半
導体素子24で増幅され、出力端子17から出力される。The microwave integrated circuit of the present invention has the above-described two-division structure, but basically realizes the same equivalent circuit as that shown in FIG. 2 and executes the same operation as the conventional one.
That is, the first gate bias applying terminal 18, the second gate bias applying terminal 19, the third gate bias applying terminal 20 and the drain bias applying terminal 21 are connected to the first stage semiconductor element 22 and the second stage semiconductor element 23. And the third stage semiconductor device
A DC voltage for operating 24 is applied. At this time, the first inductor 25, the second inductor 26, the third inductor 27 and the capacitor 28 serve as matching circuit elements and prevent signals from leaking into the bias applying terminals 18 to 21. The signal input from the input terminal 16 is amplified by the first-stage semiconductor element 22, the second-stage semiconductor element 23, and the third-stage semiconductor element 24, and output from the output terminal 17.
また、第１の半絶縁体基板１側の半導体素子22〜24を
含む能動回路と第２の半絶縁体基板２側の各インダクタ
25〜27,キャパシタ28などを含む受動回路とは、上記の
ように第１のボンディングパッド３〜６と第２のボンデ
ィングパッド７〜10を介して各金ワイヤ11〜14により接
続されており、これらの両回路間の信号の流れは従来と
同様に高能率で行われる。また、特に、受動回路のみを
第２の半絶縁体基板２上に設けることによって、半導体
プロセスに要するマスクの枚数低減による大幅な歩留り
向上を期待でき、これが結果的に、モノリシック集積回
路の全体の歩留り向上に寄与することとなる。Also, an active circuit including the semiconductor elements 22 to 24 on the first semi-insulating substrate 1 side and each inductor on the second semi-insulating substrate 2 side.
As described above, the passive circuit including 25 to 27 and the capacitor 28 is connected by the gold wires 11 to 14 via the first bonding pads 3 to 6 and the second bonding pads 7 to 10, The signal flow between these two circuits is performed with high efficiency as in the conventional case. Further, in particular, by providing only the passive circuit on the second semi-insulating substrate 2, it is possible to expect a significant improvement in the yield by reducing the number of masks required for the semiconductor process, and as a result, the entire monolithic integrated circuit can be obtained. This will contribute to improving the yield.
さらに、第２の半絶縁体基板２に抵抗を設ける場合に
は、ユピ抵抗やイオン注入抵抗を用いることができるの
で、誘電体基板上に薄膜抵抗を設ける場合と比較して、
その抵抗値の選択範囲が広がる。Furthermore, when a resistance is provided on the second semi-insulating substrate 2, since an Iupi resistance or an ion implantation resistance can be used, compared with a case where a thin film resistor is provided on the dielectric substrate,
The selection range of the resistance value is expanded.
また、第１の基板と第２の基板として同じ半絶縁体基
板1,2を使用しているため、各基板のつなぎ目での不連
続の影響が少なく、つなぎ目での反射特性の劣化が少な
くなる。歩留り向上効果は使用する半導体素子の数が多
いほど、また回路が大規模化するほど顕著となる。Further, since the same semi-insulating substrates 1 and 2 are used as the first substrate and the second substrate, the influence of discontinuity at the joints of the respective substrates is small, and the deterioration of the reflection characteristics at the joints is small. . The yield improvement effect becomes more remarkable as the number of semiconductor elements used increases and as the circuit scale increases.
なお、上記実施例では半導体素子22〜24を３つ含む場
合について示したが、その個数は何個でもよい。In the above embodiment, the case where three semiconductor elements 22 to 24 are included is shown, but the number may be any number.
また、上記実施例では入力端子16および出力端子17を
第１の半絶縁体基板１上に設けたものを示したが、両者
を第２の半絶縁体基板２上に設けてもよく、上記実施例
と同様の効果を奏する。In the above embodiment, the input terminal 16 and the output terminal 17 are provided on the first semi-insulating substrate 1, but both may be provided on the second semi-insulating substrate 2. The same effect as the embodiment is obtained.
以上のように、この発明によれば、能動素子と接続部
からなる第１の基板と、受動素子と上記第１の基板の接
続部との電気接続を行う接続部からなる第２の基板と、
上記第１の基板の接続部と上記第２の基板の接続部同士
を接続する接続手段とを備え、上記第１の基板と上記第
２の基板は共に上向きになるように構成したので、各基
板を小型化することができ、その歩留の向上並びにコス
トの低減を図れるとともに、その基板の割れや反りを未
然に防止でき、信頼性の高いモノシリック集積回路を提
供できる効果がある。As described above, according to the present invention, the first substrate including the active element and the connecting portion, and the second substrate including the connecting portion for electrically connecting the passive element and the connecting portion of the first substrate are provided. ,
Since each of the first substrate and the second substrate is configured so as to face upward, it is provided with a connecting means for connecting the connecting portions of the first substrate and the connecting portions of the second substrate. There is an effect that the substrate can be downsized, the yield thereof can be improved and the cost can be reduced, and also cracking and warpage of the substrate can be prevented in advance, and a highly reliable monolithic integrated circuit can be provided.
第１図はこの発明の一実施例によるモノリシック集積回
路を示す構成図、第２図は従来のモノリシック集積回路
の等価回路を示す回路図、第３図は従来のモノリシック
集積回路を示す構成図である。 １は第１の半絶縁体基板（第１の基板）、２は第２の半
絶縁体基板（第２の基板）、3,4,5,6は第１のボンディ
ングパッド（接続部）、7,8,9,10は第２のボンディング
パッド（接続部）、11,12,13,14は金ワイヤ（接続手
段）、22,23,24は能動回路素子（能動素子）、25,26,27
は受動回路素子（受動素子）、28は受動回路素子（受動
素子） なお、図中、同一符号は同一、または相当部分を示す。FIG. 1 is a block diagram showing a monolithic integrated circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing an equivalent circuit of a conventional monolithic integrated circuit, and FIG. 3 is a block diagram showing a conventional monolithic integrated circuit. is there. 1 is a first semi-insulating substrate (first substrate), 2 is a second semi-insulating substrate (second substrate), 3,4,5,6 are first bonding pads (connecting portions), 7,8,9,10 are second bonding pads (connection parts), 11,12,13,14 are gold wires (connection means), 22,23,24 are active circuit elements (active elements), 25,26 , 27
Is a passive circuit element (passive element), 28 is a passive circuit element (passive element) In the drawings, the same reference numerals indicate the same or corresponding portions.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/04 Ｈ０１Ｌ 27/04 Ａ 29/812 Ｈ０１Ｐ 3/08 5/08 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Internal reference number FI Technical indication H01L 27/04 H01L 27/04 A 29/812 H01P 3/08 5/08
Claims (1)
線路と外部との電気接続を行う接続部からなる第１の基
板と、受動素子およびその受動素子と上記第１の基板の
接続部との電気接続を行う接続部からなる第２の基板
と、上記第１の基板の接続部と上記第２の基板の接続部
同士を接続する接続手段とを備え、上記第１の基板と上
記第２の基板は共に上向きにしたことを特徴とするモノ
シリック集積回路。1. A first substrate comprising an active element and a connecting line for electrically connecting the active element and a connection line for the active element to the outside, and a passive element and an electrical connection between the passive element and the connecting portion of the first substrate. A second substrate including a connecting portion for making a connection; and a connecting means for connecting the connecting portion of the first substrate and the connecting portion of the second substrate to each other, the first substrate and the second substrate Monolithic integrated circuit characterized in that both substrates are facing up.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2136858A JP2549574B2 (en) | 1990-05-25 | 1990-05-25 | Monolithic integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2136858A JP2549574B2 (en) | 1990-05-25 | 1990-05-25 | Monolithic integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0430457A JPH0430457A (en) | 1992-02-03 |
| JP2549574B2 true JP2549574B2 (en) | 1996-10-30 |
Family
ID=15185160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2136858A Expired - Fee Related JP2549574B2 (en) | 1990-05-25 | 1990-05-25 | Monolithic integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2549574B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011019047A (en) * | 2009-07-08 | 2011-01-27 | Mitsubishi Electric Corp | Semiconductor device |
| JP6114972B2 (en) * | 2013-07-17 | 2017-04-19 | 住友電工デバイス・イノベーション株式会社 | Amplifier circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01228202A (en) * | 1988-03-08 | 1989-09-12 | Matsushita Electron Corp | Monolithic microwave integrated circuit |
| JPH01293525A (en) * | 1988-05-20 | 1989-11-27 | Matsushita Electric Ind Co Ltd | Semiconductor device |
-
1990
- 1990-05-25 JP JP2136858A patent/JP2549574B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0430457A (en) | 1992-02-03 |
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