JPH02119174A - Integrated high frequency amplifier - Google Patents
Integrated high frequency amplifierInfo
- Publication number
- JPH02119174A JPH02119174A JP63270659A JP27065988A JPH02119174A JP H02119174 A JPH02119174 A JP H02119174A JP 63270659 A JP63270659 A JP 63270659A JP 27065988 A JP27065988 A JP 27065988A JP H02119174 A JPH02119174 A JP H02119174A
- Authority
- JP
- Japan
- Prior art keywords
- field effect
- capacitor
- effect transistor
- integrated
- frequency amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 47
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 230000005669 field effect Effects 0.000 claims description 30
- 230000003321 amplification Effects 0.000 claims description 2
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims 4
- 230000005540 biological transmission Effects 0.000 abstract description 14
- 230000000694 effects Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract 1
- 238000005549 size reduction Methods 0.000 abstract 1
- 230000001360 synchronised effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 241001235128 Doto Species 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Junction Field-Effect Transistors (AREA)
- Amplifiers (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
本発明は高周波電力増幅器に係り、特に高周波電力増幅
装置の小型化を行うに好適な集積化高周波増幅器に関す
る。The present invention relates to a high frequency power amplifier, and particularly to an integrated high frequency amplifier suitable for downsizing a high frequency power amplifier device.
従来、数ＧＨｚを越える周波数帯では、キャパシタ、イ
ンダクタンス、及び伝送線路などの整合回路要素が比較
的小さくなるため、高周波増幅器をこれらの整合回路要
素とともに同一半導体基板に集積化することは比較的に
容易であった。しかし数ＧＨｚ以下の周波数帯における
高周波増幅器においては、上記整合回路要素のうち、特
にインダクタンスや伝送線路が長くなるため、これらを
同一半導体基板に集積する場合は、極めて細い線路が稠
密に集積されてきた。この種の集積化高周波増幅器に関
するものとしては、例えば米国誌、マイクロウェーブ・
アンド・アールエフ誌、第２５巻、ナンバー９．１９８
６年９月号第１５７頁に記載されたものがある。Conventionally, in frequency bands exceeding several GHz, matching circuit elements such as capacitors, inductances, and transmission lines are relatively small, so it is relatively difficult to integrate a high-frequency amplifier with these matching circuit elements on the same semiconductor substrate. It was easy. However, in a high-frequency amplifier in a frequency band of several GHz or less, the inductance and transmission line among the above matching circuit elements are particularly long, so when these are integrated on the same semiconductor substrate, extremely thin lines are densely integrated. Ta. Regarding this type of integrated high-frequency amplifier, see, for example, American magazine, Microwave
&RF Magazine, Volume 25, Number 9.198
There is one described on page 157 of the September 2006 issue.
【発明が解決しようとする課題】
上記従来の集積化高周波増幅器においては、上記インダ
クタンスや伝送線路の抵抗成分が極めて大きい、従って
従来技術による集積化高周波増幅器は、上記抵抗成分が
大きな問題とならない小信号増幅の範囲に限られた。す
なわち数ＧＨｚ以下の周波数帯において、大信号増幅を
行う電力増幅器を同一半導体基板に集積しようとすると
、上記インダクタンスの抵抗成分は信号選択度Ｑを低下
させ、また伝送線路の抵抗成分は発熱を伴う等の問題が
あった。
そのため従来の技術による高周波電力増幅器においては
第２図に示すように、個別のトランジスタを使用し、ま
た整合回路要素も個別素子を使用してきた。従って集積
化された場合に比べて数倍の実装面積を必要とし、さら
に個別のトランジスタ及び整合回路要素に付随する寄生
要素のばらつきを補正する調整が必要となる等の問題が
あった。
本発明の目的は、数ＧＨｚ以下の周波数帯においても、
集積化が可能で、また調整個所の少ない、小型化された
高周波電力増幅器を提供することにある。Problems to be Solved by the Invention In the conventional integrated high frequency amplifier, the resistance components of the inductance and transmission line are extremely large. Therefore, the integrated high frequency amplifier according to the prior art is a small amplifier in which the resistance component does not pose a major problem. Limited to the scope of signal amplification. In other words, when attempting to integrate a power amplifier that amplifies large signals in a frequency band of several GHz or less on the same semiconductor substrate, the resistance component of the inductance will reduce the signal selectivity Q, and the resistance component of the transmission line will generate heat. There were other problems. Therefore, in conventional high frequency power amplifiers, individual transistors and matching circuit elements have been used, as shown in FIG. 2. Therefore, there are problems such as requiring several times the mounting area compared to an integrated case, and further requiring adjustment to correct variations in parasitic elements associated with individual transistors and matching circuit elements. The purpose of the present invention is to
It is an object of the present invention to provide a miniaturized high frequency power amplifier that can be integrated and has fewer adjustment parts.
上記目的は、必要な個数の電界効果トランジスタと、整
合用のキャパシタだけを同、−半導体基板に集積し、集
積化によって直列抵抗が大きくなるインダクタンスには
ボンディング・ワイヤを使用し、また伝送線路は本来外
部回路に存在する伝送線路を使用することによって達成
される。
（作用］
第１図は本発明の基本的考え方を、示す等価回路図を示
す。破線枠内は同一半導体基板に集積化され、る部分を
示す。ここに、１は入力端子、２は出力端子、３１及び
３２は集積化された電界効果トランジスタ、７１．７２
．７３及び７４は外部回路と接続するためのワイヤ・ボ
ンディング・パッドを示す。また、５及び６は集積化さ
れた整合用のキャパシタ対であり、ボンディング・ワイ
ヤのインダクタンス８と同調させるこ５とによって、電
界効果トランジスタ３１のドレインと電界効果トランジ
スタ３２のゲートの間の整合回路を構成するものである
。９は直流電源を供給するための伝送線路であり１通常
４分の１波長線路からなるが、これは外部回路に存在す
るものを使用する。
従来の個別回路におけるキャパシタ５相当の機能は主と
して直流遮断用であり、そのインピーダンスが十分小さ
くなるように、十分大きな容量値を使用するが、本発明
においてはその容量値を。
集積化可能なように十分小さくするものである。
従って本発明においては、キャパシタ５の機能は主とし
て整合回路用であり、有限のインピーダンスを有するも
のである。
すなわち本発明においては、第１図に示すように、キャ
パシタ対５，６及びボンディング・ワイヤのインダクタ
ンス８によって集積化された整合回路を構成するもので
ある。
上記キャパシタ対５及び６は、同時に集積化される電界
効果トランジスタの入出力インピーダンスに合わせて設
計することにより、ボンディング・ワイヤのインダクタ
ンスの微調整だけに、よって整合をとることができる。
また上記キャパシタ対５及び６は、はぼ同等の容量値を
有するので、同一半導体基板の上に重ねて形成すること
ができる。The above purpose is to integrate only the necessary number of field effect transistors and matching capacitors on the same semiconductor substrate, use bonding wires for inductances whose series resistance increases due to integration, and use transmission lines to This is achieved by using transmission lines that are originally present in the external circuit. (Function) Fig. 1 shows an equivalent circuit diagram illustrating the basic idea of the present invention.The parts within the dashed line frame are integrated on the same semiconductor substrate.Here, 1 is an input terminal, and 2 is an output terminal. Terminals 31 and 32 are integrated field effect transistors, 71.72
．． 73 and 74 indicate wire bonding pads for connection with external circuits. Reference numerals 5 and 6 denote a pair of integrated matching capacitors, and by tuning them with the inductance 8 of the bonding wire, a matching circuit is formed between the drain of the field effect transistor 31 and the gate of the field effect transistor 32. It constitutes. Reference numeral 9 denotes a transmission line for supplying DC power, and 1 usually consists of a quarter wavelength line, which is present in the external circuit. The function equivalent to the capacitor 5 in conventional individual circuits is mainly for DC interruption, and a sufficiently large capacitance value is used so that its impedance is sufficiently small, but in the present invention, the capacitance value is It is designed to be small enough to be integrated. Therefore, in the present invention, the function of the capacitor 5 is mainly for a matching circuit, and has a finite impedance. That is, in the present invention, as shown in FIG. 1, an integrated matching circuit is constructed by a pair of capacitors 5 and 6 and an inductance 8 of a bonding wire. By designing the capacitor pair 5 and 6 according to the input and output impedances of the field effect transistors that are simultaneously integrated, matching can be achieved by only finely adjusting the inductance of the bonding wire. Further, since the capacitor pair 5 and 6 have approximately the same capacitance value, they can be formed overlappingly on the same semiconductor substrate.
以下、本発明の第１の実施例を第３図（ａ）及び（ｂ）
によって説明する。第３図（、）は、本発明に基ずく半
導体チップの平面図である。第１図は第３図（ａ）の等
価回路であり、また第３図（ｂ）は第３図（ａ）におけ
るＡ−Ａ’線に沿った断面図である。
ここに、１は入力端子、２は出力端子、３１及び３２は
線状の電界効果トランジスタが多数並列に接続されて成
る、高出力の電界効果トランジスタ、５及び６はキャパ
シタ対である。７１．７２．７３及び７４は外部回路と
接続するためのボンディング・パッドである。４１及び
４２はそれぞれ。
電界効果トランジスタ３１及び３２のソース・パッドで
あり、第３図（ｂ）に示すように、該パッド直下におい
て、半導体基板を表面から裏面に貫通する導電層１２に
よって裏面と接続するものである。入力端子１はボンデ
ィング・パッド７１と接続され、７１は電界効果トラン
ジスタ３１のゲートと接続されている。７２は電界効果
トランジスタ３１のドレイン・パッドであり、キャパシ
タ５に接続され、さらに該キャパシタ５は電界効果トラ
ンジスタ３１のドレインと接続されている。
第３図（ｂ）に示すように、キャパシタ５はキャパシタ
６の上に重なるように形成され、キャパシタ対を構成す
る。キャパシタ６は半導体基板に設けられた導電層１２
を下層電極とし、１２と接続する該半導体基板は共通接
地とする。キャパシタ６の上層電極は電界効果トランジ
スタ３２のゲート及びゲート・パッド７４に接続される
ものである。
以上述べたように、本実施例は同一半導体基板に２個の
電界効果トランジスタを集積し、さらに１対のキャパシ
タを集積したものである。これにより、第１及び第２の
電界効果トランジスタの間の接続が上記キャパシタ対に
よって行われ、その同調及び整合は１本のボンディング
・ワイヤ８の長さを調整することによって実現される。
その結果、集積化によって小型化の効果が大きいものは
集積化され、集積化が困難なものは、本来外部回路に存
在するものを使用することになり、小型化が効率的に行
われ、且つ、集積化された内部回路と外部回路の同調及
び整合が統一化される効果がある。
第４図（ａ）、（ｂ）及び（ｃ）は本発明の第２の実施
例を示す。第４図（ａ）は本発明に基ずく半導体チップ
の平面図、同図（ｂ）はその等価回路図、同図（ｃ）は
同図（ａ）のＢ−Ｂ’線に沿った断面構造を示す。
本実施例においては、同一半導体基板に集積される電界
効果トランジスタを、３１．３２及び３３の３個とし、
これによって３段の集積化電力増幅器を実現するもので
ある。これに伴い、個々の電界効果トランジスタを高周
波的に接続するキャパシタ対も、５１．６１及び５２．
６２の２対が集積されている。またボンディング・パッ
ドも７１．７２．７３．７４．７５及び７６が設けられ
、個々のボンディング・パッドは高周波信号の相互干渉
による帰還を防ぐために、ゲート・パッドとドレイン・
パッドが相互に隣接しないように配置されている。ボン
ディング・パッド７６は出力電流を分散するために２個
設けたものである。８１及び８２はそれぞれ、電界効果
トランジスタ３２及び３３のゲートのボンディング・ワ
イヤであり、これによってキャパシタ対５１．６１及び
５２゜６２とそれぞれ同調回路を構成させ、これによっ
て集積化された３段電力増幅器を実現するものである。
また第４図（ｃ）に示すように、本実施例においては電
界効果トランジスタ３２のソース・パッドと上記キャパ
シタ対５１．６１が３層に重ねられ、また電界効果トラ
ンジスタ３３のソース・パッドと上記キャパシタ対５２
．６２も３層に重ねられている。また、電界効果トラン
ジスタ３１のソース・パッドの上に重ねて、ゲートに並
列なるようにキャパシタ６０を集積し、外部入力回路に
必要なキャパシタを内蔵したものである。
以上述べたように、本実施例は、上記３Ｍ構造により電
力増幅器をより高密度に集積したものであり、また素子
とパッドの位置を適正に配置することにより、安定にし
て集積化された３段電力増幅器を実現するものである。The first embodiment of the present invention will be described below as shown in FIGS. 3(a) and (b).
This is explained by FIG. 3(,) is a plan view of a semiconductor chip based on the present invention. FIG. 1 is an equivalent circuit of FIG. 3(a), and FIG. 3(b) is a sectional view taken along line AA' in FIG. 3(a). Here, 1 is an input terminal, 2 is an output terminal, 31 and 32 are high-output field effect transistors formed by connecting a large number of linear field effect transistors in parallel, and 5 and 6 are a pair of capacitors. 71, 72, 73 and 74 are bonding pads for connection with external circuits. 41 and 42 respectively. This is the source pad of the field effect transistors 31 and 32, and as shown in FIG. 3(b), it is connected to the back surface by a conductive layer 12 penetrating the semiconductor substrate from the front surface to the back surface directly below the pad. The input terminal 1 is connected to a bonding pad 71, which is connected to the gate of the field effect transistor 31. Reference numeral 72 designates a drain pad of the field effect transistor 31, which is connected to the capacitor 5, and the capacitor 5 is further connected to the drain of the field effect transistor 31. As shown in FIG. 3(b), capacitor 5 is formed to overlap capacitor 6, forming a capacitor pair. The capacitor 6 is a conductive layer 12 provided on a semiconductor substrate.
is used as a lower layer electrode, and the semiconductor substrate connected to 12 is connected to a common ground. The upper electrode of capacitor 6 is connected to the gate of field effect transistor 32 and gate pad 74. As described above, in this embodiment, two field effect transistors and a pair of capacitors are integrated on the same semiconductor substrate. Thereby, the connection between the first and second field effect transistors is made by the pair of capacitors, the tuning and matching of which is achieved by adjusting the length of one bonding wire 8. As a result, things that have a large effect on miniaturization through integration are integrated, and things that are difficult to integrate use those that originally exist in external circuits, which allows for efficient miniaturization. This has the effect of unifying the tuning and matching of the integrated internal circuit and external circuit. FIGS. 4(a), (b) and (c) show a second embodiment of the present invention. FIG. 4(a) is a plan view of a semiconductor chip based on the present invention, FIG. 4(b) is its equivalent circuit diagram, and FIG. 4(c) is a cross section taken along line BB' in FIG. 4(a). Show the structure. In this example, three field effect transistors, 31, 32 and 33, are integrated on the same semiconductor substrate.
This realizes a three-stage integrated power amplifier. Along with this, capacitor pairs 51.61 and 52. which connect individual field effect transistors at high frequency are also used.
Two pairs of 62 are integrated. Bonding pads 71, 72, 73, 74, 75 and 76 are also provided, and each bonding pad is connected to the gate pad and drain to prevent feedback due to mutual interference of high frequency signals.
The pads are arranged so that they are not adjacent to each other. Two bonding pads 76 are provided to distribute the output current. 81 and 82 are bonding wires for the gates of field effect transistors 32 and 33, respectively, which configure a tuned circuit with capacitor pairs 51.61 and 52.62, respectively, thereby forming an integrated three-stage power amplifier. This is to realize the following. Further, as shown in FIG. 4(c), in this embodiment, the source pad of the field effect transistor 32 and the capacitor pair 51, 61 are stacked in three layers, and the source pad of the field effect transistor 33 and the capacitor pair 51.61 are stacked in three layers. capacitor pair 52
．． 62 is also stacked in three layers. Further, a capacitor 60 is integrated over the source pad of the field effect transistor 31 so as to be parallel to the gate, thereby incorporating a capacitor necessary for an external input circuit. As described above, in this embodiment, the power amplifiers are integrated more densely using the 3M structure, and by appropriately arranging the positions of the elements and pads, the power amplifiers are stably integrated. This realizes a stage power amplifier.
以上述べたように、本発明は集積化によって小型化の効
果が大きいものだけを集積化するものであり、大きな電
流が流れるインダクタンスや伝送線路は、ボンディング
・ワイヤや外部回路の伝送線路を使用するものである。
これにより、電力増幅器を効率的に集積化することが可
能となり、またボンディング・ワイヤや外部伝送線路を
効果的に使用するので、全体としてみれば、個別素子を
使用した場合に比べて、数分の１以下に小型化された高
周波電力増幅器を提供することができる。
また、整合回路の調整はボンディング・ワイヤの長さだ
けであり、調整を極めて簡単化することができるので、
製造ばらつきを少なくすることができる。As described above, the present invention integrates only those elements that can be significantly reduced in size through integration, and for inductances and transmission lines through which large currents flow, bonding wires or transmission lines of external circuits are used. It is something. This allows for efficient integration of power amplifiers and makes effective use of bond wires and external transmission lines, resulting in an overall savings of several minutes compared to using discrete components. It is possible to provide a high frequency power amplifier that is downsized to 1 or less. In addition, the only adjustment of the matching circuit is the length of the bonding wire, making adjustment extremely simple.
Manufacturing variations can be reduced.
第１図は本発明の詳細な説明するための等価回路図、第
２図は従来の高周波電力増幅器の構成を示す回路図、第
３図（ａ）は本発明に基ずく第１の実施例の平面図、第
３図（ｂ）は同図（ａ）のＡ−Ａ’線に沿った断面図、
第４図（ａ）は本発明に基ずく第２の実施例の平面図、
第４図（ｂ）は同図（ａ）の等価回路図、第４図（Ｑ）
は同図（ａ）のＢ−Ｂ’線に沿った断面図を示す。
符号の説明
１・・・入力端子、２・・・出力端子。
３１．３２．３３・・・電界効果トランジスタ、４１．
４２・・・ソース・パッド、
５′・・・直流遮断キャパシタ。
６′・・・整合キャパシタ、
５．６・・・キャパシタ対、
５１．６１・・・キャパシタ対。
５２．６２・・・キャパシタ対、
７’ 、７１，７２，７３，７４，７５，７６・・・ボ
ンディング・パッド、
８．８１．８２・・・ワイ゛ヤ・インダクタンス、８＃
・・・伝送線路、９・・・伝送線路、１２・・・導電層
第１ 図
第
図
Ｓ′−−一 亘汰Ｖ巴断キイハ゛・ンタ−Ｖ會セハ９シ
ア
− ホ゛〉テ１ンフ“・バット
Ｆ′
一４云進署七
第３図（Ｊ、１
／２−−−一導電斗
第４図（−ｌ）
第４図（Ｑ）FIG. 1 is an equivalent circuit diagram for explaining the present invention in detail, FIG. 2 is a circuit diagram showing the configuration of a conventional high frequency power amplifier, and FIG. 3(a) is a first embodiment based on the present invention. 3(b) is a sectional view taken along line AA' in FIG. 3(a),
FIG. 4(a) is a plan view of a second embodiment based on the present invention;
Figure 4 (b) is an equivalent circuit diagram of Figure 4 (a), Figure 4 (Q)
shows a sectional view taken along line BB' in FIG. Explanation of symbols 1...Input terminal, 2...Output terminal. 31.32.33...Field effect transistor, 41.
42...Source pad, 5'...DC cutoff capacitor. 6'... Matching capacitor, 5.6... Capacitor pair, 51.61... Capacitor pair. 52.62... Capacitor pair, 7', 71, 72, 73, 74, 75, 76... Bonding pad, 8.81.82... Wire inductance, 8#
...Transmission line, 9...Transmission line, 12...Conductive layer 1・Bat F' 14 Yunjin Station 7th Figure 3 (J, 1/2 --- 1 Conductive Doto Figure 4 (-l) Figure 4 (Q)
Claims (1)
果トランジスタと第１及び第２のキャパシタより成り、
上記第１及び第２のキャパシタは電気的に直列に接続さ
れたキャパシタ対を成し、上記第１及び第２の電界効果
トランジスタのソースはそれぞれ共通端子に接続され、
上記第１の電界効果トランジスタのゲートは入力端子に
接続され、上記第２の電界効果トランジスタのドレイン
は出力端子に接続され、上記第１の電界効果トランジス
タのドレインは上記キャパシタ対の第１端子と接続され
、上記キャパシタ対の第２端子は共通端子と接続され、
上記キャパシタ対の中間端子は上記第２の電界効果トラ
ンジスタのゲートと接続されて成る半導体チップと該半
導体チップのボンディング・ワイヤによって成り、上記
第２の電界効果トランジスタのゲートのボンディング・
ワイヤと上記キャパシタ対とによって同調回路が構成さ
れ、該同調回路によって第１の電界効果トランジスタと
第２の電界効果トランジスタの間の整合が行われること
を特徴とする集積化高周波増幅器。 ２、特許請求範囲第１項記載の集積化高周波増幅器にお
いて、上記キャパシタ対の第１のキャパシタを、上記半
導体基板と、該半導体基板の表面に堆積された第１の絶
縁膜と、該絶縁膜の上に堆積された第１の金属膜によっ
て構成し、上記キャパシタ対の第２のキャパシタを、上
記第１の金属膜と、該第１の金属膜の上に堆積された第
２の絶縁膜と、該第２の絶縁膜の上に堆積された第２の
金属膜によって、上記第１のキャパシタの上部に重ねて
構成したことを特徴とする特許請求範囲第１項記載の集
積化高周波増幅器。 ３、特許請求範囲第１項及び第２項記載の集積化高周波
増幅器を使用した高周波増幅装置。[Claims] 1. Consisting of first and second field effect transistors and first and second capacitors formed on the same semiconductor substrate,
The first and second capacitors form a capacitor pair electrically connected in series, the sources of the first and second field effect transistors are each connected to a common terminal,
A gate of the first field effect transistor is connected to an input terminal, a drain of the second field effect transistor is connected to an output terminal, and a drain of the first field effect transistor is connected to a first terminal of the capacitor pair. connected, a second terminal of the capacitor pair is connected to a common terminal,
The intermediate terminal of the capacitor pair comprises a semiconductor chip connected to the gate of the second field effect transistor and a bonding wire of the semiconductor chip, and a bonding wire of the gate of the second field effect transistor.
An integrated high-frequency amplifier characterized in that the wire and the capacitor pair constitute a tuning circuit, and the tuning circuit performs matching between the first field effect transistor and the second field effect transistor. 2. In the integrated high-frequency amplifier according to claim 1, the first capacitor of the capacitor pair includes the semiconductor substrate, a first insulating film deposited on the surface of the semiconductor substrate, and the insulating film. A second capacitor of the capacitor pair is configured by a first metal film deposited on the first metal film and a second insulating film deposited on the first metal film. and a second metal film deposited on the second insulating film, the integrated high-frequency amplifier according to claim 1, wherein the integrated high-frequency amplifier is configured to overlap the first capacitor. . 3. A high frequency amplification device using the integrated high frequency amplifier according to claims 1 and 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63270659A JPH02119174A (en) | 1988-10-28 | 1988-10-28 | Integrated high frequency amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63270659A JPH02119174A (en) | 1988-10-28 | 1988-10-28 | Integrated high frequency amplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02119174A true JPH02119174A (en) | 1990-05-07 |
Family
ID=17489170
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63270659A Pending JPH02119174A (en) | 1988-10-28 | 1988-10-28 | Integrated high frequency amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02119174A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011119987A (en) * | 2009-12-03 | 2011-06-16 | Renesas Electronics Corp | Semiconductor integrated circuit device |
| JP2012256930A (en) * | 2012-08-22 | 2012-12-27 | Toshiba Corp | Semiconductor device |
| JP2016019068A (en) * | 2014-07-07 | 2016-02-01 | 株式会社東芝 | High frequency amplifier |
-
1988
- 1988-10-28 JP JP63270659A patent/JPH02119174A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011119987A (en) * | 2009-12-03 | 2011-06-16 | Renesas Electronics Corp | Semiconductor integrated circuit device |
| JP2012256930A (en) * | 2012-08-22 | 2012-12-27 | Toshiba Corp | Semiconductor device |
| JP2016019068A (en) * | 2014-07-07 | 2016-02-01 | 株式会社東芝 | High frequency amplifier |
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