JPH065794A - High frequency amplifier - Google Patents
High frequency amplifierInfo
- Publication number
- JPH065794A JPH065794A JP4160621A JP16062192A JPH065794A JP H065794 A JPH065794 A JP H065794A JP 4160621 A JP4160621 A JP 4160621A JP 16062192 A JP16062192 A JP 16062192A JP H065794 A JPH065794 A JP H065794A
- Authority
- JP
- Japan
- Prior art keywords
- high frequency
- gate
- capacitor
- semiconductor chip
- mosc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6611—Wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4801—Structure
- H01L2224/48011—Length
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48092—Helix
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は高周波増幅装置に係り、
特に、３００ＭＨｚ以上で動作する内部整合化された半
導体高周波増幅装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency amplifier,
In particular, it relates to an internally matched semiconductor high frequency amplifier operating at 300 MHz or higher.
【０００２】[0002]
【従来の技術】従来の内部整合された高周波増幅装置の
一例が特公昭63−66441 号公報に示されている。動作周
波数が３００ＭＨｚを越える高周波電力増幅装置では、
増幅素子として使用されるパワートランジスタの入力あ
るいは出力インピーダンスが低いためにインピーダンス
が高い外部回路とのインピーダンス整合が困難となる。
そのためパワートランジスタと外部回路との間にあって
外部から見たインピーダンスを高くするのが内部整合回
路である。2. Description of the Related Art An example of a conventional internally matched high frequency amplifier is disclosed in Japanese Examined Patent Publication No. 63-66441. In the high frequency power amplifier with operating frequency over 300MHz,
Since the input or output impedance of the power transistor used as the amplifying element is low, impedance matching with an external circuit having high impedance becomes difficult.
Therefore, an internal matching circuit is provided between the power transistor and the external circuit to increase the impedance seen from the outside.
【０００３】従来技術による内部整合化高周波増幅装置
の構成は、例えば、図５のように示すことができる。こ
こに１はゲート幅の大きいしま状のＭＯＳ電界効果トラ
ンジスタを多数並列接続して成る電力増幅用ＭＯＳ電界
効果トランジスタ装置（パワーＭＯＳＦＥＴ）である。
２はＭＯＳ構造キャパシタ装置（ＭＯＳＣ）である。パ
ワーＭＯＳＦＥＴ１のゲート電極は金属ワイヤ３によっ
てＭＯＳＣ２に接続されており、金属ワイヤのインダク
タンスとＭＯＳＣ２のキャパシタンスによって図６に示
す内部整合回路をなす。更に、パワーＭＯＳＦＥＴ１の
ドレイン電極は出力端子５２に接続され、ＭＯＳＣ２は
入力端子５１に接続されて内部整合化高周波増幅装置を
成す。The structure of an internally matched high frequency amplifier according to the prior art can be shown, for example, as shown in FIG. Reference numeral 1 denotes a power amplification MOS field effect transistor device (power MOSFET) in which a large number of striped MOS field effect transistors having a large gate width are connected in parallel.
2 is a MOS structure capacitor device (MOSC). The gate electrode of the power MOSFET 1 is connected to the MOSC2 by the metal wire 3, and the internal matching circuit shown in FIG. 6 is formed by the inductance of the metal wire and the capacitance of the MOSC2. Further, the drain electrode of the power MOSFET 1 is connected to the output terminal 52, and the MOSC 2 is connected to the input terminal 51 to form an internally matched high frequency amplifier.
【０００４】また、増幅電力を増加させるためにパワー
ＭＯＳＦＥＴを複数個並列設置した従来例を図７に示
す。図７の等価回路を図８に示す。従来技術によって内
部整合化高周波増幅器の増幅電力を増加させるには、パ
ワーＭＯＳＦＥＴの並列設置数を増加させ、更に個別に
内部整合キャパシタ２の大きさ、あるいはキャパシタン
スを変更する。以上の従来技術による内部整合化高周波
増幅装置の特徴はパワーＭＯＳＦＥＴ１とＭＯＳＣ２が
個別に製造され、配置されていることである。FIG. 7 shows a conventional example in which a plurality of power MOSFETs are installed in parallel in order to increase amplified power. The equivalent circuit of FIG. 7 is shown in FIG. In order to increase the amplification power of the internally matched high frequency amplifier according to the conventional technique, the number of power MOSFETs installed in parallel is increased and the size or capacitance of the internally matched capacitor 2 is individually changed. The feature of the internally matched high-frequency amplifier according to the above-mentioned conventional technique is that the power MOSFET 1 and the MOSC 2 are manufactured and arranged individually.
【０００５】[0005]
【発明が解決しようとする課題】内部整合回路を構成す
るＭＯＳＣ２の最適キャパシタンスはパワーMOSFET1 の
インピーダンスに応じて変化する。従来技術によればパ
ワーＭＯＳＦＥＴ１とＭＯＳＣ２が個別に製造されるた
め、パワーＭＯＳＦＥＴ１が異なるに応じてＭＯＳＣ２
を変更する必要があった。また、パワーＭＯＳＦＥＴ１
とＭＯＳＣ２の横幅はほぼ等しくする必要があるので、
ＭＯＳＣ２の平面寸法の変更も必要となり、パワーＭＯ
ＳＦＥＴの設計変更を行なう毎にＭＯＳＣの設計と製造
が必要であった。また、内部整合回路を構成する金属ワ
イヤ３の最適長さもパワーＭＯＳＦＥＴ１のインピーダ
ンスに応じて変化する。そのため、高周波増幅装置５の
製造工程で、パワーＭＯＳＦＥＴ１に対するＭＯＳＣ２
の相対位置を定めて配置し、配線する工程が必要であ
り、配置誤差が伴う問題があった。また、従来技術によ
れば金属ワイヤを配置する面積が必要であり、高周波増
幅装置５が大きくなる問題があった。The optimum capacitance of the MOSC2 forming the internal matching circuit changes according to the impedance of the power MOSFET 1. According to the conventional technique, since the power MOSFET 1 and the MOSC2 are manufactured separately, the MOSC2 is different depending on the difference of the power MOSFET1.
Had to change. Also, the power MOSFET 1
And the width of MOSC2 need to be almost equal,
It is also necessary to change the plane dimensions of MOSC2, and power MO
Every time the SFET design was changed, the MOSC had to be designed and manufactured. Further, the optimum length of the metal wire 3 forming the internal matching circuit also changes according to the impedance of the power MOSFET 1. Therefore, in the manufacturing process of the high frequency amplifier 5, the MOSC2 for the power MOSFET 1
There is a problem in that there is an error in placement because a step of deciding and laying out the relative position of and placing and wiring is required. Further, according to the conventional technique, there is a problem that the area for arranging the metal wire is required, and the high frequency amplification device 5 becomes large.
【０００６】本発明の目的は、高周波増幅装置に使用さ
れる様々な大きさ，構造のパワーＭＯＳＦＥＴに対し
て、内部整合化された高周波増幅装置を安定にかつ能率
的に構成することを可能とすることにある。An object of the present invention is to make it possible to stably and efficiently construct an internally-matched high-frequency amplifier device for power MOSFETs of various sizes and structures used in the high-frequency amplifier device. To do.
【０００７】[0007]
【課題を解決するための手段】上記目的は、パワーＭＯ
ＳＦＥＴを形成する半導体チップ毎に最適なＭＯＳＣを
集積化するとともに、相互の間隔が定められたボンディ
ングパッドを形成して相互間にワイヤボンディングを行
ない、これによって最適なインダクタ装置を実現し、も
って所要の内部整合回路を構成することによって達成さ
れる。The above-mentioned object is to provide a power MO.
The optimum MOSC is integrated for each semiconductor chip forming the SFET, and the bonding pads are formed so that the mutual spacing is defined, and the wire bonding is performed between them, thereby realizing the optimum inductor device, and thus it is required. This is achieved by configuring an internal matching circuit of
【０００８】本発明の装置の基本的構成を図１に示す。
図１の等価回路を図２に示す。ここにＭＯＳＣ２１とパ
ワーＭＯＳＦＥＴ１１とを同一半導体チップ１０に形成
している。更に、パワーＭＯＳＦＥＴ１１のゲート電極
１２あるいはドレイン電極１４とＭＯＳＣ２１とをイン
ダクタ装置４１によって接続し内部整合回路を構成して
いる。The basic construction of the device of the present invention is shown in FIG.
The equivalent circuit of FIG. 1 is shown in FIG. Here, the MOSC 21 and the power MOSFET 11 are formed on the same semiconductor chip 10. Further, the gate electrode 12 or the drain electrode 14 of the power MOSFET 11 and the MOSC 21 are connected by the inductor device 41 to form an internal matching circuit.
【０００９】更に変形例として図３、及びその等価回路
を図４に示すように、第２のＭＯＳＣ２２を同一半導体
チップ１０に形成し、パワーＭＯＳＦＥＴ１１のゲート
電極１２とＭＯＳＣ２１とをインダクタ装置４１によっ
て接続し、第２のインダクタ装置４２によってパワーＭ
ＯＳＦＥＴ１１のドレイン電極１４とＭＯＳＣ２２とを
接続してそれぞれ内部整合回路を構成することもでき
る。As a modified example, FIG. 3 and its equivalent circuit are shown in FIG. 4, a second MOSC 22 is formed on the same semiconductor chip 10, and the gate electrode 12 of the power MOSFET 11 and the MOSC 21 are connected by an inductor device 41. Then, the power M is set by the second inductor device 42.
The drain electrode 14 of the OSFET 11 and the MOSC 22 may be connected to form an internal matching circuit.
【００１０】内部整合回路のゲート端子６１あるいはＭ
ＯＳＣ２１の付属端子６３は高周波増幅装置の入力端子
と接続し、ドレイン端子６２あるいはＭＯＳＣ２２の付
属端子６４は高周波増幅装置の出力端子と接続するもの
である。Gate terminal 61 or M of the internal matching circuit
The accessory terminal 63 of the OSC 21 is connected to the input terminal of the high frequency amplifier, and the drain terminal 62 or the accessory terminal 64 of the MOSC 22 is connected to the output terminal of the high frequency amplifier.
【００１１】[0011]
【作用】ここに高周波増幅装置の動作周波数は３００Ｍ
Ｈｚを越えるので、インダクタ装置４１あるいは４２は
ボンディングワイヤによって形成することができ、半導
体チップの上に立体的に配置するので高周波増幅装置に
おける余分な面積を占有しない。また、パワーＭＯＳＦ
ＥＴ１１とＭＯＳＣ２１あるいは２２に対するボンディ
ングパッドの平面配置によってインダクタ装置４１ある
いは４２のボンディングワイヤの長さが定められるの
で、インダクタンスの均一性をよくすることができる。
ＭＯＳＣ２１及び２２はパワーＭＯＳＦＥＴ１１の薄い
ゲート酸化膜（例えば６５ｎｍ）を誘電体として形成す
ることができ、厚い酸化膜（例えば６５０ｎｍ）を使用
する個別のＭＯＳＣに比較して１０％以下の面積しか占
有しないので半導体チップ１０の面積はほとんど増加し
ない。The operating frequency of the high frequency amplifier is 300M.
Since the frequency exceeds Hz, the inductor device 41 or 42 can be formed by a bonding wire and is three-dimensionally arranged on the semiconductor chip, so that it does not occupy an extra area in the high frequency amplifying device. In addition, power MOSF
Since the length of the bonding wire of the inductor device 41 or 42 is determined by the planar arrangement of the bonding pads for the ET 11 and the MOSC 21 or 22, the uniformity of the inductance can be improved.
The MOSCs 21 and 22 can be formed by using the thin gate oxide film (for example, 65 nm) of the power MOSFET 11 as a dielectric, and occupy an area of 10% or less as compared with the individual MOSC using a thick oxide film (for example, 650 nm). Therefore, the area of the semiconductor chip 10 hardly increases.
【００１２】特に、図３及びその等価回路を図４に示す
例において、高周波増幅装置の出力端子に対してドレイ
ン端子６２を接続する場合、内部整合回路はインダクタ
装置４２とキャパシタ装置２２による直列同調型とする
ことができる。これを動作周波数の２倍の周波数に同調
させることによって、ドレイン電極１４において高調波
制御を行なうことができるので、ドレイン整合回路のイ
ンピーダンスに影響されない。In particular, in the example shown in FIG. 3 and its equivalent circuit shown in FIG. 4, when the drain terminal 62 is connected to the output terminal of the high frequency amplifier, the internal matching circuit is a series tuning by the inductor device 42 and the capacitor device 22. It can be a mold. By tuning this to a frequency twice the operating frequency, harmonic control can be performed at the drain electrode 14, so that the impedance of the drain matching circuit is not affected.
【００１３】このように、本発明によればパワーＭＯＳ
ＦＥＴと同時に最適なＭＯＳＣを提供し、また同時に最
適なインダクタ装置の安定な形成を可能とするものであ
り、内部整合された高周波増幅装置を安定にかつ能率的
に構成することができる。インダクタ装置は抵抗成分の
小さいアルミニウム等の金属ワイヤあるいは金属リボン
を使用することができ、更に、能率的に高調波制御を行
なうことができるので、小型にして電力損失の少ない高
周波増幅装置を構成することができる。As described above, according to the present invention, the power MOS
An optimum MOSC is provided at the same time as the FET, and at the same time, an optimum inductor device can be stably formed, so that the internally-matched high-frequency amplifier device can be stably and efficiently constructed. The inductor device can use a metal wire or metal ribbon of aluminum or the like having a small resistance component, and further, since harmonic control can be performed efficiently, a high-frequency amplification device having a small size and low power loss can be configured. be able to.
【００１４】[0014]
【実施例】第１の実施例を図９に示す。本実施例はパワ
ーＭＯＳＦＥＴ１１のゲートに対する内部整合化高周波
電力増幅装置を示す。ここにパワーＭＯＳＦＥＴ１１は
ＭＯＳ構造キャパシタ装置（ＭＯＳＣ）２１とともに同
一半導体チップ１０に形成し、パワーＭＯＳＦＥＴ１１
のゲート電極１２とＭＯＳＣ２１は半導体チップの上に
立体的に配置したインダクタ装置４１によって接続し、
半導体チップ１０はパッケージ５の金属接地台５３に電
気的に接着して成り、キャパシタ装置２１はパッケージ
の入力端子５１に接続し、パワーＭＯＳＦＥＴ１１のド
レイン電極１４はパッケージの出力端子５２に接続して
いる。EXAMPLE FIG. 9 shows a first example. This embodiment shows an internal matching high frequency power amplifier for the gate of the power MOSFET 11. Here, the power MOSFET 11 is formed on the same semiconductor chip 10 together with the MOS structure capacitor device (MOSC) 21.
The gate electrode 12 and the MOSC 21 are connected by an inductor device 41 three-dimensionally arranged on the semiconductor chip,
The semiconductor chip 10 is electrically bonded to the metal grounding base 53 of the package 5, the capacitor device 21 is connected to the input terminal 51 of the package, and the drain electrode 14 of the power MOSFET 11 is connected to the output terminal 52 of the package. .
【００１５】本実施例の等価回路を図１０に示す。図１
０において、１０は同一半導体チップに形成するもので
ある。The equivalent circuit of this embodiment is shown in FIG. Figure 1
In 0, 10 is formed on the same semiconductor chip.
【００１６】図１１に半導体チップ１０の断面構造を示
す。ここに７は図９におけるしま状パワーＭＯＳＦＥＴ
１１の１本の断面構造、８は図９におけるソース電極１
３の断面構造、９はＭＯＳＣ２１の断面構造であり、
７，８及び９は同一半導体チップ１０に形成され、相互
はアルミニウム膜による配線によって接続する。FIG. 11 shows a sectional structure of the semiconductor chip 10. Here, 7 is a striped power MOSFET in FIG.
11 is a sectional structure of one, and 8 is the source electrode 1 in FIG.
3 is a sectional structure, 9 is a sectional structure of the MOSC21,
7, 8 and 9 are formed on the same semiconductor chip 10 and are connected to each other by wiring made of an aluminum film.
【００１７】パワーＭＯＳＦＥＴ１１を構成するしま状
トランジスタ１本の構造は７のように、ｐ＋基板の上に
ｐ−層を形成した半導体基板にｎ＋ドレイン層及びソー
ス層，ｎ−ドレインオフセット層，ｐベース層によって
形成する。ソース電極７２はｎ＋ソース層及びｐベース
層に接続し、ドレイン電極７３はｎ＋ドレイン層に接続
する。ゲート電極７１はポリシリコン，高融点金属モリ
ブデン，タングステン等によって成り、ゲート長は約１
μｍ、１本のしま状ゲート，ソース、及びドレインの幅
は約２００μｍ、しまの数は１００本である。この１０
０本を並列接続することによって全ゲート幅約２cmのパ
ワーＭＯＳＦＥＴ１１を構成する。As shown in 7, the structure of one stripe transistor constituting the power MOSFET 11 is as follows: n + drain layer and source layer, n− drain offset layer, p base on a semiconductor substrate in which a p− layer is formed on a p + substrate. Formed by layers. The source electrode 72 is connected to the n + source layer and the p base layer, and the drain electrode 73 is connected to the n + drain layer. The gate electrode 71 is made of polysilicon, refractory metal molybdenum, tungsten, etc., and has a gate length of about 1
The width of the gate, the source and the drain is about 200 μm, and the number of stripes is 100. This 10
A power MOSFET 11 having a total gate width of about 2 cm is formed by connecting 0 pieces in parallel.
【００１８】図９に示すパワーＭＯＳＦＥＴ１１のソー
ス電極１３は１００本のしま状ソース電極７２に接続さ
れ、図１１の８に示すようにｐ＋拡散層によって半導体
チップのｐ＋層に接続される。ｐ＋層は図９に示す金属
接地台５３に電気的に接続される。ＭＯＳＣは図１１の
９に示すように、図１１の７に示すゲート電極７１に相
当する７１′及びその上に接続されたアルミニウム膜を
表面電極とし、半導体チップのｐ＋層に接続されたｐ＋
拡散層と上記ゲート電極７１の間のゲート酸化膜を誘電
体として形成される。ゲート酸化膜は３５ｎｍ程度であ
り、極めて薄いのでＭＯＳＣ２１の占める面積は小さ
い。The source electrode 13 of the power MOSFET 11 shown in FIG. 9 is connected to 100 striped source electrodes 72, and is connected to the p + layer of the semiconductor chip by the p + diffusion layer as shown at 8 in FIG. The p + layer is electrically connected to the metal ground base 53 shown in FIG. As shown in 9 of FIG. 11, the MOSC has a surface electrode 71 'corresponding to the gate electrode 71 shown in 7 of FIG. 11 and an aluminum film connected thereover, and is a p + layer connected to the p + layer of the semiconductor chip.
A gate oxide film between the diffusion layer and the gate electrode 71 is formed as a dielectric. Since the gate oxide film has a thickness of about 35 nm and is extremely thin, the area occupied by the MOSC 21 is small.
【００１９】全ゲート幅２cmのパワーＭＯＳＦＥＴのゲ
ート容量は約４０ｐＦであり、ゲートインピーダンスは
１.５ＧＨｚにおいて約５.３Ωとなる。これは外部回路
のインピーダンス約５０Ωに対して１桁小さいので、こ
のままでは外部回路によるインピーダンス整合が困難で
ある。ゲート容量約４０ｐＦ，ゲート抵抗０.３Ω に対
する内部整合キャパシタＭＯＳＣ２１の容量を約２７ｐ
Ｆとするとインダクタ装置４１の最適インダクタンスは
０.７ｎＨとなる。０.７ｎＨのインダクタンスに対する
ボンディングワイヤの長さは約１mmであるので、半導体
チップの上に立体的に配置することができる。これによ
って外部回路から見たインピーダンスを純抵抗５２Ωに
することができ、外部回路によるインピーダンス整合が
容易となる。The power MOSFET having a total gate width of 2 cm has a gate capacitance of about 40 pF and a gate impedance of about 5.3 Ω at 1.5 GHz. Since this is an order of magnitude smaller than the impedance of the external circuit of about 50Ω, it is difficult to match the impedance by the external circuit as it is. The gate capacitance is about 40pF, and the capacitance of the internal matching capacitor MOSC21 for the gate resistance 0.3Ω is about 27p.
When F is set, the optimum inductance of the inductor device 41 is 0.7 nH. Since the length of the bonding wire for the inductance of 0.7 nH is about 1 mm, it can be three-dimensionally arranged on the semiconductor chip. As a result, the impedance seen from the external circuit can be made to be 52 Ω, which facilitates impedance matching by the external circuit.
【００２０】このように、本実施例は同一半導体チップ
に形成したパワーＭＯＳＦＥＴ１１のゲートとＭＯＳＣ
２１とをインダクタ装置４１によって接続して内部整合
回路を構成しており、インダクタ装置４１を半導体チッ
プ１０の上に立体的に配置しているのが特徴である。こ
こに増幅装置の動作周波数は３００ＭＨｚを越えるの
で、ボンディングワイヤによってインダクタ装置４１を
形成することができる。図９に示した本実施例を図５に
示した従来例に比較すれば、高周波増幅装置５の面積が
約７５％に小さくなることがわかる。さらに高周波増幅
装置におけるキャパシタチップ２、及びその平面配置工
程を省略することができ、高周波増幅装置がボンディン
グワイヤを用いて容易に形成できる。As described above, in this embodiment, the gate of the power MOSFET 11 and the MOSC formed on the same semiconductor chip are integrated.
21 is connected by an inductor device 41 to form an internal matching circuit, and the inductor device 41 is three-dimensionally arranged on the semiconductor chip 10. Since the operating frequency of the amplifier device exceeds 300 MHz, the inductor device 41 can be formed by the bonding wire. By comparing the present embodiment shown in FIG. 9 with the conventional example shown in FIG. 5, it can be seen that the area of the high frequency amplifying device 5 is reduced to about 75%. Further, the capacitor chip 2 in the high-frequency amplifier and the step of arranging it in the plane can be omitted, and the high-frequency amplifier can be easily formed by using the bonding wire.
【００２１】本実施例ではゲートに対する内部整合化高
周波増幅装置に対する本発明の適用を示したが、この限
りではなく更にドレインに対する内部整合化高周波増幅
装置にも適用することができる。In the present embodiment, the application of the present invention to the internal matching high frequency amplifying device for the gate has been shown, but the present invention is not limited to this, and can also be applied to the internal matching high frequency amplifying device for the drain.
【００２２】第２の実施例を図１２に示す。本実施例は
パワーＭＯＳＦＥＴ１１のゲートに対する内部整合回路
を有するとともに、ドレインに対する第２次高調波制御
用内部整合回路を有する高周波電力増幅装置を示す。図
１２の等価回路を図１３に示す。ゲートに対する内部整
合回路は実施例１に示したとおりである。The second embodiment is shown in FIG. The present embodiment shows a high frequency power amplifier having an internal matching circuit for the gate of the power MOSFET 11 and a second harmonic control internal matching circuit for the drain. The equivalent circuit of FIG. 12 is shown in FIG. The internal matching circuit for the gate is as shown in the first embodiment.
【００２３】本実施例はパワーＭＯＳＦＥＴ１１，ＭＯ
ＳＣ２１とともにＭＯＳＣ２２を同一半導体チップに形
成し、パワーＭＯＳＦＥＴ１１のドレインとＭＯＳＣ２
２とをインダクタ装置４２によって接続しており、イン
ダクタ装置４２も半導体チップ１０の上に立体的に配置
しているのが特徴である。更に、パワーＭＯＳＦＥＴ１
１のドレイン電極１４はパッケージ５の出力端子５２に
接続して第２次高調波に同調するドレイン内部整合化高
周波増幅装置を構成している。ここに増幅装置の動作周
波数は３００ＭＨｚを越えるので、ボンディングワイヤ
によってインダクタ装置４２を形成することができる。In this embodiment, the power MOSFET 11, MO
MOSC22 is formed on the same semiconductor chip together with SC21, and the drain of power MOSFET 11 and MOSC2 are formed.
2 is connected by an inductor device 42, and the inductor device 42 is also three-dimensionally arranged on the semiconductor chip 10. Furthermore, power MOSFET 1
The drain electrode 14 of No. 1 is connected to the output terminal 52 of the package 5 and constitutes a drain internal matching high frequency amplifier which tunes to the second harmonic. Since the operating frequency of the amplifier device exceeds 300 MHz, the inductor device 42 can be formed by the bonding wire.
【００２４】また本実施例はゲート内部整合回路の他
に、ドレイン電極に直列接続した第２次高調波制御用内
部整合回路を接続しており、外部のドレイン整合回路に
影響されない能率的な高調波制御を行なうことができる
ので、高周波電力損失が少なくドレイン効率の高い高周
波増幅装置をワイヤボンディングによって容易に構成す
ることができる。Further, in this embodiment, in addition to the gate internal matching circuit, a second-order harmonic control internal matching circuit connected in series to the drain electrode is connected, so that an efficient harmonic that is not affected by an external drain matching circuit. Since the wave control can be performed, it is possible to easily form a high frequency amplifier having a high radio frequency power loss and a high drain efficiency by wire bonding.
【００２５】第３の実施例を図１４に示す。等価回路を
図１５に示す。本実施例はゲートに対する内部整合化高
周波電力増幅装置を示す。本実施例は同一半導体チップ
にパワーＭＯＳＦＥＴ１１を３個並列に形成して増幅電
力を３倍に高くしたものである。パワーＭＯＳＦＥＴ１
１とともに最適な内部整合キャパシタＭＯＳＣ２１を３
個並列に設置した。実施例１と同様に内部整合キャパシ
タＭＯＳＣ２１はパワーＭＯＳＦＥＴ１１と対を成すよ
うに形成するものであり、パワーMOSFET11のゲートとＭ
ＯＳＣ２１はそれぞれ半導体チップの上に立体的に配置
したインダクタ装置４１によって接続する。本実施例は
実施例１と同じ半導体装置３対によって成るが、このか
ぎりではなく、２対から５対程度が適当である。FIG. 14 shows the third embodiment. The equivalent circuit is shown in FIG. This embodiment shows an internally matched high frequency power amplifier for a gate. In this embodiment, three power MOSFETs 11 are formed in parallel on the same semiconductor chip to triple the amplified power. Power MOSFET 1
3 together with the optimum internal matching capacitor MOSC21
We installed them in parallel. Similar to the first embodiment, the internal matching capacitor MOSC21 is formed so as to form a pair with the power MOSFET 11, and the gate of the power MOSFET 11 and M
The OSCs 21 are connected by the inductor devices 41 which are three-dimensionally arranged on the semiconductor chips. This embodiment is composed of the same three semiconductor device pairs as in the first embodiment, but not limited to this, about two to five pairs are suitable.
【００２６】また、本実施例は同一半導体チップに形成
された３対の半導体装置によって構成したが、このかぎ
りではなく、個々の分離された３対の半導体装置によっ
て構成することもできる。これによって電力の高い高周
波増幅装置をワイヤボンディングによって容易に構成す
ることができる。５対以上１０対以下の並列設置数の場
合は外部回路から見たインピーダンスを高くするために
ＭＯＳＣ２１のキャパシタンスを例えば１６ｐＦとし、
それに応じてインダクタ装置４１のインダクタンスを１
ｎＨに大きくした単位半導体装置とすることができる。
その場合、外部回路から見たインピーダンスは１５３Ω
になるが、このかぎりではなく、外部回路から見たイン
ピーダンスを純抵抗にするとともに、これを所要の抵抗
値にする条件を設定する。Further, although the present embodiment is constituted by three pairs of semiconductor devices formed on the same semiconductor chip, the present invention is not limited to this, and it may be constituted by three separate pairs of semiconductor devices. As a result, a high-frequency amplifier having high power can be easily constructed by wire bonding. When the number of parallel installation is 5 pairs or more and 10 pairs or less, the capacitance of the MOSC 21 is set to, for example, 16 pF in order to increase the impedance viewed from the external circuit,
Accordingly, the inductance of the inductor device 41 is set to 1
A unit semiconductor device having a large nH can be obtained.
In that case, the impedance seen from the external circuit is 153Ω.
However, not limited to this, the impedance seen from the external circuit is set to a pure resistance, and the condition for setting this to a required resistance value is set.
【００２７】本実施例ではゲートに対する内部整合化高
周波増幅装置に対する本発明の適用を示したが、この限
りではなく更にドレインに対する内部整合化高周波増幅
装置にも適用することができる。In the present embodiment, the application of the present invention to the internal matching high frequency amplifying device for the gate has been shown, but the present invention is not limited to this, and can also be applied to the internal matching high frequency amplifying device for the drain.
【００２８】第４の実施例を図１６に示す。等価回路を
図１７に示す。本実施例はゲートに対する内部整合回路
を有するとともに、ドレインに対する第２次高調波制御
用内部整合回路を有する高周波電力増幅装置を示す。本
実施例は同一半導体チップにパワーＭＯＳＦＥＴ１１を
２個並列に形成して増幅電力を２倍にしたものである。
パワーＭＯＳＦＥＴ１１とともに最適なゲート内部整合
キャパシタMOSC21、及び第２次高調波制御用ドレイン内
部整合キャパシタＭＯＳＣ２２をそれぞれ２個並列に設
置した。実施例２と同様に内部整合キャパシタＭＯＳＣ
２１，MOSC22はパワーＭＯＳＦＥＴ１１と対をなすよう
に形成するものであり、パワーMOSFET11のゲートとＭＯ
ＳＣ２１、及びパワーＭＯＳＦＥＴ１１のドレインとMO
SC22はそれぞれ半導体チップの上に立体的に配置したイ
ンダクタ装置４１，４２によって接続するものである。
これによって電力の高い第２次高調波制御化高周波増幅
装置をワイヤボンディングによって容易に構成すること
ができる。FIG. 16 shows the fourth embodiment. The equivalent circuit is shown in FIG. The present embodiment shows a high frequency power amplifier having an internal matching circuit for the gate and a second harmonic control internal matching circuit for the drain. In this embodiment, two power MOSFETs 11 are formed in parallel on the same semiconductor chip to double the amplified power.
Two optimum gate internal matching capacitors MOSC21 and second internal harmonic control drain internal matching capacitors MOSC22 were installed in parallel with the power MOSFET 11. Internal matching capacitor MOSC as in the second embodiment
21, MOSC22 are formed so as to form a pair with the power MOSFET 11, and the gate of the power MOSFET 11 and the MOC22 are formed.
SC21, drain of power MOSFET 11 and MO
SC22 are connected by inductor devices 41 and 42 which are three-dimensionally arranged on the semiconductor chip.
This makes it possible to easily construct a high-power second-harmonic-controlled high-frequency amplifier by wire bonding.
【００２９】本実施例は実施例２と同じ半導体装置２対
によって成るが、このかぎりではなく、３対から５対程
度が適当である。また、ゲートに対する内部整合回路の
構成に関しては実施例３と同様であり、５対以上にも適
用することができる。ここにドレインに関する内部整合
回路の構成は第２次高調波に対する短絡を行なうもので
あるが、このかぎりではなく、第２次高調波に対する開
放、基本波に対するドレイン内部整合にも適用すること
ができる。This embodiment is composed of two pairs of semiconductor devices which are the same as those of the second embodiment, but not limited to this, about 3 to 5 pairs are suitable. Further, the configuration of the internal matching circuit for the gate is similar to that of the third embodiment, and it can be applied to five pairs or more. Here, the configuration of the internal matching circuit for the drain is to short-circuit the second harmonic, but the configuration is not limited to this, and it can be applied to the opening to the second harmonic and the drain internal matching to the fundamental wave. .
【００３０】本実施例ではドレインに対する第２次高調
波制御化高周波電力増幅装置に対する本発明の適用を示
したが、この限りではなく更にゲートに対する第２次高
調波制御化高周波増幅装置にも適用することができる。In the present embodiment, the application of the present invention to the second harmonic controlled high frequency power amplifier for the drain has been shown, but the present invention is not limited to this, and it is also applied to the second harmonic controlled high frequency amplifier for the gate. can do.
【００３１】[0031]
【発明の効果】本発明によればトランジスタ装置ととも
に常に最適な内部整合キャパシタ装置を提供し、同時に
最適なインダクタ装置の安定な形成を可能とするもので
あり、３００ＭＨｚ以上の内部整合化高周波増幅装置を
能率的に構成することができる。これによって小型で電
力損失の少ない高周波増幅装置を安定に供給することが
できる。According to the present invention, an optimum internal matching capacitor device is always provided together with a transistor device, and at the same time, an optimum inductor device can be stably formed, and an internal matching high frequency amplifying device of 300 MHz or more is provided. Can be efficiently configured. As a result, it is possible to stably supply a small-sized high-frequency amplifier device with low power loss.
【図１】本発明の原理的構成を示す平面図。FIG. 1 is a plan view showing the basic configuration of the present invention.
【図２】図１の等価回路図。FIG. 2 is an equivalent circuit diagram of FIG.
【図３】本発明の変形例の構成を示す平面図。FIG. 3 is a plan view showing the configuration of a modified example of the present invention.
【図４】図３の等価回路図。FIG. 4 is an equivalent circuit diagram of FIG.
【図５】第１の従来例の平面図。FIG. 5 is a plan view of a first conventional example.
【図６】図５の等価回路図。6 is an equivalent circuit diagram of FIG.
【図７】第２の従来例の平面図。FIG. 7 is a plan view of a second conventional example.
【図８】図７の等価回路図。8 is an equivalent circuit diagram of FIG. 7.
【図９】本発明の第１の実施例の高周波増幅装置の平面
図。FIG. 9 is a plan view of the high-frequency amplifier device according to the first embodiment of the present invention.
【図１０】図９の等価回路図。FIG. 10 is an equivalent circuit diagram of FIG.
【図１１】図９に示す装置の半導体チップの要部断面
図。11 is a cross-sectional view of a main part of a semiconductor chip of the device shown in FIG.
【図１２】本発明の第二の実施例の平面図。FIG. 12 is a plan view of the second embodiment of the present invention.
【図１３】図１２の等価回路図。FIG. 13 is an equivalent circuit diagram of FIG.
【図１４】本発明の第三の実施例の平面図。FIG. 14 is a plan view of the third embodiment of the present invention.
【図１５】図１４の等価回路図。FIG. 15 is an equivalent circuit diagram of FIG.
【図１６】本発明の第四の実施例の平面図。FIG. 16 is a plan view of the fourth embodiment of the present invention.
【図１７】図１６の等価回路。FIG. 17 is an equivalent circuit of FIG.
１１…パワーＭＯＳＦＥＴ、１２…ゲート電極、１３…
ソース電極、２１…ＭＯＳキャパシタ装置、４１…イン
ダクタ装置、６１…ゲート端子、６２…ドレイン端子、
６３…キャパシタ付属端子。11 ... Power MOSFET, 12 ... Gate electrode, 13 ...
Source electrode, 21 ... MOS capacitor device, 41 ... Inductor device, 61 ... Gate terminal, 62 ... Drain terminal,
63 ... Terminal attached to the capacitor.
Claims (12)
パシタより成る半導体チップを主体とする高周波増幅装
置において、前記ＭＯＳ電界効果トランジスタのゲート
と前記ＭＯＳキャパシタとを前記半導体チップの上に立
体的に配置したインダクタ装置によって接続したことを
特徴とする高周波増幅装置。1. A high frequency amplifier mainly comprising a semiconductor chip composed of a MOS field effect transistor and a MOS capacitor, and an inductor in which a gate of the MOS field effect transistor and the MOS capacitor are three-dimensionally arranged on the semiconductor chip. A high frequency amplifying device characterized by being connected by a device.
ランジスタのゲートを前記高周波増幅装置の入力端子と
接続し、ドレインを前記高周波増幅装置の出力端子と接
続した高周波増幅装置。2. The high frequency amplification device according to claim 1, wherein a gate of the MOS field effect transistor is connected to an input terminal of the high frequency amplification device and a drain thereof is connected to an output terminal of the high frequency amplification device.
を前記高周波増幅装置の入力端子と接続し、前記ＭＯＳ
電界効果トランジスタのドレインを前記高周波増幅装置
の出力端子と接続した高周波増幅装置。3. The MOS capacitor according to claim 1, wherein the MOS capacitor is connected to an input terminal of the high frequency amplifier.
A high frequency amplifying device in which a drain of a field effect transistor is connected to an output terminal of the high frequency amplifying device.
パシタより成る半導体チップを主体とする高周波増幅装
置において、前記ＭＯＳ電界効果トランジスタのドレイ
ンと前記ＭＯＳキャパシタとを前記半導体チップの上に
立体的に配置したインダクタ装置によって接続した高周
波増幅装置。4. A high frequency amplifier mainly comprising a semiconductor chip composed of a MOS field effect transistor and a MOS capacitor, wherein the drain of the MOS field effect transistor and the MOS capacitor are three-dimensionally arranged on the semiconductor chip. High frequency amplifier connected by the device.
ランジスタのゲートを前記高周波増幅装置の入力端子と
接続し、前記ドレインを前記高周波増幅装置の出力端子
と接続した高周波増幅装置。5. The high frequency amplification device according to claim 4, wherein the gate of the MOS field effect transistor is connected to the input terminal of the high frequency amplification device and the drain is connected to the output terminal of the high frequency amplification device.
ランジスタのゲートを前記高周波増幅装置の入力端子と
接続し、前記ＭＯＳキャパシタを前記高周波増幅装置の
出力端子と接続した高周波増幅装置。6. The high frequency amplifying device according to claim 4, wherein the gate of the MOS field effect transistor is connected to an input terminal of the high frequency amplifying device and the MOS capacitor is connected to an output terminal of the high frequency amplifying device.
のＭＯＳキャパシタより成る半導体チップを主体とする
高周波増幅装置において、前記ＭＯＳ電界効果トランジ
スタのゲートと前記第１のキャパシタとを前記半導体チ
ップの上に立体的に配置した第１のインダクタ装置によ
って接続し、前記ＭＯＳ電界効果トランジスタのドレイ
ンと前記第２のＭＯＳキャパシタとを前記半導体チップ
の上に立体的に配置した第２のインダクタ装置によって
接続したことを特徴とする高周波増幅装置。7. A MOS field effect transistor and first and second MOS field effect transistors.
In a high-frequency amplifier device mainly composed of a semiconductor chip composed of a MOS capacitor, the gate of the MOS field effect transistor and the first capacitor are connected by a first inductor device which is three-dimensionally arranged on the semiconductor chip. A high-frequency amplifier device, wherein the drain of the MOS field effect transistor and the second MOS capacitor are connected by a second inductor device which is three-dimensionally arranged on the semiconductor chip.
ランジスタのゲートを前記高周波増幅装置の入力端子と
接続し、前記ドレインを前記高周波増幅装置の出力端子
と接続した高周波増幅装置。8. The high frequency amplifying device according to claim 7, wherein the gate of the MOS field effect transistor is connected to an input terminal of the high frequency amplifying device, and the drain is connected to an output terminal of the high frequency amplifying device.
ランジスタのゲートを前記高周波増幅装置の入力端子と
接続し、前記第２のキャパシタを前記高周波増幅装置の
出力端子と接続した高周波増幅装置。9. The high frequency amplifying device according to claim 7, wherein the gate of the MOS field effect transistor is connected to an input terminal of the high frequency amplifying device, and the second capacitor is connected to an output terminal of the high frequency amplifying device.
前記高周波増幅装置の入力端子と接続し、前記ドレイン
を前記高周波増幅装置の出力端子と接続した高周波増幅
装置。10. The high frequency amplification device according to claim 7, wherein the first capacitor is connected to an input terminal of the high frequency amplification device and the drain is connected to an output terminal of the high frequency amplification device.
タを前記高周波増幅装置の入力端子と接続し、前記第２
のキャパシタを前記高周波増幅装置の出力端子と接続し
た高周波増幅装置。11. The method according to claim 7, wherein the first capacitor is connected to an input terminal of the high frequency amplifier, and the second capacitor is connected to the input terminal of the high frequency amplifier.
High frequency amplification device in which the capacitor of (1) is connected to the output terminal of the high frequency amplification device.
８，９，１０または１１に記載の前記高周波増幅装置か
らなる高周波電力増幅装置。12. Claims 1, 2, 3, 4, 5, 6, 7,
A high frequency power amplification device comprising the high frequency amplification device according to 8, 9, 10 or 11.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4160621A JPH065794A (en) | 1992-06-19 | 1992-06-19 | High frequency amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4160621A JPH065794A (en) | 1992-06-19 | 1992-06-19 | High frequency amplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH065794A true JPH065794A (en) | 1994-01-14 |
Family
ID=15718893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4160621A Pending JPH065794A (en) | 1992-06-19 | 1992-06-19 | High frequency amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH065794A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11233799A (en) * | 1997-09-03 | 1999-08-27 | Motorola Inc | Variable capacitor and its manufacture |
| EP1168607A2 (en) * | 2000-06-22 | 2002-01-02 | Texas Instruments Incorporated | An on-chip signal filter with bond wire inductors |
| WO2002037573A1 (en) * | 2000-10-30 | 2002-05-10 | Kabushiki Kaisha Toshiba | Semiconductor device and its manufacturing method |
| JP2007059924A (en) * | 2006-09-22 | 2007-03-08 | Mitsubishi Electric Corp | Semiconductor device |
| US7598660B2 (en) | 2005-02-15 | 2009-10-06 | Murata Manufacturing Co., Ltd. | Monolithic piezoelectric element |
| JP2012015531A (en) * | 2011-08-01 | 2012-01-19 | Renesas Electronics Corp | Semiconductor device |
| JP2012019221A (en) * | 2011-08-01 | 2012-01-26 | Renesas Electronics Corp | Semiconductor device |
| EP2458636A1 (en) * | 2010-11-29 | 2012-05-30 | Nxp B.V. | Compensation Network for RF Transistor |
| JP2012227342A (en) * | 2011-04-19 | 2012-11-15 | Toshiba Corp | Power amplifier |
| WO2018003111A1 (en) * | 2016-07-01 | 2018-01-04 | 三菱電機株式会社 | Amplifier |
| WO2019106909A1 (en) * | 2017-11-30 | 2019-06-06 | ソニーセミコンダクタソリューションズ株式会社 | High frequency amplifier, electronic device, and communication device |
-
1992
- 1992-06-19 JP JP4160621A patent/JPH065794A/en active Pending
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11233799A (en) * | 1997-09-03 | 1999-08-27 | Motorola Inc | Variable capacitor and its manufacture |
| EP1168607A2 (en) * | 2000-06-22 | 2002-01-02 | Texas Instruments Incorporated | An on-chip signal filter with bond wire inductors |
| EP1168607A3 (en) * | 2000-06-22 | 2005-12-28 | Texas Instruments Incorporated | An on-chip signal filter with bond wire inductors |
| WO2002037573A1 (en) * | 2000-10-30 | 2002-05-10 | Kabushiki Kaisha Toshiba | Semiconductor device and its manufacturing method |
| US6940132B2 (en) | 2000-10-30 | 2005-09-06 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US7598660B2 (en) | 2005-02-15 | 2009-10-06 | Murata Manufacturing Co., Ltd. | Monolithic piezoelectric element |
| JP2007059924A (en) * | 2006-09-22 | 2007-03-08 | Mitsubishi Electric Corp | Semiconductor device |
| US8981433B2 (en) | 2010-11-29 | 2015-03-17 | Nxp, B.V. | Compensation network for RF transistor |
| EP2458636A1 (en) * | 2010-11-29 | 2012-05-30 | Nxp B.V. | Compensation Network for RF Transistor |
| JP2012227342A (en) * | 2011-04-19 | 2012-11-15 | Toshiba Corp | Power amplifier |
| US8610507B2 (en) | 2011-04-19 | 2013-12-17 | Kabushiki Kaisha Toshiba | Power amplifier |
| JP2012019221A (en) * | 2011-08-01 | 2012-01-26 | Renesas Electronics Corp | Semiconductor device |
| JP2012015531A (en) * | 2011-08-01 | 2012-01-19 | Renesas Electronics Corp | Semiconductor device |
| WO2018003111A1 (en) * | 2016-07-01 | 2018-01-04 | 三菱電機株式会社 | Amplifier |
| JPWO2018003111A1 (en) * | 2016-07-01 | 2018-08-23 | 三菱電機株式会社 | amplifier |
| WO2019106909A1 (en) * | 2017-11-30 | 2019-06-06 | ソニーセミコンダクタソリューションズ株式会社 | High frequency amplifier, electronic device, and communication device |
| US11336241B2 (en) | 2017-11-30 | 2022-05-17 | Sony Semiconductor Solutions Corporation | High-frequency amplifier, electronic device, and communication device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1750298B1 (en) | RF power transistor with impedance matched output electrode | |
| US6177834B1 (en) | Output matched LDMOS power transistor device | |
| US5760650A (en) | Coplanar waveguide amplifier | |
| JPH06125208A (en) | Microwave integrated circuit and its production | |
| JPH11308059A (en) | High frequency amplifier | |
| JPH065794A (en) | High frequency amplifier | |
| JP2001111364A (en) | Microwave amplifier | |
| EP0015709B1 (en) | Constructional arrangement for semiconductor devices | |
| JPH11346130A (en) | Semiconductor device | |
| JP3004882B2 (en) | Spiral inductor, microwave amplifier circuit and microwave amplifier | |
| JPS6114183Y2 (en) | ||
| JP2018107387A (en) | Semiconductor device | |
| US6800929B1 (en) | Semiconductor device | |
| JPS6114182Y2 (en) | ||
| JP2001244710A (en) | High-frequency device and mobile wireless unit using the same | |
| JP2002043812A (en) | High-frequency device and mobile radio set using the same | |
| JPS6364081B2 (en) | ||
| JP2010021961A (en) | Amplifier | |
| JP2001345606A (en) | Mmic amplifier | |
| JPH07321130A (en) | Semiconductor device | |
| JPH08172306A (en) | High frequency device and mobile radio equipment using the device | |
| JP2000082788A (en) | Microstrip line, spiral inductor, and electronic device and its manufacture | |
| RU2192692C1 (en) | High-power broadband high-frequency and microwave transistor | |
| JPH054281Y2 (en) | ||
| JPH02119174A (en) | Integrated high frequency amplifier |