JP2010021961A - Amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately adjust inductance or capacitance in an amplifier that performs Class-EJ operation. <P>SOLUTION: In an amplifier 1, a microstrip substrate 3 is connected to a semiconductor chip 2. On the semiconductor chip 2, a field effect transistor having capacitive impedance between a drain and a source is mounted. The microstrip substrate 3 constitutes an inductor connected to the drain so as to be positioned on a post-stage rather than the capacitive impedance and a capacitor connected in parallel to the capacitive impedance via the inductor by forming a conductive part on a surface of a substrate constituted of an insulator. The conductive part constituting the inductor includes a plurality of strip-like unit inductor domains 31a arrayed on the substrate and a connector domain 31b mutually bridging partial or all the unit inductor domains among the plurality od unit inductor domains at both terminals thereof. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an amplifier that performs so-called EJ class operation, which is an improvement of class J.

  There are various operational classes of amplifiers. For example, Non-Patent Document 1 includes Class A (Class A), Class AB (Class AB), Class B (Class B), Class C (Class C), Class D (Class D), Class E (Class E), Class F (Class F), Class FD (Class FD), and Class J (Class J) amplifiers are disclosed.

The basic circuit of the class J amplifier in Non-Patent Document 1 is as shown in FIG. 21 (see Non-Patent Document 1: P71, Figure 4.2). In FIG. 21, the field effect transistor Tr is represented as a half-wave rectified current source. Further, RL shown in FIG. 21 is an effective load of the fundamental wave (ω ₀ = 2πf ₀ ), and its value is expressed as RL = Vdc / (Imax × 0.5).
In addition, Id, IF, Idc, and Ic in the figure are represented by the following equations.

The feature of the class J amplifier shown in FIG. 21 is that Cds is connected between the drain and source of the field effect transistor Tr, and that Xds / RL exceeds 1 when Xds = 1 / ω ₀ Cds. , Cds is set (see Non-Patent Document 1 (P.68)).
FIG. 22 shows voltage / current waveforms (drain-source voltage Vds and drain current Id waveforms) of a conventional class J amplifier.

Steve C. Cripps, “RF Power Amplifiers for Wireless Communications”, Second Edition, (USA), ARTECH House Inc, 2006, P68-77

  In the conventional class J amplifier as described above, the voltage waveform Vds and the current waveform Id are not symmetrical as shown in FIG. That is, the phase difference between the drain-source voltage Vds and the drain current Id was not 180 °. As a result, the voltage waveform Vds and the current waveform Id overlap each other, and there is room for improvement with respect to the efficiency of the amplifier.

  FIG. 14 is a circuit diagram of the amplifier 1 that performs the so-called class EJ operation, which is an improvement of the class J amplifier (see Japanese Patent Application No. 2007-263539). The operation of the EJ class will be described later. The amplifier 1 is used, for example, as a power amplifier for wireless communication, and is particularly suitable for communication in the GHz band (for example, about 2 GHz). In the figure, a field effect transistor Tr is mounted on the amplifier 1, and its gate G is an input terminal Pin of the amplifier 1. Further, between the drain D and the source S of the field effect transistor Tr, there is a first capacitor Cds that forms a capacitive impedance.

  On the other hand, an inductor Ls connected between the drain D and the output terminal Pout so as to be located behind the first capacitor Cds, and a second capacitor connected in parallel to the first capacitor Cds via the inductor Ls. Cs. The inductance of the inductor Ls and the capacitance of the second capacitor Cs are set to optimum values according to the output impedance ZL of the semiconductor chip 2. The amplifier 1 is connected to a resistor RL1 as an output load.

  In the EJ class amplifier as described above, the output impedance ZL of the semiconductor chip 2 varies from product to product. Therefore, the inductance of the inductor Ls and the capacitance of the second capacitor Cs must be adjusted to optimum values for each product. Adjustment is performed by laser processing a microstrip line formed on a substrate, but it is difficult to obtain desired inductance and capacitance with high accuracy.

  In view of such a conventional problem, an object of the present invention is to make it possible to accurately adjust inductance and capacitance in an amplifier that performs so-called EJ class operation with improved class J.

  The present invention relates to a field effect transistor having a capacitive impedance between a drain and a source, an inductor connected to the drain so as to be located behind the capacitive impedance, and the capacitive impedance via the inductor. And a microstrip substrate configured by forming a conductive portion on a surface of a substrate made of an insulator, and the inductor has an impedance at a fundamental frequency of the capacitive impedance portion. The conductive portion constituting the inductor includes a plurality of unit inductor regions arranged on the substrate and a part or all of the plurality of unit inductors. With connecting piece regions bridging each other at their ends And wherein the door.

  In the amplifier as described above, the inductance is constituted by an aggregate of unit inductor regions bridged by the connection piece regions. Since the inductance of each unit inductor region can be formed with high accuracy, a desired inductance can be configured with high accuracy as a whole.

In the above amplifier, the conductive portion constituting the capacitor includes a plurality of unit capacitor regions arranged on the substrate and a connection that bridges the regions between some or all of the plurality of unit capacitor regions. It may have a single region.
In this case, the capacitance is constituted by an assembly of unit capacitor regions that are bridged by the connection piece regions. Since the capacitance of each unit capacitor region can be formed with high accuracy, a desired capacitance can be configured with high accuracy as a whole.

In the amplifier, it is preferable that all the conductive portions are formed symmetrically with respect to the center line in the arrangement direction of the unit inductor regions as a whole.
In this case, it is possible to effectively use the entire area of the microstrip substrate to suppress a useless empty area, and since the device is symmetrical, there is no bias in the signal path length. As a result, the microstrip substrate can be made compact, and power synthesis is ideally achieved.

In the amplifier, the unit capacitor regions may be arranged outside the region occupied by all the unit inductor regions in the arrangement direction of the unit inductor regions.
In this case, the entire conductive portion (inductance / capacitance) has a compact size in the longitudinal direction of the unit inductor region. Therefore, the package base of the amplifier can be made compact.

  On the other hand, the present invention provides a field effect transistor having a capacitive impedance between a drain and a source, an inductor connected to the drain so as to be located at a later stage than the capacitive impedance, and the capacitance via the inductor. And a microstrip substrate configured by forming a conductive part on the surface of a substrate made of an insulator, and the inductor has an impedance at the fundamental frequency of the capacitor. The amplifier is set to a value equal to or higher than the impedance of the impedance unit, and the conductive unit constituting the capacitor includes a plurality of unit capacitor regions arranged on the substrate and a part or all of the plurality of unit capacitor regions. The unit capacitor area has a connection piece area that bridges between the areas. It is characterized in.

  In the amplifier as described above, the capacitance is constituted by an aggregate of unit capacitor regions bridged by the connection piece region. Since the capacitance of each unit capacitor region can be formed with high accuracy, a desired capacitance can be configured with high accuracy as a whole.

  According to the amplifier of the present invention, impedance (inductance / capacitance) can be adjusted with good reproducibility and accuracy in order to realize so-called EJ class operation in a more ideal state.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
<Basic circuit configuration>
First, the amplifier 1 that performs EJ class operation will be described in detail.
FIG. 14 shows a so-called EJ class amplifier 1 which is an improvement over a conventional class J amplifier. In the following, the operational class of the amplifier 1 according to the embodiment is referred to as “Class EJ”.

  FIG. 14 is a circuit diagram showing the amplifier 1 that performs the EJ class operation according to the embodiment. The amplifier 1 is used, for example, as a power amplifier for wireless communication, and is particularly suitable for communication in the GHz band (for example, about 2 GHz). In the figure, the amplifier 1 is structurally composed of a semiconductor chip 2 and a microstrip substrate 3. A field effect transistor Tr is mounted on the semiconductor chip 2, and its gate G is an input terminal Pin of the amplifier 1. Further, between the drain D and the source S of the field effect transistor Tr, there is a first capacitor Cds that forms a capacitive impedance.

  On the other hand, the microstrip substrate 3 on which the LC circuit is mounted has an inductor Ls connected between the drain D and the output terminal Pout so as to be located on the rear stage side of the first capacitor Cds, and the first via the inductor Ls. And a second capacitor Cs connected in parallel to one capacitor Cds. The inductor Ls and the capacitor Cds are configured by forming a microstrip line on the microstrip substrate 3. The inductance of the inductor Ls and the capacitance of the second capacitor Cs are set to optimum values according to the output impedance ZL of the semiconductor chip 2. The amplifier 1 is connected to a resistor RL1 as an output load.

  That is, in the EJ class amplifier 1, a C-L-C π-type circuit including the first capacitor Cds, the inductor Ls, and the second capacitor Cs is connected to the output side of the field effect transistor Tr. The class EJ amplifier 1 is different from the conventional class J amplifier in that an LC circuit including an inductor Ls and a second capacitor Cs is added.

Now, in order to reduce the overlap between the voltage waveform Vds and the voltage waveform Id generated in the conventional class J amplifier as shown in FIG. 22, in this class EJ amplifier 1, by appropriately setting the value of the inductor Ls, The impedance Z0 (impedance seen from the drain D / source S of the field effect transistor to the output side) in FIG. 14 is made capacitive.
That is, in the present embodiment, the impedance (2πf ₀ Ls = ω ₀ Ls) at the fundamental frequency of the inductor Ls is equal to the impedance (Xds = 1 / 2πf ₀ Cds = 1 / (ω ₀ Cds) of the capacitive impedance unit Cds. ) It is set to be the above value.
That is, in this embodiment, the relationship of ω ₀ Ls ≧ 1 / (ω ₀ Cds) is established.

Hereinafter, it will be described in detail that ω ₀ Ls ≧ 1 / (ω ₀ Cds) may be used in order to reduce the overlap between the voltage waveform Vds and the voltage waveform Ids that has occurred in the conventional class J amplifier.

  First, in the voltage waveform Vds and the current waveform Id shown in FIG. 22, the phase difference Δθ between the peaks is 133 deg, and the phase difference Δθ of these waveforms is set to 180 deg to eliminate the overlap between the voltage waveform Vds and the current waveform Id. Therefore, the phase of the current waveform Id may be shifted by about 45 degrees. That is, the current waveform Id may be shifted 45 degrees to the right in FIG.

The reason why the phase of the current waveform Id should be shifted by about 45 degrees is as follows.
That is, the voltage waveform Vds (see FIG. 22) of the class J amplifier is expressed by the following equation (1).

  From the above equation (1), the phase θvp at which the voltage waveform Vds (θ) peaks is obtained. In order to obtain the peak phase θvp, the following equations (2) and (3) may be solved.

  That is, from equation (2)

From equation (3),

It is.

  On the other hand, the parameters during the conventional class J operation shown in FIG. 22 are as follows.

  Substituting the above parameters into Equations (4) and (5) yields θvp = 317 [deg]. Therefore, the difference Δθ between the peak phase θvp of the voltage waveform Vds and the peak phase θip of the current waveform Id is 133 deg as shown in FIG. Therefore, in order to invert the voltage waveform Vds and the current waveform Id so that Δθ = 180 deg, the phase relationship between the voltage waveform Vds and the current waveform Id is about 45 deg (≈47 deg) compared to the conventional class J operation. = (180 deg-133 deg))

In the present embodiment, since the shift 45deg phase relationship between the voltage waveform Vds and current waveform Id, relates impedance Z0 in FIG. 14, the impedance at the second harmonic (2 × ω ₀₎ Z0 of (2 × ω ₀₎ Capacitance (second harmonic phase is approximately -90 deg). When the second harmonic impedance Z0 (2 × ω ₀ ) is capacitive, the current waveform Id (fundamental wave ω ₀ ) is shifted by 45 degrees (right shift in FIG. 22).
In order to make the second harmonic impedance Z0 (2 × ω ₀ ) sufficiently capacitive while causing the amplifier 1 to perform class J operation, as a result of the study by the present inventors, ω ₀ Ls ≧ 1 / ω ₀ Cds (EJ It has been found that class condition 1) is sufficient. By setting ω ₀ Ls ≧ 1 / ω ₀ Cds, | Z1 (2ω ₀ ) | is sufficiently larger than 1 / (2ω ₀ Cds) with respect to the impedance Z1 viewed from the first capacitor Cds to the output side. Become.

In addition, since the class EJ is premised on class J operation, the class J operation condition needs to be satisfied even if the inductor Ls and the second capacitor Cs are added to the conventional class J amplifier. In the conventional class J amplifier shown in FIG. 21, the class J operating condition is Xds / RL> 1 when Xds = 1 / ω ₀ Cds.
In the class EJ amplifier 1 of the present embodiment, the real part Z1 (Re) of the impedance Z1 viewed from the first capacitor Cds on the output side corresponds to the RL of the conventional class J amplifier.
Therefore, in order for the class EJ amplifier 1 to maintain the class J operating condition, Xds / Z1 (Re)> 1 (the class EJ condition 2 = the class J operating condition), and if this condition is satisfied, the inductor Ls and Even if the second capacitor Cs is added, the maximum power can be supplied.

In the case of the circuit shown in FIG. 14, Z1 (Re) is specifically obtained by Z1 (Re) = RL1 · Xcs ² / (RL1 ² + Xcs ² ). Note that Xcs = 1 / ω ₀ Cs.

Further, when Xds / Z1 (Re) exceeds 2.5, the efficiency starts to deteriorate. Therefore, it is preferable that Xds / Z1 (Re) <2.5. That is, by setting 1 <Xds / Z1 (Re) <2.5, it is possible to prevent the efficiency degradation while operating the EJ class amplifier under the J class operating condition.
When Xds / Z1 (Re) is 1 or less, a class B amplifier is obtained.

In the class EJ amplifier of FIG. 14, for example, when the fundamental frequency is 2.0 [GHz], the first capacitor Cds = 10 [pF], and the output load RL1 = 50 [Ω], the inductor Ls is 0.7 [nH When the second capacitor Cs is 4 [pF] or more, the EJ class condition 1 ω ₀ Ls ≧ 1 / ω ₀ Cds can be satisfied in the J class operation. Under the above conditions, a second harmonic phase (φ2) of about −80 deg or more can be secured, and the overlap between the voltage waveform Vds and the current waveform Id can be reduced.
Further, under the conditions of Cds = 10 [pF] and RL1 = 50 [Ω], by setting Cs to 4 to 6 [pF], the condition of Xds / Z1 (Re) <2.5 is also satisfied, and high efficiency is achieved. Obtainable.

  In addition, since the second harmonic phase becomes closer to −90 deg when the inductor Ls is as large as possible, in the example where the first capacitor Cds = 10 [pF] and the output load RL1 = 50 [Ω], Ls is 0. It is preferably 8 [nH] or more. In this case, −85 deg or more is ensured as the second harmonic phase (φ2), and the overlap between the voltage waveform and the current waveform can be extremely reduced.

That is, the value of the inductor Ls is set so as to ensure that the second harmonic phase (φ2) is −80 deg or more, preferably −85 deg or more, and the second condition is satisfied so that the condition of Xds / Z1 (Re) <2.5 is also satisfied. By setting the value of the capacitor Cs, a highly efficient class EJ amplifier can be realized while reducing the overlap between the voltage waveform and the current waveform.
For example, 1 [nH] can be adopted as the upper limit of the inductor Ls, but is not particularly limited.

  FIG. 15 shows a voltage / current waveform of the EJ class amplifier 1 in which the second harmonic phase is −90 deg. As is apparent from FIG. 15, the overlap between the voltage waveform Vds and the current waveform Id is smaller than that in FIG. As a result, the maximum efficiency of the EJ class amplifier 1 can be increased by about 9% as compared with the conventional class J amplifier.

  FIG. 16 shows an amplifier 1 according to another configuration. In this amplifier 1, a plurality (two) of field effect transistors Tr1 and Tr2 are connected in series, and capacitive impedance exists as capacitors Cds1 and Cds2 between the drain and source of each field effect transistor Tr1 and Tr2, respectively. is doing.

According to the configuration of FIG. 16, if the capacitances of the capacitors Cds1 and Cds2 are, for example, Cds1 = Cds2 = (Cds in FIG. 14), the capacitance Cds (value as a series body) of the capacitive impedance in FIG. In comparison with the capacitance of Cds in FIG. Therefore, the capacitive impedance (1 / 2πf ₀ Cds) between the drain (Tr1) and the source (Tr2) in FIG. 16 can be increased.
In FIG. 16, it is not necessary that Cds1 = Cds2. Further, points that are not described here are the same as in FIG.

FIG. 17 shows an amplifier 1 according to still another configuration. This amplifier 1 includes a plurality of (three) parallel field effect transistors (Tr1, Tr2, Tr3), capacitors (cds1, cds2, cds3) and inductors (Ls1, Ls2, Ls3) similar to the amplifier 1 shown in FIG. They are connected and configured to operate in parallel. In the amplifier 1, an input is given to the gates of the transistors Tr1, Tr2, Tr3 from a common input terminal Pin. In addition, the outputs P1out, P2out, and P3out from the inductors Ls1, Ls2, and Ls3 are combined into a common output Pout.
A high output can be obtained by operating a plurality of amplifier elements (field effect transistors, capacitors, inductors) in parallel like the amplifier 1.

《Basic mounting technology》
Next, an embodiment of the amplifier viewed from the mounting technology will be described by taking the amplifier 1 shown in FIG. 17 as an example. First, an amplifier as a reference example will be described.
FIG. 18 is a schematic diagram showing a state in which the amplifier 1 shown in FIG. In the figure, the semiconductor chip 201 includes the field effect transistors Tr1, Tr2, Tr3 and the first capacitors Cds1, Cds2, Cds3 of FIG. Three pads 202 made of a conductor are provided on the upper surface of the semiconductor chip 201, which serve as output terminals connected to the drains of the field effect transistors Tr1, Tr2, Tr3, respectively. Each source of the field effect transistors Tr1, Tr2, Tr3 is connected to a common ground side electric circuit (not shown) and can be connected to an external lead wire (not shown).

  A rectangular parallel plate capacitor 203 corresponding to the second capacitor Cs of FIG. 17 is provided beside the semiconductor chip 201, and one electrode 204 made of a conductor is formed on the upper surface thereof. The other (back surface) electrode is connected to a common ground-side electric circuit. One end of each of the three wires 205 corresponding to the inductors Ls1, Ls2, and Ls3 in FIG. 17 is connected to the three pads 202 in the semiconductor chip 201, respectively, and the other ends are all connected to the electrode 204 of the parallel plate capacitor 203. ing. The electrode 204 is electrically connected to the external lead 207 through the wire 206.

In order to realize the EJ class in the amplifier, a series inductor larger than the above-described EJ class condition 1 is required. In the reference example of FIG. 18, in order to obtain a large series inductor,
(A) It is conceivable to use the wire 205 that connects the semiconductor chip 201 and the parallel plate capacitor 203 as an inductor.
Further, in consideration of the above-mentioned EJ class condition 2, it is preferable that the parallel capacitance (Cs) is further small. for that purpose,
(B) It is conceivable to reduce the area of the parallel plate capacitor 203 as much as possible.

On the other hand, the wire 205 needs to have the following three functions.
That is, (i) DC and envelope band low loss power supply, (ii) fundamental band RF signal low loss output, (iii) second harmonic band RF signal cutoff, and having these functions, (Iv) It is important that wire bonding (assembly) and performance extraction (adjustment) are easy.

First, regarding the configuration of (A), since the wire 205 is used as an inductor element, it is necessary to ensure a corresponding length. The predetermined inductance L is
L = 0.4593 × log ₁₀ (D / d) [nH / mm]. . . (6)
It can be expressed as. Here, D is the height in the package base 200, and d is the wire diameter. Equation (6) is for obtaining the inductance of the central conductor of the normal coaxial line. For example, in order to obtain 0.9 [nH], if D = 3 [mm] and d = 20 [μm] (= 0.02 [mm]) from this equation (6), L = 1 [nH / mm].

On the other hand, normally, a plurality of (n number) transistors are provided in parallel on the high-power semiconductor chip 201, and the number of wires is n. If n wires are connected, in order to set the overall inductance value to 0.9 [nH], the inductance value per wire needs to be 0.9 × n [nH].
As a result, the wire length WL is
WL = (0.9 × n) /L=0.9×n [mm]. . . (7)
It becomes. As shown in FIG. 18, when n = 3, WL = 2.7 [mm]. If the number of transistors in parallel is increased, the wire length WL is further increased.

Considering that the width of the semiconductor chip 201 is several mm and the diameter of the wire 205 is only 0.02 mm, the numerical value indicated by the result of the equation (7) is quite long. Moreover, since it is sufficient to have a wire length WL of about 1 mm when it is not necessary to secure inductance with a wire (when it is only necessary to connect), it can be said that the above numerical value is long.
Further, for example, ten wires 205 having a diameter of 0.02 mm are routed by 10 mm, which causes a problem of deformation of the wire 205 due to vibration or the like, and breakage of the joint portion with the pad 202 or the electrode 204. In addition, if the wires 205 are magnetically coupled in order to connect the plurality of wires 205 in parallel, the alternating current is biased, and the wires 205 are melted by the relatively increased alternating current. There is a fear.

  FIG. 19 is a circuit diagram of the amplifier 1 with emphasis on mounting technology. The difference from FIG. 17 is that each of the transistors Tr1, Tr2, Tr3 is common to each of the transistors Tr1, Tr2, Tr3 and is connected in series without providing an inductor corresponding to the transistor 1: 1. This is in that an inductor Ls-s is provided, and the rest is the same as in FIG.

  FIG. 20 is a schematic diagram showing a state in which the amplifier 1 shown in FIG. In the figure, the semiconductor chip 201 includes the field effect transistors Tr1, Tr2, Tr3 and first capacitors Cds1, Cds2, Cds3 of FIG. Three pads 202 made of a conductor are provided on the upper surface of the semiconductor chip 201, which serve as output terminals connected to the drains of the field effect transistors Tr1, Tr2, Tr3, respectively. Each source of the field effect transistors Tr1, Tr2, Tr3 is connected to a common ground side electric circuit (not shown) and can be connected to an external lead wire (not shown).

  A rectangular microstrip substrate 208 is provided next to the semiconductor chip 201, and a horizontally elongated microstrip line 209 made of a conductor is formed on the upper surface thereof. The microstrip line 209 corresponds to the inductor Ls-s in FIG. 19 and is insulated from the ground-side electric circuit by the microstrip substrate 208. One end of each of the three wires 205 is connected to each of the three pads 202 in the semiconductor chip 201, and the other ends are all connected to the vicinity of one end (left end in the figure) of the microstrip line 209. One end of a wire 206 is connected to the vicinity of the other end of the microstrip line 209, and the other end of the wire 206 is connected to an external lead 207.

When the microstrip line 209 is a ribbon inductance, the inductance value is
L = Z ₀ × ML × (ε ^1/2 ) / 300 [nH]. . . (8)
It becomes. Here, Z ₀ is the characteristic impedance, ML is the line length [mm], and ε is the effective dielectric constant of the microstrip substrate 208. For example, if a microstrip line with ε = 10 and Z ₀ = 10 [Ω] is used, ML = 8.5 mm in order to obtain L = 0.9 [nH]. The microstrip line width is 2.5 mm if the substrate thickness is 0.3 mm.

Therefore, if 8.5 mm is ensured as the line length of the microstrip line 209, a desired inductance L (= 0.9 nH) can be obtained. As a result, the three wires 205 are not used as inductors, but only as an electrical path connecting the transistors Tr1, Tr2, Tr3 and the microstrip line 209 to each other for the purpose of internal matching. Therefore, the length of the wire 205 may be minimal, for example, about 1 mm.
Therefore, it is possible to solve the problem of deformation of the wire 205 due to vibration or the like, and breakage of the joint portion between the wire 205 and the pad 202 or the electrode 204. Further, since the magnetic coupling between the wires 205 hardly occurs, the fear of the wire 205 being melted can be eliminated.

  On the other hand, in FIG. 20, the parallel plate capacitor 210 is provided on the microstrip substrate 208. This corresponds to the second capacitor Cs of FIG. One (upper surface) electrode 211 of the capacitor 210 is connected to the conductive portion 212 from the microstrip line 209 and is electrically connected directly to the microstrip line 209.

On the other hand, regarding the configuration of (B) described above, that is, to reduce the area of the parallel plate capacitor 210 as much as possible, it can be as follows.
That is, the capacitance of the parallel plate capacitor 203 is
Cp = ε ₀ × ε × (S / d) [pF]. . . (9)
It is obtained by. Here, ε ₀ is the dielectric constant in vacuum, ε is the relative dielectric constant of the substrate, S is the parallel plate capacitor area, and d is the plate thickness. For example, if Cp = 30 pF, ε = 50, and d is 0.2 mm, S is 13.6 mm ² and can be realized with a size that does not cause a problem in mounting.

Here, in order to reduce Cp, it is conceivable to reduce S. However, in order to obtain Cp of about 4 pF, S becomes 1.8 mm ² , and there is a risk of reducing the connecting force to the microstrip substrate 208 when mounting. Therefore, instead of reducing S, the dielectric constant ε is made smaller than the above value, and the plate thickness d is made larger. That is, from the equation (9), when a capacitance of Cp = 4 pF is formed on the same substrate with ε = 10 and d = 0.3 mm, S = 13.6 mm ² as in the above case, and the mounting Can be realized in a size with no problem. Note that reducing the dielectric constant ε contributes to cost reduction.

  In addition, if the microstrip line 209 as the inductor Ls-s and the parallel plate capacitor 210 as the capacitor Cs are integrally formed on the microstrip substrate 208, the wire connection is made on the microstrip line 209. A wire is not bonded to the capacitor 210. Therefore, even if S is made small, the possibility of causing bonding mistakes can be solved. That is, the problem that wire bonding is impossible or difficult due to the small area is solved, and the configuration is suitable for small capacitor connection.

Next, an embodiment of an amplifier and a microstrip substrate obtained by further improving the above-described amplifier 1 will be described including a manufacturing method. First, the circuit configuration will be described.
《Improved circuit configuration》
FIG. 1 is a circuit diagram showing an amplifier 1 that performs EJ class operation according to the present invention. The amplifier 1 is used, for example, as a power amplifier for wireless communication, and is particularly suitable for communication in the GHz band (for example, about 2 GHz). In the figure, the amplifier 1 is structurally composed of a semiconductor chip 2 and a microstrip substrate 3. A field effect transistor Tr is mounted on the semiconductor chip 2, and its gate G is an input terminal Pin of the amplifier 1. Further, between the drain D and the source S of the field effect transistor Tr, there is a first capacitor Cds that forms a capacitive impedance.

  On the other hand, the microstrip substrate 3 on which the LC circuit is mounted has an inductor Ls connected between the drain D and the output terminal Pout so as to be located on the rear stage side of the first capacitor Cds, and the first via the inductor Ls. And a second capacitor Cs connected in parallel to one capacitor Cds. The inductor Ls and the capacitor Cds are configured by forming a microstrip line on the microstrip substrate 3. The inductance of the inductor Ls and the capacitance of the second capacitor Cs are set to optimum values according to the output impedance ZL of the semiconductor chip 2. The amplifier 1 is connected to a resistor RL as an output load.

The inductor Ls includes a plurality (n) of unit inductors Ls (1), Ls (2), Ls (3),. . . , Ls (n) are connected in parallel to each other. The inductance Ls of the whole inductor Ls as a set of unit inductors is unit inductors Ls (1), Ls (2), Ls (3),. . . , Ls (n) directly represents each inductance,
Ls = 1 / [{1 / Ls (1)} + {1 / Ls (2)} + {1 / Ls (3)} +. . . + {1 / Ls (n)}]. . . (10)
It becomes.

On the other hand, the capacitance Cs includes a plurality (n) of unit capacitor regions Cs (1), Cs (2), Cs (3),. . . , Cs (n) are connected in parallel to each other. Here, the same number n as the number of unit inductor regions is used as the number of unit capacitor regions, but the number may be the same or different.
The total capacitance Cs as an aggregate of unit capacitor regions is represented by unit inductors Cs (1), Cs (2), Cs (3),. . . , Cs (n) represents each inductance as it is,
Cs = Cs (1) + Cs (2) + Cs (3) +. . . + Cs (n). . . (11)
It becomes.

In the inductor Ls as described above, the inductances of the unit inductors may or may not be the same value. In short, it must be composed of multiple elements. In case of equivalence,
Ls (1) = Ls (2) = Ls (3) =. . . = Ls (n) = Lso
Then, the above equation (10) is
Ls = Lso / n. . . (12)
It becomes.

Similarly, in the capacitor Cs as described above, the capacitances of the unit capacitors may or may not be equal to each other. In short, it must be composed of multiple elements. In case of equivalence,
Cs (1) = Cs (2) = Cs (3) =. . . = Cs (n) = Cso
Then, the above equation (11) is
Cs = n · Cso. . . (13)
It becomes.

  The semiconductor chip 2 has various configuration examples other than FIG. FIG. 2 is a circuit diagram of an amplifier 1 having a semiconductor chip 2 according to another configuration example based on the configuration of FIG. The configuration subsequent to the semiconductor chip 2 is the same as that shown in FIG. In FIG. 2, two field effect transistors Tr1 and Tr2 are connected in series with each other. The first capacitors Cds1 and Cds2 as capacitive impedances existing between the drain and source of the field effect transistors Tr1 and Tr2 are also connected in series.

  FIG. 3 is a circuit diagram of an amplifier 1 having a semiconductor chip 2 according to still another configuration example based on the configuration of FIG. The configuration subsequent to the semiconductor chip 2 is the same as that shown in FIG. In FIG. 3, three field effect transistors (Tr1, Tr2, Tr3) and three first capacitors (cds1, cds2, cds3) are respectively connected in parallel and configured to operate in parallel. In this case, the same input is given to the gates of the transistors Tr1, Tr2, Tr3 from the common input terminal Pin. Also, the outputs from the drains of the transistors are combined into one output. According to such a parallel configuration, a higher output can be obtained than the configuration of FIG. Although this is an example in which the number of parallels is 3, any number of parallel numbers can be used as necessary.

《Improved mounting technology》
<< First Embodiment of Microstrip Substrate >>
Next, an improved mounting technique for the amplifier will be described.
FIG. 4 is a schematic diagram showing a state in which the amplifier 1 shown in FIG. In the figure, the semiconductor chip 2 includes the field effect transistors Tr1, Tr2, Tr3 and the first capacitors Cds1, Cds2, Cds3 of FIG. Three pads 21 made of a conductor are provided on the upper surface of the semiconductor chip 2 and serve as output terminals connected to the drains of the field effect transistors Tr1, Tr2, Tr3, respectively. The sources of the field effect transistors Tr1, Tr2, Tr3 are connected to a common ground-side electric circuit (not shown), and can be connected to the microstrip substrate 3 or an external lead wire (not shown). .

  Next to the semiconductor chip 2, a rectangular microstrip substrate 3 is provided, and on its upper surface, a horizontally long conductive portion 31 that forms the inductor Ls and a rectangular island-shaped conductive portion that forms the second capacitor Cs. A portion 32 is formed. The conductive portion 32 constitutes a parallel plate capacitor with the microstrip substrate 3 interposed between the conductive portion 32 and a conductive portion (not shown) of a ground-side electric circuit provided on the back surface. In addition, the conductive portion 32 is connected to the conductive portion 31 via the connection piece 33 and is electrically connected to each other. On the other hand, one end of each of the three wires 5 is connected to each of three pads 21 in the semiconductor chip 2 (connection by bonding, the same applies hereinafter), and the other ends are all connected to the vicinity of one end (left end in the figure) of the conductive portion 31. ing. One end of the wire 6 is connected to the vicinity of the other end of the conductive portion 31, and the other end of the wire 6 is connected to the external lead 7.

  FIG. 5 is an enlarged view showing only the microstrip substrate 3 of FIG. In the figure, the conductive portion 31 constituting the inductor Ls includes a plurality (six in this case) of strip-shaped unit inductor regions 31a arranged on the microstrip substrate 3, and connection pieces that bridge these at both ends. It is comprised by the area | region 31b. For example, the unit inductor region 31a is electrically isolated by cutting off a portion indicated by a circle (dotted line) in the vicinity of both ends with a laser, and does not contribute to the overall inductance. Accordingly, if necessary, the total inductance can be adjusted by cutting off both ends of the unit inductor regions 31a (1 to 5 out of 6 in this case) with a laser.

Specifically, Ls in the above equation (12) is as follows depending on the number of unit inductor regions to be cut in this case.
When not excised: Lso / 6
When excising one: Lso / 5,
When excising two: Lso / 4
When excising three: Lso / 3
When excising four: Lso / 2
When removing 5: Lso
Thus, the inductance of the inductor Ls can be adjusted to six types. Since the inductance of each unit inductor region can be formed with high accuracy, a desired inductance can be configured with high accuracy as a whole.

  On the other hand, the conductive portion 32 constituting the second capacitor Cs includes three unit capacitor regions 32a, 32b, and 32b and a connection piece region 32c that bridges between the unit capacitor regions 32a and 32b. The three unit capacitor regions 32a, 32b, 32b are non-uniform in area, and are constituted by a unit capacitor region 32a having a large area and two unit capacitor regions 32b having a small area. The two unit capacitor regions 32b are electrically isolated by cutting off the connection piece region 32c with a laser and do not contribute to the overall capacitance. Therefore, if one or two of the unit capacitor regions 32b is cut off with a laser as necessary, the overall capacitance can be adjusted.

Specifically, for example, when the capacitance of the unit capacitor region 32a is Cs (1) and each capacitance of the two unit capacitor regions 32b is Cs (2), the total capacitance Cs is expressed by the above-described equation (11), Depending on the number of connection piece regions to be cut,
When not excised: Cs (1) + 2Cs (2)
When excising one piece: Cs (1) + Cs (2)
When excising two: Cs (1)
Thus, the capacitance of the second capacitor Cs can be adjusted to three types. Since the capacitance of the two unit inductor regions 32b can be formed with high accuracy, a desired capacitance can be configured with high accuracy as a whole.

<< Second Embodiment of Microstrip Substrate >>
FIG. 6 is a view showing a microstrip substrate 3 according to the second embodiment. The dimension as an example which shows the magnitude | size of the real thing of each part is described in the figure.
In the figure, the microstrip substrate 3 includes a conductive portion 31 constituting an inductor Ls and a conductive portion 32 constituting a second capacitor Cs. The conductive portion 31 constituting the inductor Ls includes a plurality of (here, ten) strip-shaped unit inductor regions 31a arranged on the microstrip substrate 3, and connection piece regions 31b bridging these at both ends. And is configured in a horizontally long lattice shape as a whole.

  The conductive portion 32 constituting the second capacitor Cs bridges a plurality of (here, ten) rectangular unit capacitor regions 32a arranged in a matrix on the microstrip substrate 3 and these regions. It is comprised by the connection piece area | region 32c. The conductive part 31 constituting the inductor Ls and the conductive part 32 constituting the capacitor Cs are electrically connected to each other via five connection pieces 33.

  The arrangement of the conductive portions 31 and 32 in FIG. 6 is symmetrical with respect to the center line CL in the arrangement direction (vertical direction in the drawing) of the unit inductor regions 31a. As is clear from the comparison with FIG. 5, such an arrangement configuration of the conductive portions can effectively use the entire area of the microstrip substrate 3 to suppress a useless empty area and Since it is symmetrical, there is no bias in the signal path length. As a result, the microstrip substrate can be made compact, and power synthesis is ideally achieved.

  The patterns of the conductive portions 31 and 32 in the microstrip substrate 3 in FIG. 6 are original shapes, and from here, the inductance and capacitance can be adjusted by laser cutting as necessary. FIG. 7 shows a state where both ends of three unit inductor regions 31a from the top and three from the bottom are cut out by the laser. As a result, the six unit inductor regions 31a are electrically isolated and do not contribute to the overall inductance. The overall inductance is determined by the central four unit inductor regions 31a.

  Further, in FIG. 7, of the ten unit capacitor regions 32 a, a connection piece region 32 c (each of the two unit capacitor regions 32 a at the upper right corner and the lower right corner between the adjacent unit capacitor regions 32 a (each of the ten unit capacitor regions 32 a). The state which excised 2 places) is shown. As a result, the two unit capacitor regions 32a are electrically isolated and do not contribute to the overall capacitance. The total capacitance is determined by the remaining eight unit capacitor regions 32a.

  In this way, the inductance of the inductor Ls can be adjusted in multiple stages by selecting the number of unit inductor regions 31a to be laser cut. Since the inductance of each unit inductor region can be formed with high accuracy, a desired inductance can be configured with high accuracy as a whole. Similarly, the capacitance of the second capacitor Cs can be adjusted in multiple stages by selecting the number of unit capacitor regions 32a to be laser cut. Since the capacitance of each unit capacitor region can be formed with high accuracy, a desired inductance can be configured with high accuracy as a whole.

  FIG. 8 is a schematic diagram showing a state in which the microstrip substrate 3 shown in FIG. In the figure, the semiconductor chip 2 includes field effect transistors Tr1 to Tr5 and first capacitors Cds1 to Cds5 when the parallel number of the circuit configuration of FIG. Five pads 21 made of a conductor are provided on the upper surface of the semiconductor chip 2, which serve as output terminals connected to the drains of the field effect transistors Tr1 to Tr5, respectively. Each source of the field effect transistors Tr1 to Tr5 is connected to a common ground-side electric circuit (not shown), and can be connected to the microstrip substrate 3 or an external lead wire (not shown).

  On the other hand, one end of each of the five wires 5 is connected to each of the five pads 21 in the semiconductor chip 2, and the other ends are all connected to the connection piece region 31 b of the conductive portion 31. One end of the wire 6 is connected to one of the unit capacitor regions 32 a of the conductive portion 32, and the other end of the wire 6 is connected to the external lead 7.

<< Third Embodiment of Microstrip Substrate >>
FIG. 9 is a schematic diagram showing a state in which the amplifier 1 having the microstrip substrate 3 according to the third embodiment is housed in the package base 4. As is clear from comparison with FIG. 8, the microstrip substrate 3 in FIG. 9 has the same electrical connection relationship, but the unit inductor region 31a in the arrangement direction of the unit inductor regions 31a (vertical direction in the figure). The arrangement pitch of is expanding. According to such an arrangement, even when the number of parallel semiconductor chips 2 increases and the pads 21 of the semiconductor chip 2 are distributed over a wide range in the arrangement direction of the unit inductor regions 31a, the connection piece regions 31b are formed. Accordingly, it is formed to extend long in the same direction. As a result, the lengths of the plurality of wires 5 can be made the same. Therefore, the losses in the plurality of wires 5 can be made equal to each other.

<< Fourth Embodiment of Microstrip Substrate >>
FIG. 10 is a schematic diagram showing a state in which the amplifier 1 having the microstrip substrate 3 according to the fourth embodiment is housed in the package base 4. In FIG. 10, the microstrip substrate 3 includes a conductive portion 31 that forms an inductor Ls and a conductive portion 32 that forms a second capacitor Cs. The conductive portion 31 constituting the inductor Ls has substantially the same configuration as that shown in FIGS. 7 and 8, but the right connection piece region 31 b is thicker for bonding the wire 6.

  In addition, the conductive portion 32 constituting the second capacitor Cs is connected to both ends of the connection piece region 31b via the connection piece 33 in parallel with the longitudinal direction of the unit inductor region 31a and the conductive portion constituting the inductor Ls. 31 are arranged so as to be located outside the entire region in the arrangement direction (vertical direction in the figure) of the unit inductor regions 31a. In the illustrated example, the unit capacitor region 32a at the left end is separated from the other unit capacitor regions 32a and does not contribute to the overall capacitance.

  As is clear from comparison with FIG. 8, the arrangement configuration of the conductive portions 31 and 32 in FIG. 10 is reduced in size in the longitudinal direction (lateral direction in the drawing) of the unit inductor region 31a. Therefore, the package base 4 of the amplifier 1 can be made compact.

<< Fifth Embodiment of Microstrip Substrate >>
FIG. 11 is a schematic diagram showing a state in which the amplifier 1 having the microstrip substrate 3 according to the fifth embodiment is housed in the package base 4. In FIG. 11, the microstrip substrate 3 is different from the microstrip substrate 3 of FIG. 10 in that a plurality of (here, five) slits 32d are formed in the connection piece region 31b of the conductive portion 31 constituting the inductor Ls. The point is that it is configured in a comb shape as a whole. By forming such a slit 32d, when the wire 6 is bonded between the slits, the slit serves as a scale, and the inductance can be changed with good reproducibility. Therefore, fine adjustment with good reproducibility of inductance is possible depending on where the end of the wire is bonded. In this case, it is also possible to perform finer inductance adjustment using a plurality of wires 6. Similarly, the left connection piece region 31b may have a comb shape by providing slits.

《Supplementary items regarding each embodiment》
For example, in the second embodiment, the unit inductor region 31a and the connection piece region 31b are connected to each other in advance as the original conductive portion (FIG. 6), and a manufacturing method that performs laser cutting as necessary. A desired pattern (FIG. 7) was formed. The relationship between the unit capacitor region 32a and the connection piece region 32c is also the same.

This is the same in other embodiments, and more comprehensively speaking, in such a manufacturing method, m unit impedance regions (31a, 32a) are arranged on a substrate, A first step of creating an original conductive part in which unit impedance regions are bridged by connection piece regions (31b, 32c), and (mn) unit impedance regions (31a, For 32a), both ends of the connection piece region connected to each of the unit impedance regions or the unit impedance region in the vicinity of the connection piece region are excised with a laser to electrically isolate (mn) unit impedance regions. And a second step in which the other n unit impedance regions are electrically connected to each other.
However, it is also possible to form a similar result as a result of a completely reverse procedure.

  That is, the unit inductor region 31a and the connection piece region 31b are separated from each other in advance as a prototype conductive portion (FIG. 12), and if necessary, a desired pattern ( FIG. 13) can be formed. In this case, the black part in FIG. 13 is a place where vapor deposition is performed. As for the unit capacitor region 32a, the portion where the vapor deposition is performed becomes the connection piece region 32c.

  This also applies to the other embodiments. More generally, in the method of manufacturing the microstrip substrate constituting the inductance, m strip-shaped unit inductor regions (31a) are arranged on the substrate. And a first step of creating an original conductive part having a connection piece region (31b) extending in a direction orthogonal to the longitudinal direction of the unit inductor region with a gap between both ends thereof, and n of m or less With respect to the unit inductor regions, the gaps at both ends of the unit inductor regions are filled with the conductive portion by vapor deposition, so that the n unit inductor regions are electrically connected to each other, and the other (mn) pieces And a second step of electrically isolating the unit inductor region.

  In addition, the manufacturing method of the microstrip substrate constituting the capacitance creates the original conductive portion in which m unit capacitor regions (32a) are arranged on the substrate and all the unit capacitor regions are insulated from each other. Forming a connection piece region (32c) that bridges each region by vapor deposition for the first unit step and n unit capacitor regions of m or less, and the n unit capacitor regions are electrically connected to each other. And a second step of electrically isolating the other (mn) unit capacitor regions.

  As described above, a unit region (unit inductor region) can be obtained by either cutting off a portion connected in advance as necessary, or connecting a portion separated in advance as necessary. -With a basic configuration in which the unit capacitor area is prepared as an existing part, such a microstrip substrate has a high reproducibility (for example, who, when, where, and how many times, a desired inductance / capacitance can be obtained). Obtained).

In each of the above embodiments, it is preferable that a protective film made of an insulating material is applied in advance in addition to the portion to be excised by laser.
In this case, the portion where the protective film is applied can prevent a pattern short circuit that may occur due to the metal splash adhering to the conductive portion.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined not by the above-mentioned meaning but by the scope of claims for patent, and is intended to include all modifications within the scope and meaning equivalent to the scope of claims for patent.

FIG. 3 is a circuit diagram (improved type) showing an amplifier performing EJ-class operation according to the present invention. It is a circuit diagram (improvement type) of an amplifier having a semiconductor chip according to another configuration example. FIG. 10 is a circuit diagram (an improved type) of an amplifier having a semiconductor chip according to still another configuration example. 4 is a schematic diagram showing a state where the amplifier shown in FIG. 3 is housed in a package base. It is a figure which expands and shows only the microstrip board | substrate of FIG. It is a figure which shows the microstrip board | substrate which concerns on 2nd Embodiment. With respect to the microstrip substrate of FIG. 6, both ends of each of six unit inductor regions are cut off by laser, and two units of an upper right corner and a lower right corner of the ten unit capacitor regions are cut. It is a figure which shows the state which cut away the connection piece area | region (each 2 places) between the adjacent unit capacitor area | regions about a capacitor area | region. 8 is a schematic diagram showing a state in which the microstrip substrate shown in FIG. 7 is housed in a package base. It is the schematic which shows the state which accommodated the amplifier which has a microstrip board | substrate concerning 3rd Embodiment in the package base. It is the schematic which shows the state which accommodated the amplifier which has a microstrip board | substrate concerning 4th Embodiment in the package base. 10 is a schematic view showing a state in which an amplifier having a microstrip substrate according to a fifth embodiment is housed in a package base. It is a figure which shows the microstrip board | substrate which has an original electroconductive part different from FIG. 6 for manufacturing the microstrip board | substrate shown in FIG. It is a figure which shows the state which manufactured the thing substantially the same as the microstrip board | substrate shown in FIG. 7 from the microstrip board | substrate which has the original electroconductive part of FIG. It is a circuit diagram (basic type) which shows an EJ class amplifier which improved a J class amplifier. It is a voltage-current waveform diagram of an EJ class amplifier. It is a circuit diagram (basic type) of another EJ class amplifier. It is a circuit diagram (basic type) of still another EJ class amplifier. 18 is a schematic diagram illustrating a state where the amplifier illustrated in FIG. 17 is housed in a package base. It is a circuit diagram (basic type) of an amplifier with an emphasis on mounting technology. 20 is a schematic diagram illustrating a state where the amplifier illustrated in FIG. 19 is housed in a package base. It is a circuit diagram of the conventional class J amplifier. It is a voltage-current waveform diagram of a conventional class J amplifier.

Explanation of symbols

1: Amplifier, 2: Semiconductor chip, 3: Microstrip substrate, 4: Package base, 5, 6: Wire, 7: External lead, 21: Pad, 31: Conductive part, 31a: Unit inductor region, 31b: Connection piece Region, 32: conductive portion, 32a, 32b: unit capacitor region, 32c: connection piece region, 33: connection piece, Tr, Tr1 to Tr3: field effect transistor, Cds, Cds1 to Cds3: first capacitor (capacitive impedance) , Ls: inductor / inductance, Ls (1) to Ls (n): unit inductor / inductance, Cs: second capacitor / capacitance, Cs (1) to Cs (n): unit capacitor / capacitance, RL: resistance, 200 : Package base, 201: Semiconductor die chip, 202: Pad, 203: Parallel plate core Densa, 204: Electrode, 205: Wire, 206: Wire, 207: External lead, 208: Microstrip substrate, 209: Microstrip line, 210: Parallel plate capacitor, 211: Electrode, 212: Conductive part, Ls1, Ls2, Ls3, Ls-s; Inductor

Claims (5)

A field effect transistor having a capacitive impedance between the drain and source;
An inductor connected to the drain so as to be positioned behind the capacitive impedance, and a capacitor connected in parallel to the capacitive impedance via the inductor, a conductive portion on the surface of the substrate made of an insulator Comprising a microstrip substrate configured by forming,
The inductor is an amplifier whose impedance at the fundamental frequency is set to a value equal to or higher than the impedance of the capacitive impedance unit,
The conductive part constituting the inductor is:
A plurality of unit inductor regions arranged on the substrate;
An amplifier comprising: a connection piece region that bridges a part or all of the plurality of unit inductor regions at both ends thereof.   The conductive portion constituting the capacitor includes a plurality of unit capacitor regions arranged on the substrate, and a connection piece region that bridges between the regions of some or all of the plurality of unit capacitor regions. The amplifier according to claim 1.   The amplifier according to claim 2, wherein all the conductive portions are formed symmetrically with respect to a center line in the arrangement direction of the unit inductor regions.   4. The amplifier according to claim 2, wherein the unit capacitor regions are arranged outside the region occupied by all the unit inductor regions in the arrangement direction of the unit inductor regions. 5. A field effect transistor having a capacitive impedance between the drain and source;
An inductor connected to the drain so as to be positioned behind the capacitive impedance, and a capacitor connected in parallel to the capacitive impedance via the inductor, a conductive portion on the surface of the substrate made of an insulator Comprising a microstrip substrate configured by forming,
The inductor is an amplifier whose impedance at the fundamental frequency is set to a value equal to or higher than the impedance of the capacitive impedance unit,
The conductive part constituting the capacitor is:
A plurality of unit capacitor regions arranged on the substrate;
An amplifier comprising: a connection piece region bridging between each region for a part or all of the plurality of unit capacitor regions.

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