JP2624370B2 - High frequency integrated circuit - Google Patents
High frequency integrated circuitInfo
- Publication number
- JP2624370B2 JP2624370B2 JP2304703A JP30470390A JP2624370B2 JP 2624370 B2 JP2624370 B2 JP 2624370B2 JP 2304703 A JP2304703 A JP 2304703A JP 30470390 A JP30470390 A JP 30470390A JP 2624370 B2 JP2624370 B2 JP 2624370B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- integrated circuit
- chip
- mmic
- frequency transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/1423—Monolithic Microwave Integrated Circuit [MMIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Waveguides (AREA)
- Microwave Amplifiers (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、高性能化を図った高周波帯の集積回路に
関するものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency integrated circuit with high performance.
〔従来の技術〕 以下、高周波集積回路として、モノリシックマイクロ
波集積回路増幅器（MMIC増幅器）を例にとって説明す
る。[Prior Art] Hereinafter, a monolithic microwave integrated circuit amplifier (MMIC amplifier) will be described as an example of a high-frequency integrated circuit.
第２図は従来のMMIC増幅器の一例を示す平面図であ
る。FIG. 2 is a plan view showing an example of a conventional MMIC amplifier.
図において、１はMMICチップ、３は高周波トランジス
タ、４はコンデンサ、６は高周波トランジスタ３の入
力，出力インピーダンス整合回路である。なお、高周波
トランジスタの電源バイアス印加回路の図示は省略して
いる。In the figure, 1 is an MMIC chip, 3 is a high frequency transistor, 4 is a capacitor, and 6 is an input / output impedance matching circuit of the high frequency transistor 3. The illustration of the power supply bias application circuit of the high-frequency transistor is omitted.
次に動作について説明する。 Next, the operation will be described.
MMICチップ１に印加された入力信号は、入力側の整合
回路６を通して高周波トランジスタ３に印加されて、増
幅されさらに整合回路６と直流阻止用コンデンサ４を介
して次の増幅段に達し、同様に増幅され、出力側の整合
回路６より出力される。The input signal applied to the MMIC chip 1 is applied to the high-frequency transistor 3 through a matching circuit 6 on the input side, is amplified, and reaches the next amplification stage via the matching circuit 6 and the DC blocking capacitor 4. The signal is amplified and output from the matching circuit 6 on the output side.
従来のMMIC増幅器は以上のように構成されているの
で、要求される特性によってはMMIC増幅器での実現が困
難となる場合があった。例えば、低雑音特性が必要な増
幅器では、MMICチップ内の高周波トランジスタ３の特性
を超低雑音にしなけらばならず、技術的に困難であっ
た。Since the conventional MMIC amplifier is configured as described above, it may be difficult to realize the MMIC amplifier depending on required characteristics. For example, in an amplifier that requires low noise characteristics, the characteristics of the high-frequency transistor 3 in the MMIC chip must be extremely low noise, which is technically difficult.
対して個別の高周波トランジスタは、超低雑音特性に
適した素子構造に最適化されており、MMIC増幅器に使用
されている高周波トランジスタ３より特性が優れてい
る。このため、第３図に示したような、高周波トランジ
スタチップ２とMMICチップ１を用いたハイブリッドIC構
成の増幅器モジュールが、低雑音特性を得る手段として
採用されていた。即ち、接地金属板８の上に、アルミナ
セラミック板などのマイクロ波回路基板９の上に形成さ
れた整合回路６を高周波トランジスタチップ２の入，出
力側に設け、さらに次増幅段のMMICチップ１とボンディ
ングワイヤ７で接続した構造である。On the other hand, individual high-frequency transistors are optimized for an element structure suitable for ultra-low noise characteristics, and have better characteristics than the high-frequency transistor 3 used in the MMIC amplifier. Therefore, an amplifier module having a hybrid IC configuration using the high-frequency transistor chip 2 and the MMIC chip 1 as shown in FIG. 3 has been adopted as a means for obtaining low noise characteristics. That is, a matching circuit 6 formed on a microwave circuit board 9 such as an alumina ceramic plate is provided on the input and output sides of the high-frequency transistor chip 2 on the ground metal plate 8, and the MMIC chip 1 of the next amplification stage is further provided. And a bonding wire 7.
しかし以上のような構成の増幅器では、組立工程が複
雑であること、マイクロ波回路基板９の形状が大きくな
ること、及び組立上の位置精度バラツキによる特性変動
が生じるなどの問題があった。However, the amplifier having the above-described configuration has problems such as a complicated assembling process, an increase in the size of the microwave circuit board 9, and variations in characteristics due to variations in positional accuracy in assembling.
この発明は上記のような問題点を解消する為になされ
たもので、組立工程が複雑でなく且つ低雑音特性を備え
た高周波集積回路を得ることを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to obtain a high-frequency integrated circuit having a low-noise characteristic without a complicated assembling process.
この発明に係る高周波集積回路は、高周波集積回路上
に個別の高周波トランジスタチップを装着し、高周波集
積回路上の整合回路とボンディングワイヤで電気的に接
続し、組み合わせて動作させるようにしたものである。A high-frequency integrated circuit according to the present invention has individual high-frequency transistor chips mounted on the high-frequency integrated circuit, is electrically connected to a matching circuit on the high-frequency integrated circuit by bonding wires, and is operated in combination. .
この発明における高周波集積回路は、低雑音特性のよ
い高周波トランジスタチップを高周波集積回路と共に使
用することで、高周波集積回路のチップ寸法を小型に保
ったまま、低雑音特性面での性能を向上させることがで
きる。The high-frequency integrated circuit according to the present invention uses a high-frequency transistor chip having good low-noise characteristics together with a high-frequency integrated circuit to improve performance in terms of low-noise characteristics while keeping the chip size of the high-frequency integrated circuit small. Can be.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例によるMMIC増幅器チップを
示す平面図であり、図において、１はMMICチップ、２は
個別高周波トランジスタチップ、３はMMIC1のトランジ
スタパターン、４は直流阻止用コンデンサ、５は高周波
トランジスタチップ２の接地用パターン、６は個別高周
波トランジスタチップ２及びMMIC1の高周波トランジス
タパターン３の入力，出力部分に設けた整合回路パター
ン、７は接続用ボンディングワイヤである。FIG. 1 is a plan view showing an MMIC amplifier chip according to an embodiment of the present invention, in which 1 is an MMIC chip, 2 is an individual high-frequency transistor chip, 3 is a transistor pattern of MMIC1, 4 is a DC blocking capacitor, Reference numeral 5 denotes a grounding pattern of the high-frequency transistor chip 2, 6 denotes a matching circuit pattern provided on the input and output portions of the individual high-frequency transistor chip 2 and the high-frequency transistor pattern 3 of the MMIC 1, and 7 denotes a bonding wire for connection.
次に作用について説明する。 Next, the operation will be described.
MMICチップ１の一部分に高周波トランジスタチップ２
の接地用パターン５を設けると共に、その入力，出力イ
ンピーダンス整合回路６をMMICチップ１上に設け、高周
波トランジスタチップ２を上記接地パターン５上に接着
した後、整合回路６と接続用ボンディングワイヤ７によ
り、電気的に接続する。High frequency transistor chip 2 as part of MMIC chip 1
And the input / output impedance matching circuit 6 is provided on the MMIC chip 1 and the high-frequency transistor chip 2 is adhered on the ground pattern 5, and then the matching circuit 6 and the bonding wire 7 for connection are used. , Electrical connection.
このような本実施例では、MMICチップ１上に高周波ト
ランジスタパターン３の他に、個別の高周波トランジス
タチップ２を装着し、ボンディングワイヤ７でそのトラ
ンジスタチップ２の入力，出力部分に設けた入力，出力
インピーダンス整合回路６と接続したので、低雑音特性
の面で、高周波トランジスタチップ２とMMICチップ１と
をハイブリッドIC構成で用いた第３図の増幅器と同等の
性能を実現でき、また、高周波トランジスタチップ２の
入力，出力インピーダンス整合回路６をMMICチップ１上
に設けたので、パターン精度よく整合回路６を形成可能
となり、低雑音特性面でのバラツキを減少させることが
でき、かつ回路を小型にできる。In this embodiment, in addition to the high-frequency transistor pattern 3, an individual high-frequency transistor chip 2 is mounted on the MMIC chip 1, and the input and output provided on the input and output portions of the transistor chip 2 by bonding wires 7. Since the high frequency transistor chip 2 and the MMIC chip 1 are connected to the impedance matching circuit 6, the same performance as the amplifier of FIG. 3 using the high frequency transistor chip 2 and the MMIC chip 1 in a hybrid IC configuration can be realized. Since the input / output impedance matching circuit 6 is provided on the MMIC chip 1, the matching circuit 6 can be formed with high pattern accuracy, the variation in the low noise characteristic can be reduced, and the circuit can be downsized. .
なお上記実施例ではMMIC増幅器について説明したが、
本発明はこれに限定されるものでなく、他の高周波集積
回路であってもよく、上記と同様の効果を奏する。Although the above embodiment has described the MMIC amplifier,
The present invention is not limited to this, but may be another high-frequency integrated circuit, and has the same effects as described above.
以上のようにこの発明によれば、高周波集積回路基板
上に低雑音特性の優れた高周波トランジスタチップを装
着し、MMIC部分と組み合わせて使用するようにしたの
で、小型で特性のよい高周波集積回路が得られる効果が
ある。As described above, according to the present invention, a high-frequency integrated circuit board is mounted with a high-frequency transistor chip having excellent low-noise characteristics, and is used in combination with the MMIC portion. There is an effect that can be obtained.
第１図はこの発明の一実施例によるMMIC増幅器のチップ
パターンを示す平面図、第２図は従来のMMIC増幅器のチ
ップパターンを示す平面図、第３図は従来のMMIC増幅器
と高周波トランジスタチップのハイブリッドICの構成例
を示す平面図である。 図において、１はMMICチップ、２は高周波トランジスタ
チップ、３は高周波トランジスタパターン、４はコンデ
ンサパターン、５は接地パターン、６は整合回路パター
ン、７はボンディングワイヤ、８は接地金属板、９はマ
イクロ波回路基板である。 なお図中、同一符号は同一又は相当部分を示す。FIG. 1 is a plan view showing a chip pattern of an MMIC amplifier according to an embodiment of the present invention, FIG. 2 is a plan view showing a chip pattern of a conventional MMIC amplifier, and FIG. FIG. 2 is a plan view illustrating a configuration example of a hybrid IC. In the figure, 1 is an MMIC chip, 2 is a high-frequency transistor chip, 3 is a high-frequency transistor pattern, 4 is a capacitor pattern, 5 is a ground pattern, 6 is a matching circuit pattern, 7 is a bonding wire, 8 is a ground metal plate, and 9 is a micro Wave circuit board. In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (1)
コンデンサなどの電気回路部品を半導体基板上に集積形
成した高周波集積回路において、 該高周波集積回路の一部分に積載した他の高周波トラン
ジスタチップと、 上記基板上の該高周波トランジスタチップの入力及び出
力部分に設けたインピーダンス整合回路と、 該両者間を電気的に接続するボンディングワイヤとを備
えたことを特徴とする高周波集積回路。A high-frequency transistor and a high-frequency transmission line;
In a high-frequency integrated circuit in which electric circuit components such as capacitors are formed on a semiconductor substrate, another high-frequency transistor chip mounted on a part of the high-frequency integrated circuit and input and output portions of the high-frequency transistor chip on the substrate are provided. A high-frequency integrated circuit, comprising: an impedance matching circuit; and a bonding wire for electrically connecting the two.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2304703A JP2624370B2 (en) | 1990-11-09 | 1990-11-09 | High frequency integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2304703A JP2624370B2 (en) | 1990-11-09 | 1990-11-09 | High frequency integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04176201A JPH04176201A (en) | 1992-06-23 |
| JP2624370B2 true JP2624370B2 (en) | 1997-06-25 |
Family
ID=17936202
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2304703A Expired - Fee Related JP2624370B2 (en) | 1990-11-09 | 1990-11-09 | High frequency integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2624370B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015061278A (en) * | 2013-09-20 | 2015-03-30 | 住友電工デバイス・イノベーション株式会社 | Signal transmission line |
-
1990
- 1990-11-09 JP JP2304703A patent/JP2624370B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04176201A (en) | 1992-06-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |