JPH04176201A - High-frequency integrated circuit - Google Patents
High-frequency integrated circuitInfo
- Publication number
- JPH04176201A JPH04176201A JP2304703A JP30470390A JPH04176201A JP H04176201 A JPH04176201 A JP H04176201A JP 2304703 A JP2304703 A JP 2304703A JP 30470390 A JP30470390 A JP 30470390A JP H04176201 A JPH04176201 A JP H04176201A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- high frequency
- integrated circuit
- mmic
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 239000006185 dispersion Substances 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 230000003321 amplification Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/1423—Monolithic Microwave Integrated Circuit [MMIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、高性能化を図った高周波帯の集積回路に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-frequency integrated circuit with improved performance.
以下、高周波集積回路として、モノリシックマイクロ波
集積回路増幅器（ＭＭＴ Ｃ増幅器）を例にとって説明
する。Hereinafter, a monolithic microwave integrated circuit amplifier (MMT C amplifier) will be explained as an example of a high frequency integrated circuit.
第２図は従来のＭＭＩＣ増幅器の一例を示す平面図であ
る。FIG. 2 is a plan view showing an example of a conventional MMIC amplifier.
図において、ｌはＭＭＩＣチップ、３は高周波トランジ
スタ、４はコンデンサ、６は高周波トランジスタ３の入
力、出力インピーダンス整合回路である。なお、高周波
トランジスタの電源バイアス印加回路の図示は省略して
いる。In the figure, 1 is an MMIC chip, 3 is a high frequency transistor, 4 is a capacitor, and 6 is an input and output impedance matching circuit of the high frequency transistor 3. Note that the illustration of the power supply bias application circuit for the high-frequency transistor is omitted.
次に動作について説明する。Next, the operation will be explained.
ＭＭＩＣチップ１に印加された入力信号は、入力側の整
合回路６を通して高周波トランジスタ３に印加されて、
増幅されさらに整合回路６と直流阻止用コンデンサ４を
介して次の増幅段に達し、同様に増幅され、出力側の整
合回路６より出力される。The input signal applied to the MMIC chip 1 is applied to the high frequency transistor 3 through the matching circuit 6 on the input side.
The signal is amplified and further reaches the next amplification stage via the matching circuit 6 and the DC blocking capacitor 4, where it is similarly amplified and output from the matching circuit 6 on the output side.
従来のＭＭＩＣ増幅器は以上のように構成されているの
で、要求される特性によってはＭＭＩＣ増幅器での実現
が困難となる場合があった。例えば、低雑音特性か必要
な増幅器ては、ＭＭＩ Ｃチップ内の高周波ｌ・ランシ
スタ３の特性を超低雑音にしなければならず、技術的に
困難であった。Since conventional MMIC amplifiers are configured as described above, depending on the required characteristics, it may be difficult to realize them with the MMIC amplifier. For example, in order to create an amplifier that requires low noise characteristics, the high frequency lance transistor 3 in the MMIC chip must have extremely low noise characteristics, which is technically difficult.
対して個別の高周波トランジスタは、超低雑音特性に適
した素子構造に最適化されており、ＭＭＩＣ増幅器に使
用されている高周波トランジスタ３より特性か優れてい
る。このため、第３図に示したような、高周波Ｉ・ラン
ジスタデツブ２とＭＭＩＣチップｌを用いたハイブリッ
ドＩＣ構成の増幅器モジコールか、低雑音特性を得る手
段として採用されていた。即ち、接地金属板８の七に、
アルミナセラミック板などのマイクロ波回路基板９の」
−に形成された整合回路６を高周波トランジスタチップ
２の人、出力側に設け、さらに次増幅段のＭＭＩ Ｃチ
ップ１とボンディングワイヤ７て接続した構造である。On the other hand, the individual high-frequency transistors are optimized to have an element structure suitable for ultra-low noise characteristics, and have better characteristics than the high-frequency transistors 3 used in the MMIC amplifier. For this reason, as a means of obtaining low noise characteristics, an amplifier module having a hybrid IC configuration using a high frequency I/transistor block 2 and an MMIC chip I, as shown in FIG. 3, has been adopted. That is, in the seventh part of the ground metal plate 8,
Microwave circuit board 9 such as alumina ceramic board
- is provided on the output side of the high frequency transistor chip 2, and is further connected to the MMIC chip 1 of the next amplification stage by a bonding wire 7.
しかし以上のような構成の増幅器では、組立工程が複雑
であること、マイクロ波回路基板９の形状か大きくなる
こと、及び組立上の位置精度ハラツギによる特性変動か
生じるなどの問題があった。However, the amplifier with the above configuration has problems such as a complicated assembly process, an increase in the size of the microwave circuit board 9, and variations in characteristics due to positional accuracy variations during assembly.
この発明は上記のような問題点を解消する為になされた
もので、組立工程が複雑でなく且つ低雑音特性を備えた
高周波集積回路を得ることを目的とする。This invention was made to solve the above-mentioned problems, and aims to provide a high-frequency integrated circuit that does not require a complicated assembly process and has low noise characteristics.
この発明に係る高周波集積回路は、高周波集積回路」二
に個別の高周波トランジスタチップを装着し、高周波集
積回路」二の整合回路とホンディングワイヤで電気的に
接続し、組み合オっせて動作させるようにしたものであ
る。The high-frequency integrated circuit according to the present invention has individual high-frequency transistor chips mounted on the high-frequency integrated circuit "2" and is electrically connected to the matching circuit of the high-frequency integrated circuit "2" by a bonding wire, and operates in combination. It was designed so that
この発明における高周波集積回路は、低雑音特性のよい
高周波トランジスタチップを高周波集積回路と共に使用
することで、高周波集積回路のチップ寸法を小型に保っ
たまま、低雑音特性面での性能を向上させることができ
る。The high-frequency integrated circuit of the present invention improves performance in terms of low-noise characteristics while keeping the chip size of the high-frequency integrated circuit small by using a high-frequency transistor chip with good low-noise characteristics together with the high-frequency integrated circuit. I can do it.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例によるＭＭＩＣ増幅器チップ
を示す平面図であり、図において、１はＭＭＩ Ｃチッ
プ、２は個別高周波トランジスタデツプ、３はＭＭＩＣ
Ｉのトランジスタパターン、４は直流阻止用コンデンサ
、５は高周波トランジスタチップ２の接地用パターン、
６は個別高周波１ヘランジスタチツプ２及びＭＭＩＣＩ
の高周波トランジスタパターン３の入力、出力部分に設
けた整合回路パターン、７は接続用ボンデインクワイヤ
である。FIG. 1 is a plan view showing an MMIC amplifier chip according to an embodiment of the present invention. In the figure, 1 is an MMIC chip, 2 is an individual high frequency transistor depth, and 3 is an MMIC amplifier chip.
4 is a DC blocking capacitor, 5 is a grounding pattern for the high frequency transistor chip 2,
6 is an individual high frequency 1 transistor chip 2 and MMICI
A matching circuit pattern is provided at the input and output portions of the high frequency transistor pattern 3, and 7 is a bonding wire for connection.
次に作用について説明する。Next, the effect will be explained.
ＭＭＴ Ｃチップ１の一部分に高周波ｌ・ランジスタデ
ツブ２の接地用パターン５を設けると共に、その入力、
出力インピーダンス整合回路６をＭＭＩＣチップｌ」二
に設け、高周波トランジスタチップ２を上記接地パター
ン５上に接着した後、整合回路６と接続用ボンディング
ワイヤ７により、電気的に接続する。In addition to providing a grounding pattern 5 for the high frequency l/transistor block 2 in a part of the MMT C chip 1, its input,
An output impedance matching circuit 6 is provided on the MMIC chip 1''2, and after the high frequency transistor chip 2 is bonded onto the ground pattern 5, the matching circuit 6 and the connecting bonding wire 7 are used to electrically connect.
このような本実施例では、ＭＭＩＣチップ１上に高周波
トランジスタパターン３の他に、個別の高周波トランジ
スタチップ２を装着し、ボンディングワイヤ７でそのト
ランジスタチップ２の入力。In this embodiment, in addition to the high frequency transistor pattern 3, an individual high frequency transistor chip 2 is mounted on the MMIC chip 1, and the bonding wire 7 is used to connect the input of the transistor chip 2.
出力部分に設けた入力、出力インピーダンス整合回路６
と接続したので、低雑音特性の而で、高周波ｌ・ランジ
スタデツブ２とＭＭＩＣチップ１とをハイブリッドＩＣ
構成で用いた第３図の増幅器ど同等の性能を実現でき、
また、高周波トランジスタチップ２の入力、出力インピ
ーダンス整合回路６をＭＭＩＣチップ１上に設けたので
、パターン精度よく整合回路６を形成可能となり、低雑
音特性面でのバラツキを減少させることができ、かつ回
路を小型にてきる。Input and output impedance matching circuit 6 provided in the output section
Because of its low noise characteristics, the high frequency l/transistor block 2 and the MMIC chip 1 can be connected to a hybrid IC.
It can achieve the same performance as the amplifier shown in Figure 3 used in the configuration,
Furthermore, since the input and output impedance matching circuits 6 of the high-frequency transistor chip 2 are provided on the MMIC chip 1, it is possible to form the matching circuit 6 with high pattern accuracy, and variations in low noise characteristics can be reduced. The circuit can be made smaller.
なお上記実施例ではＭＭＩＣ増幅器について説明したが
、本発明はこれに限定されるものでなく、他の高周波集
積回路であってもよく、」１記と同様の効果を奏する。In the above embodiment, an MMIC amplifier has been described, but the present invention is not limited to this, and other high frequency integrated circuits may be used, and the same effects as described in item 1 can be obtained.
以上のようにこの発明によれば、高周波集積回路基板上
に低雑音特性の優れた高周波ｌ・ランジスタデツブを装
着し、ＭＭＩ Ｃ部分と組み合わせて使用するようにし
たので、小型で特性のよい高周波集積回路が得られる効
果かある。As described above, according to the present invention, a high frequency l/transistor block with excellent low noise characteristics is mounted on a high frequency integrated circuit board and is used in combination with the MMI C part. This may be due to the benefits of high-frequency integrated circuits.
第１図はこの発明の一実施例によるＭＭＩ Ｃ増幅器の
チップパターンを示す平面図、第２図は従来のＭＭＩＣ
増幅器のチップパターンを示す平面図、第３図は従来の
ＭＭＩ Ｃ増幅器と高周波トランジスタチップのハイブ
リッドＩＣの構成例を示す平面図である。
図において、１はＭＭＩ Ｃチップ、２は高周波）・ラ
ンジスタチップ、３は高周波トランジスタパターン、４
はコンデンサパターン、５は接地パターン、６は整合回
路パターン、７はボンディングワイヤ、８は接地金属板
、９はマイクロ波回路基板である。
なお図中、同一符号は同−又は相当部分を示す。FIG. 1 is a plan view showing a chip pattern of an MMIC amplifier according to an embodiment of the present invention, and FIG. 2 is a plan view showing a chip pattern of a conventional MMIC amplifier.
FIG. 3 is a plan view showing a chip pattern of an amplifier, and FIG. 3 is a plan view showing a configuration example of a hybrid IC of a conventional MMIC amplifier and a high frequency transistor chip. In the figure, 1 is an MMI C chip, 2 is a high frequency transistor chip, 3 is a high frequency transistor pattern, and 4 is a high frequency transistor pattern.
5 is a capacitor pattern, 5 is a grounding pattern, 6 is a matching circuit pattern, 7 is a bonding wire, 8 is a grounding metal plate, and 9 is a microwave circuit board. In the drawings, the same reference numerals indicate the same or equivalent parts.
Claims (1)
ンサなどの電気回路部品を半導体基板上に集積形成した
高周波集積回路において、 該高周波集積回路の一部分に積載した他の高周波トラン
ジスタチップと、 上記基板上の該高周波トランジスタチップの入力及び出
力部分に設けたインピーダンス整合回路と、 該両者間を電気的に接続するボンディングワイヤとを備
えたことを特徴とする高周波集積回路。(1) In a high-frequency integrated circuit in which electric circuit components such as high-frequency transistors, high-frequency transmission lines, and capacitors are integrated and formed on a semiconductor substrate, other high-frequency transistor chips mounted on a part of the high-frequency integrated circuit and A high-frequency integrated circuit comprising: an impedance matching circuit provided at the input and output portions of a high-frequency transistor chip; and a bonding wire that electrically connects the two.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2304703A JP2624370B2 (en) | 1990-11-09 | 1990-11-09 | High frequency integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2304703A JP2624370B2 (en) | 1990-11-09 | 1990-11-09 | High frequency integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04176201A true JPH04176201A (en) | 1992-06-23 |
| JP2624370B2 JP2624370B2 (en) | 1997-06-25 |
Family
ID=17936202
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2304703A Expired - Fee Related JP2624370B2 (en) | 1990-11-09 | 1990-11-09 | High frequency integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2624370B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015061278A (en) * | 2013-09-20 | 2015-03-30 | 住友電工デバイス・イノベーション株式会社 | Signal transmission line |
-
1990
- 1990-11-09 JP JP2304703A patent/JP2624370B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015061278A (en) * | 2013-09-20 | 2015-03-30 | 住友電工デバイス・イノベーション株式会社 | Signal transmission line |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2624370B2 (en) | 1997-06-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |