JP2003078102A - Flip-chip amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-stage flip-chip amplifier which is small in size and inexpensive. SOLUTION: A DC cut capacitor is provided so as to stop a DC power applied to a field effect transistor forming an amplifier from flowing outside, an interdigital capacitor formed on a dielectric board mounted with an electric field effect transistor by the use of bumps is used as the above DC cut capacitor, and a bias circuit is formed by mounting a low-frequency bias laminated ceramic capacitor and an interdigital capacitor on the same dielectric board mounted with the above field effect transistor, by which a small, inexpensive, and multi- stage flip-chip amplifier can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wide band amplifier used for microwave communication and the like, an amplifier used in an oscillator, a transceiver and the like.

[0002]

2. Description of the Related Art FIG. 5 shows a form of a flip chip amplifier according to a conventional embodiment. In the figure, 1 is an RF input pattern, 2 is an RF output pattern, 3 is a dielectric substrate, 4 is a metal carrier on which the dielectric substrate 3 is mounted by soldering or adhesive, and 5 is bump-mounted on the dielectric substrate 3. Field effect transistors, 6 and 7 are via holes formed in the dielectric substrate 3 for grounding the source electrode of the field effect transistor 5, and 8 is the field effect transistor 5.
A gate bias circuit for supplying a bias to the device, 9 is a stabilizing resistor, 10 is a pattern forming a gate side short stub, 77 and 80 are parallel plate capacitors, 76 and 79 are wires, and 78 and 81 are radial open stubs. is there.

Further, 19 is a drain bias circuit for supplying a bias to the field effect transistor 5, 20 is a pattern forming a drain side short stub, and 82 and 83 are DC power supplied to the field effect transistor 5 and the outside of the device. Coupling lines for cutting DC for cutting off and, 84 and 85 are matching circuits.

6 and 7 show a detailed view of the field effect transistor 5 and a mounting view of the dielectric substrate 3 and the field effect transistor 5. In the figure, 86 is a drain electrode bump mounting pad in the field effect transistor 5, 87 is a gate electrode bump mounting pad in the field effect transistor 5, 88 is one source electrode bump mounting pad in the field effect transistor 5,
89 is another source electrode bump mounting pad in the field effect transistor 5, 90 is a bump for connecting the dielectric substrate 3 and the drain electrode bump mounting pad 86 by thermocompression bonding, and 91 is the dielectric substrate 3 and gate. Bumps for connecting the electrode bump mounting pads 87 by thermocompression bonding,
Reference numeral 92 denotes the dielectric substrate 3 and the source electrode bump mounting pad 8
A plurality of bumps for connecting 9 by thermocompression bonding, and 93 for a plurality of bumps for connecting the dielectric substrate 3 and the source electrode bump mounting pad 88 by thermocompression bonding.

Next, the operation will be described. 5, 6,
In the conventional flip-chip amplifier shown in FIG. 7, the RF signal is input from the RF input pattern 1, and the coupling line 8 having a length of ¼ wavelength with respect to the DC signal for DC cutting is used.
After passing through 2, the impedance is converted by the input side matching circuit 84 and input to the field effect transistor 5 via the bump 91. At this time, the field effect transistor 5 is biased by the DC power supplied from the gate bias circuit 8 and the drain bias circuit 19, and the RF signal is amplified by the DC power supplied from the drain bias circuit 19.

After that, the RF signal is impedance-converted by the output side matching circuit 85 via the bump 90, passes through the coupling line 83 having a length of ¼ wavelength with respect to the DC signal for the DC cut, and outputs. Output from pattern 2.
Regarding the power supplied to the field effect transistor 5, the gate bias is parallel plate capacitor 77 from the outside.
Is supplied through the wire 76, the short stub 10, and the stabilizing resistor 9, and the drain bias is externally supplied through the parallel plate capacitor 80, the wire 79, and the short stub 20.

Here, the stabilizing resistor 9 removes an unnecessary signal with respect to the RF signal by its resistance value, the short stub 10 is short-circuited with respect to the RF signal by the radial open stub 78, and its line length is desired. It has a quarter wavelength for the RF signal frequency. Further, the parallel plate capacitor 77 and the wire 76 bonded on the metal carrier 4 are attached.
Grounded through. Further, the short stub 20 is short-circuited with respect to the RF signal by the radial open stub 81, and the line length thereof has a length of ¼ wavelength with respect to the desired RF signal frequency. Further metal carrier 4
It is grounded via a parallel plate capacitor 80 bonded above and a wire 79.

Since the conventional flip-chip amplifier shown in FIGS. 5, 6 and 7 is formed by only the pattern of the coupled lines 82 and 83 as a DC cut, it has the advantages of being inexpensive and having a small loss. Further, since the short stubs 10 and 20 are short-circuited in RF by the parallel plate capacitors 77 and 80, the MIM (Metal Insulator Met) is used.
Al) is not used, and the dielectric substrate 3 can be formed by an inexpensive and simple process.

In the conventional flip chip amplifier shown in FIGS. 5, 6 and 7, the field effect transistor 5 and the dielectric substrate 3 are connected by the bumps 90, 91, 92 and 93. Since the parasitic inductor component is also small, variations in characteristics are small. In addition, the bumps 9 are formed on the source electrodes 88 and 89 of the field effect transistor 5.
By arranging a plurality of 2, 93, it is possible to efficiently dissipate the heat generated from the field effect transistor 5.

In the conventional flip chip amplifier shown in FIGS. 5, 6 and 7, the field effect transistor 5 which is an active element and the dielectric substrate 3 which is a passive element are separated from each other, so that a microwave integrated circuit (hereinafter, MMIC: Monol) is used.
itic Microwave Integrate
d Circuit) and G that constitutes the MMIC
The area of aAs (Gallium Arsenide) can be reduced, and the cost can be reduced.

[0011]

However, as shown in FIGS.
In the conventional flip-chip amplifier of No. 7, the short stubs 10 and 20 used at the time of impedance conversion are connected to the dielectric substrate 3 and the parallel plate capacitors 77 and 80 on the metal carrier 4 by using wires 76 and 79. It has a structure that short-circuits. Due to this structure, even if the inductance component is reduced by connecting the field effect transistor 5 and the dielectric substrate 3 with the bumps 90, 91, 92, 93, the wires 76, 79 are parallel to the short stubs 10, 20. Flat plate capacitor 77,
A wire process for connecting 80 is required, and the influence of wire inductance on electrical characteristics is large,
And parallel plate capacitors 77 and 8 with respect to the dielectric substrate 3.
Since 0 has an external structure that is adhered to the metal carrier 4, the flip chip amplifier becomes large as a whole,
There is a problem that it is difficult to reduce the cost of the flip chip amplifier.

Further, in the conventional flip-chip amplifier shown in FIG. 5, the coupling lines 82 and 83 inserted for cutting off the DC power supplied to the field effect transistor 5 from the external circuit of the device are generally desired. Since it has a length of 1/4 wavelength with respect to the RF signal frequency, it becomes large for low frequencies, and there is a problem that it is difficult to configure a flip-chip multistage amplifier. Moreover, since the coupling capacitance cannot be changed arbitrarily, there is a problem that it is difficult to use for impedance transformation.

It is an object of the present invention to obtain a small-sized and low-cost flip chip amplifier by using an interdigital capacitor and a laminated ceramic capacitor as a DC cut and short stub capacitor.

[0014]

A flip-chip amplifier according to a first aspect of the present invention is a field effect transistor having bump mounting pads on a source electrode, a gate electrode and a drain electrode, and a dielectric for mounting the field effect transistor. In a flip-chip amplifier including a substrate, a field effect transistor, and bumps for mounting this dielectric substrate, the dielectric substrate applies a bias to the matching circuit used for input / output impedance conversion of the field effect transistor and the field effect transistor. Equipped with a bias circuit to
This bias circuit is provided with a laminated ceramic capacitor for low frequency bypass and an interdigital capacitor formed on a dielectric substrate, and the field effect transistor and the dielectric substrate are bump-mounted. A flip-chip amplifier according to a second invention is the flip-chip amplifier according to the first invention, comprising a plurality of field effect transistors in the same plane of a dielectric substrate and a plurality of impedance matching circuits. A flip-chip amplifier according to a third invention is the flip-chip amplifier according to the first or second invention, wherein the field effect transistor comprises a resin-based underfill agent between the dielectric substrate and the field effect transistor.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. 1 is a configuration diagram of a flip chip amplifier according to Embodiment 1 of the present invention, FIG. 2A is a detailed diagram of an interdigital capacitor 17 of FIG. 1, and FIG. 2B is a gate bias circuit of FIG. 8 is a detailed view of FIG. The structure itself for bump mounting the field effect transistor is similar to the conventional flip chip amplifier, and the structure is shown in FIGS. 6 and 7. In FIG. 1, 1 is an RF input pattern, 2 is an RF output pattern, 3 is a dielectric substrate, and 4 is a metal carrier on which the dielectric substrate 3 is mounted by soldering or an adhesive.

5, 28, 52 are field effect transistors of the first, second, N (N = 3, 4, ...) Which are bump-mounted on the dielectric substrate 3, and 6, 29, 53 are field effects. The source electrode 88 and the plurality of bumps 9 connected to the source electrode 88 shown in FIG.
Via holes 7, 30, 30 and 54 for grounding the field effect transistors 5, 28 and 52 are connected to the source electrode 89 and the source electrode 89 shown in FIG. Via holes 92 for connecting the field effect transistor 5 to the ground.

Further, 8, 32 and 57 are gate bias circuits (details of FIG. 2a) for supplying DC power to the field effect transistors 5, 28 and 52, and 9, 33 and 58 are stabilizing resistors, 10. 34 and 59 are patterns forming short stubs, 11, 35 and 60 are interdigital capacitors, and 12, 36 and 61 are patterns 10, 34 and 59 forming short stubs, which are grounded through the interdigital capacitors 11, 35 and 60. Via holes, 13, 37, 62 are resistors, 14, 38, 63 are RF
Patterns, 15, 39 and 64 are multilayer ceramic capacitors, and 16, 40 and 65 are via holes.

Also, 17, 31, 51, 55 and 56 are D
C-cut interdigital capacitor (Fig. 2b
(Details), 18, 27, 41, 50, 66, and 75 are matching circuits for performing impedance conversion, 19, 42, and 67.
Is a drain bias circuit for supplying DC power to the field effect transistors 5, 28, 52, 20, 43, 68
Is a pattern forming short stubs, 21, 44, 6
9 is an interdigital capacitor, 22, 45, 70
Is a pattern 20, 43, 68 forming a short stub
Vias for grounding via the interdigital capacitors 21, 44, 69, 23, 47, 71 are resistors, 24, 47, 72 are RF patterns, 25, 48, 7
Reference numeral 3 is a monolithic ceramic capacitor, and reference numerals 26, 49 and 74 are via holes. It is obvious that the stabilizing resistors 9, 33, 58 may be unnecessary depending on the characteristics of the circuit. Further, the drain bias circuits 19, 42, 67
Is obviously equivalent to the case without the stabilizing resistors 9, 33, 58 in the gate bias circuits 5, 28, 52.

Next, a detailed description of the first embodiment will be given.
The RF signal is input from the RF pattern 1 and passes through the interdigital capacitor 17 for DC cut. At this time, the RF signal impedance-converted by the C component of the interdigital capacitor 17 is further impedance-converted by the matching circuit 18. After that, the RF signal is input to the field effect transistor 5 via the bump 91. At this time, the field effect transistor 5 is biased by the DC power supplied from the gate bias circuit 8 and the drain bias circuit 19, and the drain bias circuit 19 is set.
The RF signal is amplified by the supplied DC power.
After that, the RF signal is output to the output matching circuit 1 via the bump 90.
The impedance is converted at 6. After that, the second stage, 3 ...
The same operation as in the Nth stage is performed, and the RF signal passes through the Nth stage interdigital capacitor 56 and is output from the RF pattern 2.

Regarding the power supplied to the field effect transistor 5, the gate bias is externally supplied to the point of the short stub 10 which is short-circuited in terms of RF, and is supplied through the short stub 10 and the stabilizing resistor 9. The drain bias is supplied to a point where the short stub 20 is short-circuited in terms of RF, and is supplied through the short stub 20. Here, the stabilizing resistor 9 removes an unnecessary signal with respect to the RF signal, and the short stub 10 generally has a line length of ¼ wavelength with respect to the desired RF signal. When used as a short stub for impedance conversion, it has a required length. Further, the short stub 10 is grounded by the interdigital capacitor 11 for DC cutting and the via hole 12 to remove unnecessary RF signals, and is grounded by the resistor 13, the RF pattern 14, the laminated ceramic capacitor 15 and the via hole 16. As a result, the unnecessary signal on the low frequency side with respect to the desired RF signal is removed by the resistor 13.

Further, the short stub 20 generally has a line length of ¼ wavelength with respect to a desired RF signal, and has a necessary length when it is used for impedance conversion as a short stub. Further, the short stub 20 is grounded by the interdigital capacitor 21 for DC cut and the via hole 22 to remove unnecessary RF signals,
Further, by grounding the resistor 23, the RF pattern 24, the multilayer ceramic capacitor 25, and the via hole 26, unnecessary signals on the low frequency side of the desired RF signal are removed by the resistor 23. Thereafter, the second, third, ... Nth stages are similar in operation.

In this embodiment, R is used for DC cutting.
By using an interdigital capacitor instead of a 1/4 wavelength coupled line for F signals, low frequency R
It is possible to obtain a relatively free capacitance value by designing the number of fingers or the finger length forming the interdigital capacitor to a desired length for the F signal, and compared with the case of using a coupled line. It has the advantage of not increasing in size.

When RF impedance conversion is performed, a short stub that short-circuits the tip in terms of RF may be required, and it is necessary to prevent DC from flowing to the outside of the device at that point as well. Also, by using the interdigital capacitor, it is possible to set the number of fingers or the finger length to a desired length to set a relatively free capacitance value.

Further, by using a monolithic ceramic capacitor in which external electrodes are provided at both ends of a general ceramic dielectric as a capacitor for low frequency bypass,
Since it is possible to solder or adhere directly to the pattern of the dielectric substrate, there is no need to carry out the wire connection process as compared with the case of using the parallel plate capacitor, which was required in the conventional technology. The cost can be reduced by reducing

Further, since the wire connection is eliminated by using the laminated ceramic capacitor, a plurality of amplifier patterns are formed in the same substrate, the laminated ceramic capacitors are soldered or adhered, and the field effect transistors are collectively bumped. After mounting, on-wafer measurement is possible. Further, a plurality of amplifiers are formed and mounted on the same substrate, and the substrate is diced while spraying pure water, so that the cost can be reduced.

Further, by using a laminated ceramic capacitor as a low frequency bypass capacitor, a low frequency bias circuit can be formed on the same substrate as the RF circuit, and the flip chip amplifier can be integrated into the bias circuit. There is also an advantage that a compact circuit can be realized.

Further, by using an interdigital capacitor, a laminated ceramic capacitor and a plurality of field effect transistors in the bias circuit, there is an advantage that a multistage high gain flip chip amplifier can be easily constructed.

Embodiment 2. FIG. 3 is a diagram showing a second embodiment of the present invention, and FIG. 4 is a detailed diagram showing mounting on the dielectric substrate 3 and the field effect transistor 5 in the second embodiment of the present invention. The basic structure of the flip chip amplifier is the same as that of the first embodiment, but is characterized in that a resin-based underfill agent is injected between the field effect transistor and the dielectric substrate.

Next, a detailed description of the second embodiment will be given.
The basic structure is the same as that of the first embodiment of FIG. 1, but in FIG. 4, 3 is a dielectric substrate, 4 is a metal carrier, and 5 is a metal carrier.
Is a field effect transistor, 6 is a via hole, 90 is a bump for connecting the dielectric substrate 3 and the drain electrode pad 86 by thermocompression bonding similar to those shown in FIG. 7, 91 is the same as that shown in FIG. 7. A bump for connecting the dielectric substrate 3 and the gate electrode pad 87 by thermocompression bonding, and 92 for thermocompression bonding and connecting the dielectric substrate 3 and the source electrode pad 89 similar to those shown in FIG. And 94 are resin-based underfill agents injected between the dielectric substrate 3 and the field effect transistor 5.

As described above, the second embodiment has the advantage of improving the moisture resistance, the reliability against vibration and the impact by injecting the resin underfill agent between the field effect transistor and the dielectric substrate. Furthermore, by injecting the underfill agent, sealing using an airtight package is not necessary, and there is an advantage that cost can be reduced.

[0031]

The flip-chip amplifier according to the first to third aspects of the present invention can miniaturize the circuit even for a low-frequency RF signal and obtain a desired capacitance value. In addition, the influence of variations in the inductance component of the wire is excluded, and since it can be integrally configured on the dielectric substrate,
It is possible to reduce the size and cost of the flip chip amplifier. Further, in addition to the above effects, it is possible to easily configure a multi-stage flip chip amplifier. In addition, on-wafer evaluation is possible, and since substrate dicing can be performed in a series of operations, cost reduction can be achieved.

Further, in the flip-chip amplifier according to the third aspect of the present invention, by injecting a resin-based underfill agent between the field effect transistor and the dielectric substrate, the moisture resistance, the reliability against vibration and the impact are improved, Further, since it is not necessary to carry out the hermetic sealing by the external package of the flip chip amplifier, the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of a flip chip amplifier according to the present invention.

FIG. 2 is a detailed diagram of an interdigital capacitor and a gate bias circuit in the first embodiment of the flip chip amplifier according to the present invention.

FIG. 3 is a diagram showing a second embodiment of a flip chip amplifier according to the present invention.

FIG. 4 is a diagram showing a mounting cross-sectional view of a flip-chip amplifier according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a conventional flip chip amplifier.

FIG. 6 is a schematic view of a field effect transistor of a conventional flip chip amplifier.

FIG. 7 is a view showing a mounting cross-sectional view of a conventional flip chip amplifier.

[Explanation of symbols]

1 RF input pattern, 2 RF output pattern, 3
Dielectric Substrate, 4 Carriers, 5, 28, 52 First, Second, Nth (N = 3, 4, ...) Field Effect Transistors, 6, 47, 72 Via Holes, 7, 3
0,54 via hole, 8,32,57 gate bias circuit, 9,33,58 stabilizing resistor, 1
0,34,59 Patterns that form short stubs,
11,35,60 interdigital capacitors,
12,36,61 via hole, 13,37,62
Resistance, 14, 38, 63 RF pattern, 1
5, 39, 64 monolithic ceramic capacitor, 16,
40,65 via holes, 17,31,51,5
5,56 DC cut interdigital capacitor, 18,27,41,50,66,75 Matching circuit,
19, 42, 67 Drain bias circuit, 20,
43,68 Patterns that form short stubs, 2
1,44,69 interdigital capacitor, 2
2,45,70 via holes, 23,47,71
Resistance, 24, 47, 72 RF pattern, 25, 4
8,73 Multilayer ceramic capacitor, 26,4
9,74 Via hole, 76,79 Wire, 7
7,80 Parallel plate capacitor, 78,81 Radial open stub, 82,83 DC cut coupling line, 84,85 Matching circuit, 86 Drain electrode bump mounting pad, 87 Gate electrode bump mounting pad, 88 Source electrode bump mounting Pad, 89
Source electrode bump mounting pad, 90 bump,
91 bumps, 92 bumps, 93 bumps, 9
4 Resin-based underfill agent

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5J067 AA01 AA04 CA87 CA92 FA16                       HA09 HA25 HA29 KA12 KA29                       KA66 KA68 KS11 LS11 MA08                       QA04 QS02 QS06 SA13

Claims (3)

[Claims] 1. A field effect transistor having bump mounting pads on a source electrode, a gate electrode and a drain electrode, a dielectric substrate for mounting the field effect transistor, the field effect transistor and the dielectric substrate. In the flip-chip amplifier provided with bumps for use in the dielectric substrate, the dielectric substrate includes a matching circuit used for input / output impedance conversion of the field effect transistor, and a bias circuit for applying a bias to the field effect transistor. A flip-chip amplifier comprising a multilayer ceramic capacitor for low frequency bypass and an interdigital capacitor formed on the dielectric substrate, wherein the field effect transistor and the dielectric substrate are bump-mounted. 2. The flip chip amplifier according to claim 1, further comprising a plurality of the field effect transistors and a plurality of impedance matching circuits in the same plane of the dielectric substrate. 3. The field-effect transistor comprises a resin-based underfill agent between the dielectric substrate and the field-effect transistor.
Alternatively, the flip chip amplifier according to item 2.