JPS5861652A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an RF transistor for high output and high band having a matching circuit inside, by reducing earth inductance by physical and circuit means without providing an earth electrode plate in a transistor package or IC. CONSTITUTION:An emitter earth conductor 2 is formed on an insulating substrate 1 in a band form and connected 21, 22 to a base back surface electrode on the both side surfaces, and then terminals 23, 24 are provided. A base terminal 31 and a collector terminal 41 are connected to conductors 3, 4 on the both sides of the conductor 2. A clearance 25 is opened at the center of the conductor 2, an insular collector conductor 5 is provided, and then a transistor chip 50 and a capacity array chip 60 are joined to conductors 5 and 3. Connections 71, 72 are performed from the side of the terminal 4 of the conductor 2 to the capacity of the chip 60 via the emitter junction pad of the chip 50, connections 81, 82 are performed from the base pad of the chip 50 to the terminal 3, and then the conductor 5 is connected to 90, 91 to the terminal 4. The emitter earth inductance becomes the minimum by the series resonance of the connection 72 and the capacity 62, and input/output impedance Q can be set respectively to the local minimum by the matching circuit for the capacity 65, connection 82 and connections 90, 91, terminal 4 resulting in an RF semiconductor device for high output and high band.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a high frequency semiconductor device having an internal matching circuit.

Conventionally, high-frequency, high-power transistors are placed in a transistor container made of an insulating substrate in order to minimize ground inductance and obtain maximum gain or output. Two emitter terminal electrodes with different directions are provided, and a thin bonding wire is connected to each via the emitter bonding butt of the transistor chip, or the ground inductance from the emitter electrode of the transistor chip to the emitter terminal electrode of the transistor container is In order to further reduce
A structure in which the emitter bonding pad of the transistor chip is connected to this ground electrode plate over a short distance using a thin bonding wire or the like is rarely used.

In addition, as a method to reduce grounding inductance, a tanza-like through hole is provided on the back side of the insulating substrate, parallel to the transistor chip in the transistor container made of the insulating substrate, and connected to the grounding electrode on the emitter bonding pad side. The commonly used method was to connect the ground metallized surface to a ground metallized surface.

However, the above-described methods for reducing grounding inductance all have complicated structures and manufacturing methods, which are factors that increase the price of transistor containers. Furthermore, in any of the above-mentioned methods, it is impossible to physically reduce the ground inductance to zero, and there are limits to obtaining high gain and high output.

An object of the present invention is to eliminate the causes of the price increase as described above, reduce ground inductance, and provide a high-output, wide-band, high-frequency, high-output transistor.

Another object of the present invention is to provide a transistor that can be used as an entire transistor chip carrier or as part of a membrane circuit board, and that can easily realize a high frequency output hybrid acquisition/concentration circuit.

According to the present invention, it is possible to reduce the ground inductance both physically and circuit-wise without providing a ground electrode plate ft within the transistor container or within the hybrid film integrated circuit. That is, in the present invention, metallization is carried out in a band shape approximately at the center of the narrow surface of an insulating substrate, and both ends are connected to the metallization on the back side of the substrate through through holes or side metallization, and the crab ivy grounding conductor portion and the emitter grounding portion are sandwiched therebetween. an insulating substrate having a base and four collector terminals respectively metallized on both sides of the surface of the insulating substrate; a transistor chip and a plurality of capacitor chips mounted on the insulating substrate; In a semiconductor device comprising a plurality of bonding lines connecting the transistor chip and capacitor chip to the emitter grounded conductor section and each terminal conductor section, the transistor chip is provided approximately at the center of the emitter grounded conductor section. The capacitor chip is mounted and connected to an island-shaped collector conductor section separated from the emitter ground conductor section, and one electrode of the capacitor chip is mounted on the emitter ground conductor section between the transistor chip and the base terminal conductor section. The emitter bonding line, the base bonding line, and the collector bonding line connected to each other connect the emitter bonding pad of the transistor chip from the emitter ground conductor section located between the transistor chip and the collector terminal section. from the base bonding pad of the transistor chip to the base terminal portion via the other electrode of the remaining capacitor chips; The collector conductor portion is connected to the collector terminal portion, respectively.

Embodiments of the present invention will be explained below with reference to the drawings.

FIG. 1 shows a first embodiment of a semiconductor device of the present invention, and FIG. 2 is an equivalent circuit diagram thereof. Each circuit element in FIG.
In order to correspond to each part in the figure, the same number as the part number in FIG. 1 is shown with a dash added. In FIG. 1, a strip-shaped emitter grounding conductor part 2 is provided with a metallized layer approximately in the center of an insulating substrate 1, and this emitter grounding conductor part has side metallization 21, 22 on both sides of the insulating substrate l.
It is electrically connected to the back metal layer of the highly insulating substrate.

Further, emic terminals 23 and 24 for leading to the outside are provided at both ends of the emitter grounded conductor portion, respectively.

On the other hand, on the insulating substrate 1, there are base terminal portions on both sides of the emitter conductor portion 2 in different directions.
3 and a collector terminal portion 4 are metallized, and a base terminal 31 and a collector terminal 41 are connected to the base and collector terminal portions, respectively. Furthermore, an island-shaped collector conductor part 5 is provided approximately at the center of the emitter ground conductor part 2 with a gap 25 for electrical insulation from the emitter ground conductor 27. One capacitor array chip 60 containing 50.5 transistor chips and capacitors is die-bonded to the collector conductor portion 5 and the emitter ground conductor portion of the rigid base terminal portion, respectively. The emitter bonding lines 71 and 72 are connected from the emitter ground conductor portions 2 of the four collector terminal portions to the capacitors in the capacitor array chip 60 via the emitter bonding pads of the transistor chip 50. The pace bonding lines 81 and 82 are connected to the base bonding terminal portion 3 of the transistor chip 50 via the remaining capacitors of the capacitor array chip 60. Collector bonding wires 90 and 91 are each connected from the end of the collector conductor section 5 to the collector terminal section 4.

As is well known, high-frequency, high-output transistor chips,
When operating as a common emitter, the input impedance between one pace and the emitter must be inductance.
On the other hand, since the output impedance between the collector and emitter is capacitive, when using this transistor chip in a container, in order to obtain high gain and high output at the operating frequency,
In addition to creating a structure that minimizes emitter grounding impedance, we also ensure that the Q does not exceed the Q of the transistor chip on both the input and output sides. Also, on the output side, it is necessary to construct an inductance transistor container or a matching circuit between each terminal of the transistor and the transistor chip to cancel out the capacitance.

However, if you try to design a transistor housed in such a transistor container or a transistor container with an internal matching circuit, if you try to minimize the common emitter inductance, the Q of the input or output impedance will increase, or vice versa. If you try to minimize the Q of the input/output impedance, the common emitter inductance tends to become large.Therefore, minimizing both the Q of the input/output impedance and the grounding inductance at the same time will improve the performance of the transistor. It has been difficult to improve the performance of transistor chips. The semiconductor device of the present invention is intended to minimize both the common emitter inductance of the transistor and the output impedance Q of the transistor at the same time, as can be seen from the equal film circuit in FIG. , the emitter grounded impedance can be minimized by selecting the capacitance of capacitor 62 such that emitter bonding line 72 and capacitor 62 have series resonance at the operating frequency. At this time, the emitter current of the transistor can bypass the bonding line 71 and flow to the ground.

Q of the input impedance on the pace side of the transistor is determined by a matching circuit consisting of the bonding line 81, the capacitor 65 in the capacitor array chip 60 on the emitter grounding part 2 closest to the emitter bonding pad, and the bonding line 82. This makes it possible to keep it to a minimum.

Next, Q of the output impedance on the collector side of the transistor
The collector conductor part for collector die bonding is separated from the collector terminal part and is provided in the form of an island within the emitter grounded conductor part to minimize the area, so the capacitor component of the output impedance is smaller than that of the chip. Since the bonding wire 90.91 and the collector terminal section 4 are connected to the collector terminal section 4 through the bonding wire 90.91 with almost no increase in the length, the bonding wire 90.91 and the collector terminal section 4 can be connected to each other at the operating frequency by imitating a matching circuit to increase their length. If you design it, you can make it extremely small.

FIG. 3 shows another embodiment of the semiconductor device of the present invention, in which the emitter terminals 23 and 24 of the embodiment of FIG.
Pace terminal 31, collector terminal section 4, collector terminal 41
The isomembrane circuit diagram is shown at point 11 in Figure 2.
It is surrounded by 00. If this semiconductor device is used in a hybrid film integrated circuit, that is, it is inserted between the film circuit boards or into a hole provided in the film circuit board, and placed on the film circuit board located on the left side of this embodiment. By connecting the input circuit and the capacitances 61, 63.65 of the capacitor chip with bonding wires, the output circuit on the membrane circuit board located on the right side of this embodiment and the collector conductor portion 5 are bonded. By connecting with a wire, it becomes possible to have the same function as the first semiconductor device of the present invention. At this time, it is a hot theory that the wire for connecting the membrane circuit and the semiconductor device and the bonding wire on the output side each play a role as a part of the matching circuit. In the embodiments shown in Figures 1 and 3, the capacitors 62, 64 for grounding the emitter and the shunt capacitors 61, 63, 65 for the input matching circuit on the pace side use a capacitor array tip with the back surface of one side serving as a common electrode.
The semiconductor device of the present invention does not need to be a capacitor array chip; in other words, the capacitor for the input matching circuit and the capacitor for emitter grounding are each connected separately to the emitter grounding conductor on the bonding side of the transistor. All you have to do is

High-frequency, high-output transistors are used to achieve even higher output.
9, where many transistor elements are arranged in the same chip;
It is common to use a plurality of such chips arranged in the same container, but such high frequency, high power transistors often cause thermal and high frequency power disharmony. It may not be possible to obtain an output proportional to the number of elements. In order to eliminate this disharmony, higher output can be obtained by setting an appropriate amount of grounded inductance between the emitter of each transistor element and the emitter grounded conductor. It may be better not to provide lines 72 and 74.

As explained above, the semiconductor device of the present invention has (1) a grounded emitter conductor on the surface of the insulating substrate and electrical continuity with the grounded metallization on the back surface; (
3) At least the shaft capacitor for the pace input matching circuit is die-bonded on the emitter grounding conductor on the pace bonding pad side close to and parallel to the transistor chip, (4) the emitter and pace bonding wires are each Also connect the emitter bonding pad to the emitter grounding conductor land on the same side, and the pace bonding pad to the input matching shunt capacitor. Impedance becomes minimum, ■)
Parasitic capacitance at the collector terminal can be eliminated, and the capacitance between the collector and ground can be kept to a minimum, so there is no need to unnecessarily increase the Q on the output side. (3) Bonding from the pace bonding pad to the shunt capacitor Since the line length can be minimized, the inductance from the emitter bonding pad to the emitter to ground conductor can be optimized to provide the lowest Q input matching circuit.

For the above reasons, the present invention can provide a semiconductor device that is structurally simpler than the conventional high frequency high-frequency quadrupole transistor, is inexpensive, has high performance, has a low Q, and is therefore easy to use in terms of circuitry.

High-power transistors generate a large amount of heat, and in order to improve the dissipation of this heat, a BeO substrate is often used as an insulating substrate. In order to reduce the thermal resistance, the size of this BeO substrate must be increased (perhaps more than the size of the transistor chip), and for this reason, conventionally, the size of the BeO substrate has to be increased at the expense of increasing the Q of the input and output impedance of the transistor. It's here. Another advantage of the present invention is that if the second semiconductor device of the present invention is used in a hybrid film integrated circuit, it is possible to avoid increasing the Q of the output impedance of the transistor chip (as can be seen from the above explanation). Since the size can be made slightly larger than the size of a transistor chip, it is possible to provide a high-frequency, high-output hybrid film integrated circuit with low thermal resistance and high reliability.

Although the embodiment for emitter grounding has been described above, it can be similarly applied to pace grounding, in which case the pace electrode becomes the ground electrode and the emitter electrode becomes the input electrode.

[Brief explanation of drawings]

1, 2, and 3 are a plan view of a semiconductor device according to one embodiment of the present invention, an isometric circuit diagram thereof, and a plan view of a semiconductor device according to another embodiment of the present invention, respectively. 1...Insulating substrate, 2...Emitter ground conductor bond, 21.22...Side metalization, 23, 24...Emitter (external connection) terminal,
25...Gap, 3...Base terminal land, 31...Base (external connection) terminal, 4...
...Collector terminal land, 41...Collector (external connection) terminal, 5...Collector conductor land, 50...Transistor chip, 60...
...Capacitor array chip, 61, 62, 63, 64
．． 65... Each capacitor in the capacitor array, 70 (71°72)... Emitter bonding line, 80 (81, 82)... Base bonding line, 90 ( 91, 92)... Collector bonding line, 100... Isofilm circuit diagram of FIG. 3. Inferior / Good Moose 2 With the Father Z / Lol J

Claims (1)

[Claims] a common electrode conductor portion formed in a strip shape on the surface of the insulating substrate; input and output conductor portions formed respectively on opposite sides of the surface of the insulating substrate with the common electrode conductor portion sandwiched therebetween; In a semiconductor device having a transistor chip and a capacitor chip mounted on an insulating substrate, the transistor chip is mounted on an island-shaped conductor portion provided approximately in the middle of the common electrode conductor portion and separated from the common electrode conductor portion. one electrode of the capacitor chip is mounted and connected on the common electrode conductor portion between the transistor container and the input conductor portion, and a thin common electrode wire is connected between the transistor chip and the output conductor portion. The common electrode conductor part located between the parts is connected to the capacitor chip via the common electrode of the transistor chip, and the input thin wire is connected from the input electrode of the transistor chip to the input conductor part via the capacitor chip, 14. A semiconductor device characterized in that output thin wires are connected from the output conductor portion to the island-shaped conductor portion, respectively.