JPS634662A - Electronic circuit device - Google Patents

Electronic circuit device

Info

Publication number
JPS634662A
JPS634662A JP61146884A JP14688486A JPS634662A JP S634662 A JPS634662 A JP S634662A JP 61146884 A JP61146884 A JP 61146884A JP 14688486 A JP14688486 A JP 14688486A JP S634662 A JPS634662 A JP S634662A
Authority
JP
Japan
Prior art keywords
semiconductor chip
capacitor
insulating layer
electronic circuit
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61146884A
Other languages
Japanese (ja)
Inventor
Shigeaki Minamibata
重秋 南畑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP61146884A priority Critical patent/JPS634662A/en
Publication of JPS634662A publication Critical patent/JPS634662A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To enable mounting with high density by laminating an insulating layer and a conductor layer between a semiconductor chip and a supporter and forming a capacitor by the laminated conductor layer and insulating layer while the capacitor is utilized as a bypass capacitor connected in parallel between the semiconductor chip and a power supply. CONSTITUTION:An insulating layer 6 and a conductor layer 7 are formed to a laminating shape between a conductor land 4 and a semiconductor chip 1, and a capacitor 9 is shaped, using the conductor land 4 and the conductor layer 7 as electrodes and the insulating layer 6 as a dielectric layer. The capacitor 9 superposed in the same plane space as the semiconductor chip 1 is utilized as a bypass capacitor for a power supply VCC and a GND, thus remarkably shortening an effective wiring distance between the semiconductor chip 1 and the bypass capacitor 9. Accordingly, an inductive parasitic impedance Zs interposed in series between the semiconductor chip 1 and the bypass capacitor 9 can be reduced, and a positive bypass effect is obtained even in the capacitor having comparatively small capacitance while both the semiconductor chip 1 and the bypass capacitor 9 can be mounted in a comparatively small space with high density.

Description

【発明の詳細な説明】 ［産業上の利用分野コ この発明は、電子回路装置技術、さらにはチップ状の半
導体装置を組込んだ電子回路装置に適用して有効な技術
に関するもので、たとえば、数百ＭＨｚないし数ギガＨ
ｚ以上の超高周波帯で動１ヤする通信用電子回路装置に
利用して有効な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] This invention relates to electronic circuit device technology, and further to technology that is effective when applied to electronic circuit devices incorporating chip-shaped semiconductor devices. Several hundred MHz to several gigahertz
The present invention relates to a technique that is effective for use in communication electronic circuit devices that operate in an ultra-high frequency band of z or higher.

［従来の技術］ 最近、たとえば日経マグロウヒル社刊行「日経エレクト
ロニクス　１９８２年２月１日号（ｎｏ。[Prior Art] Recently, for example, Nikkei McGraw-Hill Publishing Co., Ltd. published “Nikkei Electronics February 1, 1982 issue (no.

２８３）Ｊ　９２〜１２８頁（解説ニアセンブリ革命を
引き起こすリードのない小型部品）に記載されているよ
うに、所定の回路機能が形成された半導体チップをチッ
プ状の受動部品とともに高密度実装してなる電子回路装
置が作られるようになってきた。283) As described in J pages 92-128 (Explanation: Leadless small components that bring about an assembly revolution), semiconductor chips with predetermined circuit functions are mounted in high-density together with chip-shaped passive components. Electronic circuit devices have begun to be manufactured.

ここで、本発明者は、半導体チップをチップ状の受動部
品とともに適当な支持体に組み込むことにより、数百Ｍ
Ｈｚないし数ギガＨｚ以上の超高周波帯で動作する無線
通信用の電子回路装置の組立を検討した。以下は、公知
とされた技術ではないが、本発明者によって検討された
技術であり、その概要は次のとおりである。Here, the present inventor has developed a method that allows several hundred M
We investigated the assembly of electronic circuit devices for wireless communications that operate in ultra-high frequency bands of Hz to several gigahertz or higher. Although the following is not a publicly known technique, it is a technique studied by the present inventor, and its outline is as follows.

第５図は本発明者によって検討された無線通信用電子回
路装置の一部における組立状態を示す。FIG. 5 shows an assembled state of a part of the wireless communication electronic circuit device considered by the present inventor.

同図に示す電子回路装置は、いわゆるハイブリッド型集
積回路装置に属するものであって、選択的に形成された
導体領域いわゆる導体ランド４による配線パターンが形
成された絶縁支持（ｋ、３上に、能動素子としての半導
体チップ１および受動素子としてのチップ状コンデンサ
９をそれぞれの所定位置に直付けの形で装着するととも
に、これらの装着部品（１，９）をボンディング・ワイ
ヤ２１Ａ、２１によって導体ランド４と接続することに
より、所定の回路が構成されている。The electronic circuit device shown in the figure belongs to a so-called hybrid integrated circuit device, and includes an insulating support (k, 3) on which a wiring pattern is formed by selectively formed conductor regions, so-called conductor lands 4. The semiconductor chip 1 as an active element and the chip capacitor 9 as a passive element are directly attached to their respective predetermined positions, and these attached parts (1, 9) are connected to conductor lands by bonding wires 21A, 21. 4, a predetermined circuit is constructed.

この場合、チップ状コンデンサ９はバイパスコンデンサ
として使用され、上記ボンディング・ワイヤ２ＬＡおよ
び導体ランド４を介して電源Ｖｃｃ−ＧＮＤの間に並列
に接続されている。また、絶縁支持体３には電気絶縁性
のセラミックス基板が使われ、図示を省略するが、その
支持体３上にて、たとえば高周波増幅回路などの無線通
信用の電子回路が配線されている。In this case, the chip capacitor 9 is used as a bypass capacitor and is connected in parallel between the power supply Vcc and GND via the bonding wire 2LA and the conductive land 4. Further, an electrically insulating ceramic substrate is used as the insulating support 3, and although not shown, an electronic circuit for wireless communication such as a high frequency amplification circuit is wired on the support 3.

以上のようにして、半導体チップ１が装着された支持体
３上にて、その半導体チップ１とバイパスコンデンサ９
の配線が行われている電子回路装置が組み立てられてい
る。As described above, the semiconductor chip 1 and the bypass capacitor 9 are placed on the support 3 on which the semiconductor chip 1 is mounted.
An electronic circuit device with wiring is being assembled.

［発明が解決しようとする問題点コ しかしながら、上述した技術には、次のような問題点の
あることが本発明者によってあきらかとされた。[Problems to be Solved by the Invention However, the inventors have found that the above-mentioned technique has the following problems.

すなわち、たとえば上述した電子回路装置では、第６図
にその部分的な等価回路を示すように、半導体チップ１
とコンデンサ９とを接続するためのボンディング・ワイ
ヤ２１Ａなどによって、その半導体チップ１とコンデン
サ９の間に誘導性のインピーダンスＺｓが直列に寄生す
る。この寄生インピーダンスＺｓは、比較的低い周波数
領域で動作する電子回路装置の場合にはさほど問題にな
らない。ところが、上述したように、たとえば数百ＭＨ
ｚ〜数ギガＨｚ以上の非常に高い周波数帯で動作する電
子回路装置では、わずか数ｍｍ程度の長さしかないワイ
ヤ２１Ａでも、かなり大きなインピーダンスを呈するよ
うになる。ちなみに、長さ１ｍｍのボンディング・ワイ
ヤーは約１ｎＨのインダクタンスをもち、周波数１００
１００Ｏにおいては１ｍｍの長さに対して約６Ωものイ
ンピーダンスを呈するようになる。That is, for example, in the above-mentioned electronic circuit device, as shown in FIG. 6, a partial equivalent circuit thereof, the semiconductor chip 1 is
An inductive impedance Zs is parasitic in series between the semiconductor chip 1 and the capacitor 9 due to the bonding wire 21A for connecting the semiconductor chip 1 and the capacitor 9. This parasitic impedance Zs does not pose much of a problem in the case of electronic circuit devices that operate in a relatively low frequency range. However, as mentioned above, for example, several hundred MH
In an electronic circuit device that operates in a very high frequency band of z to several gigahertz or more, even the wire 21A having a length of only a few mm exhibits a considerably large impedance. By the way, a bonding wire with a length of 1 mm has an inductance of about 1 nH and a frequency of 100
At 100O, it exhibits an impedance of about 6Ω for a length of 1mm.

このため、チップ状コンデンサ９によるバイパスコンデ
ンサを挿入しても、このコンデンサ９を半導体チップ１
に接続するためのワイヤー２１Ａによる直列寄生インピ
ーダンスＺｓによって、せっかくのコンデンサ９も、バ
イパスコンデンサとして十分に機能できなくなってしま
う。しがち、そのコンデンサ９と半導体チップ１間の直
列寄生インピーダンスＺｓによって、半導木チップ１の
回路勤牛が不安定になり、寄生発振やクロストーク（干
渉・結合）、の原因となる、という問題点を生じること
が本発明者らによってあきらがとされた。Therefore, even if a bypass capacitor using a chip capacitor 9 is inserted, this capacitor 9 is connected to the semiconductor chip 1.
Due to the series parasitic impedance Zs caused by the wire 21A for connection to the capacitor 9, the capacitor 9 cannot function sufficiently as a bypass capacitor. However, the series parasitic impedance Zs between the capacitor 9 and the semiconductor chip 1 makes the circuit operation of the semiconductor chip 1 unstable, causing parasitic oscillation and crosstalk (interference/coupling). It has been found by the inventors that this would cause problems.

また、上記チップ状コンデンサ９は、リードレス構造に
よって小型化されてはいるものの、支持体３上にてかな
り大きなスペースを占め、このことがこの種の電子回路
装置の実装密度の向上を妨げる大きな要因の一つになっ
ている、ということも本発明者によってあきらがとされ
た。Further, although the chip capacitor 9 is miniaturized by the leadless structure, it occupies a considerable space on the support 3, which hinders the improvement of the packaging density of this type of electronic circuit device. The inventor has also admitted that this is one of the factors.

本発明の目的は、比較的小容量のコンデンサでも確実な
バイパス効果が得られるとともに、半導体チップとバイ
パスコンデンサの両方を比較的小さなスペース内に高密
度に実装できるようにする、という技術を提供すること
にある。An object of the present invention is to provide a technology that allows a reliable bypass effect to be obtained even with a relatively small capacitance capacitor, and also enables high-density packaging of both a semiconductor chip and a bypass capacitor in a relatively small space. There is a particular thing.

本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

［問題点を解決するための手段コ 本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

すなわち、半導体チップと支持体の間に絶縁層と導体層
を積層し、この積層された導体層と絶縁層によってコン
デンサを形成するとともに、このコンデンサを半導体チ
ップと電源との間にて並列に接続するバイパスコンデン
サとして利用する、というものである。That is, an insulating layer and a conductor layer are laminated between a semiconductor chip and a support, a capacitor is formed by the laminated conductor layer and insulating layer, and this capacitor is connected in parallel between the semiconductor chip and a power source. It is used as a bypass capacitor.

［作用］ 上記した手段によれば、半導体チップとバイパスコンデ
ンサとが同一平面スペースに配置されることにより、そ
の半導体チップとコンデンサとの間の実効的な配線距離
が著しく短縮されるようになる。これによって、比較的
小容量のコンデンサでも確実なバイパス効果が得られる
とともに、半導体チップとバイパスコンデンサの両方を
比較的小さなスペース内に高密度に実装できるようにす
る、という目的が達成される。[Operation] According to the above-described means, the semiconductor chip and the bypass capacitor are arranged in the same plane space, so that the effective wiring distance between the semiconductor chip and the capacitor can be significantly shortened. This achieves the objective of achieving a reliable bypass effect even with a capacitor of relatively small capacity, and of allowing both the semiconductor chip and the bypass capacitor to be densely packaged in a relatively small space.

［実施例］ 以下、本発明の好適な実施例を図面に基づいて説明する
。[Examples] Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

なお、各図中、同一符号は同一あるいは相当部分を示す
。In each figure, the same reference numerals indicate the same or corresponding parts.

第１図はこの発明による電子回路装置の要部における一
実施例を示す。FIG. 1 shows an embodiment of the main part of an electronic circuit device according to the present invention.

同図に示す電子回路装置は、半導体チップ１を電気絶縁
性のセラミック基板からなる絶縁支持体３上に装着する
とともに、その支持体３上で所定の電子回路を構成する
ための配線が行われている。In the electronic circuit device shown in the figure, a semiconductor chip 1 is mounted on an insulating support 3 made of an electrically insulating ceramic substrate, and wiring for configuring a predetermined electronic circuit is performed on the support 3. ing.

支持体３の上には、導体ランド４によって所定の配線パ
ターンが形成されている。A predetermined wiring pattern is formed on the support body 3 by conductive lands 4 .

ここで、半導体チップ１は上記導体ランド４の上に装着
される。この導体ランド４と半導体チップ１の間には、
絶縁層６と導体層７が積層状に形成されている。そして
、その導体ランド４と導体層７を電極とし、かつ絶縁層
６を誘電体層としてコンデンサ９が形成されている。Here, the semiconductor chip 1 is mounted on the conductive land 4. Between this conductor land 4 and semiconductor chip 1,
An insulating layer 6 and a conductor layer 7 are formed in a laminated manner. A capacitor 9 is formed using the conductor land 4 and the conductor layer 7 as electrodes and the insulating layer 6 as a dielectric layer.

上記半導体チップ１の表面側にはハンダなどを盛った端
子部２Ａ、２Ｂが形成されている。これらの端子部２Ａ
、２Ｂは、上記導体ランド４の上に形成された導体層７
．５に対面状態で直付けされている。この場合、その半
導体チップ１の電源端子部（あるいは接地端子部）とな
る端子部２Ａは、上記コンデンサ９の一方の電極をなす
導体層７に直接接続されている。Terminal portions 2A and 2B filled with solder or the like are formed on the front side of the semiconductor chip 1. These terminal parts 2A
, 2B is a conductor layer 7 formed on the conductor land 4.
．． It is directly attached to 5 in a facing state. In this case, the terminal section 2A which becomes the power terminal section (or ground terminal section) of the semiconductor chip 1 is directly connected to the conductor layer 7 which forms one electrode of the capacitor 9.

導体層７，５は、たとえば銀ペーストなどを印刷・塗付
することにより形成される。また、絶縁層６はガラス質
のもので形成される。The conductor layers 7 and 5 are formed by printing and applying silver paste, for example. Further, the insulating layer 6 is made of glass.

以上のようにして、半導体チップ１とコンデンサ９とが
同一平面スペースに重ねられた状態で配置されている。As described above, the semiconductor chip 1 and the capacitor 9 are arranged in an overlapping state in the same plane space.

この半導体チップ１と同一平面スペースに重ねられたコ
ンデンサ９を電源ＶＣ，−ＧＮＤのバイパスコンデンサ
として利用することにより、半導体チップ１とバイパス
コンデンサ９との間の実効的な配線距離を著しく短かく
することができる。これにより、第２図にその等価回路
を示すように、半導体チップ１とバイパスコンデンサ９
との間に直列に介入する誘導性の寄生インピーダンスＺ
ｓを少なくすることができ、比較的小容量のコンデンサ
でも、確実なバイパス効果が得られるとともに、半一導
体チップ１とバイパスコンデンサ９の両方を比較的小さ
なスペース内に高密度に実装できるようになる。By using the capacitor 9 stacked on the same plane as the semiconductor chip 1 as a bypass capacitor for the power supplies VC and -GND, the effective wiring distance between the semiconductor chip 1 and the bypass capacitor 9 can be significantly shortened. be able to. As a result, as shown in the equivalent circuit in FIG. 2, the semiconductor chip 1 and the bypass capacitor 9
Inductive parasitic impedance Z intervening in series between
s can be reduced, a reliable bypass effect can be obtained even with a capacitor of relatively small capacity, and both the semiconductor chip 1 and the bypass capacitor 9 can be densely mounted in a relatively small space. Become.

第３図はこの発明の第２の実施例を示す。FIG. 3 shows a second embodiment of the invention.

同図に示した電子回路装置はパッケージ付半導体集積回
路装置として構成されている。前述した実施例との相違
点について説明すると、この実施例では、上記支持体３
として、半導体チップ１をパッケージ８内で支持する金
属タブ４１が使用されている。この金属タブ４１上の上
記半導体チップ１が装着される位置に形成された絶縁層
６と、この絶縁層６の上に積層された導体層７とによっ
て、上記バイパスコンデンサ９が形成されている。The electronic circuit device shown in the figure is configured as a packaged semiconductor integrated circuit device. To explain the difference from the above-mentioned embodiment, in this embodiment, the above-mentioned support 3
As such, a metal tab 41 is used to support the semiconductor chip 1 within the package 8. The bypass capacitor 9 is formed by the insulating layer 6 formed on the metal tab 41 at a position where the semiconductor chip 1 is mounted, and the conductor layer 7 laminated on the insulating layer 6.

これにより、パッケージ８内にバイパスコンデンサ９を
内蔵した半導体集積回路装置が構成されている。This constitutes a semiconductor integrated circuit device in which the bypass capacitor 9 is built into the package 8.

なお、第３図において、４Ａ、４Ｂは端子リード、２１
はボンディング・ワイヤーをそれぞれ示す。In addition, in Fig. 3, 4A and 4B are terminal leads, 21
indicate bonding wires, respectively.

第４図はこの発明の第３の実施例を示す。FIG. 4 shows a third embodiment of the invention.

同図に示す電子回路装置は、第１図に示したものと同様
、セラミックス基板からなる絶縁支持体３上に形成され
ている。第１図に示したものと相違するところは、半導
体チップ１は、その端子部２Ａ、２Ｂ側とは反対の底面
側が支持体３側に固着されている。そして、その半導体
チップ１の底面と支持体３の間にて、導体ランド４−絶
縁層６−導体層７によるバイパスコンデンサ９が形成さ
れている。The electronic circuit device shown in the figure is formed on an insulating support 3 made of a ceramic substrate, similar to that shown in FIG. The difference from that shown in FIG. 1 is that the semiconductor chip 1 has its bottom surface side opposite to the terminal portions 2A and 2B side fixed to the support body 3 side. A bypass capacitor 9 is formed between the bottom surface of the semiconductor chip 1 and the support 3 by a conductor land 4, an insulating layer 6, and a conductor layer 7.

この実施例では、半導体チップ１とバイパスコンデンサ
９との間の接続がワイヤー２１によって行われている。In this embodiment, the connection between the semiconductor chip 1 and the bypass capacitor 9 is made by a wire 21.

しかし、半導体チップ１とバイパスコンデンサ９が平面
的に同位置に形成されていることにより、両者間の配線
長は非常に短くてすむようになっている。これにより、
前述した実施例とほぼ同様の効果を得ることができる。However, since the semiconductor chip 1 and the bypass capacitor 9 are formed at the same position in a plane, the wiring length between them can be extremely short. This results in
Almost the same effects as in the embodiment described above can be obtained.

以上、本発明者によってなされた発明を実施例にもとづ
き具体的に説明したが、本発明は上記実施例に限定され
るものではなく、その要旨を逸脱しない範囲で種々変更
可能であることはいうまでもない。たとえば、上記バイ
パスコンデンサ９は半導体チップ１の上面に形成しても
よい。Above, the invention made by the present inventor has been specifically explained based on the examples, but it should be noted that the present invention is not limited to the above examples and can be modified in various ways without departing from the gist thereof. Not even. For example, the bypass capacitor 9 may be formed on the upper surface of the semiconductor chip 1.

以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である超高周波帯での通信
用電子回路装置に適用した場合について説明したが、そ
れに限定されるものではなく、たとえば、高速の論理機
能をもつ電子回路装置などにも適用できる。In the above explanation, the invention made by the present inventor was mainly applied to an electronic circuit device for communication in an ultra-high frequency band, which is the background field of application, but it is not limited to this, and for example, It can also be applied to electronic circuit devices with high-speed logic functions.

［発明の効果コ 本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

すなわち、比較的小容量のコンデンサでも確実なバイパ
ス効果が得られるとともに、半導体チップとバイパスコ
ンデンサの両方を比較的小さなスペース内に高密度に実
装できるようになる、という効果が得られる。That is, it is possible to obtain a reliable bypass effect even with a capacitor of relatively small capacity, and also to be able to mount both the semiconductor chip and the bypass capacitor with high density in a relatively small space.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明による技術が適用された電子回路装置
の要部における一実施例を示す断面図、第２図は第１図
に示した部分の等価回路を示す図、 第３図はこの発明の第２の実施例による電子回路装置の
要部を示す断面図、 第４図はこの発明の第３の実施例による電子回路装置の
要部を示す断面図、 第５図はこの発明に先立って検討された電子回路装置の
一部を斜視図、 第６図は第５図に示した部分の等価回路を示す図である
。 １・・・半導体チップ、２１・・・ボンディング・ワイ
ヤー、２Ａ、２Ｂ・・・半導体チップの端子部、３・・
・支持体、４・・・導体ランド、４１・・・支持体とし
ての金属タブ、５・・・導体層、６・・・絶縁層、７・
・・導体層、８・・・パッケージ、９・・・バイパスコ
ンデンサ。 第　　３　　図 第　　４　　図 ！６図FIG. 1 is a sectional view showing an embodiment of the main part of an electronic circuit device to which the technology according to the present invention is applied, FIG. 2 is a diagram showing an equivalent circuit of the part shown in FIG. 1, and FIG. FIG. 4 is a sectional view showing the main parts of an electronic circuit device according to the second embodiment of the invention, FIG. 4 is a sectional view showing the main parts of the electronic circuit device according to the third embodiment of the invention, and FIG. FIG. 6 is a perspective view of a part of the electronic circuit device previously studied, and FIG. 6 is a diagram showing an equivalent circuit of the portion shown in FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 21... Bonding wire, 2A, 2B... Terminal part of semiconductor chip, 3...
- Support, 4... Conductor land, 41... Metal tab as support, 5... Conductor layer, 6... Insulating layer, 7...
...Conductor layer, 8...Package, 9...Bypass capacitor. Figure 3 Figure 4! Figure 6

Claims (1)

【特許請求の範囲】 １、半導体チップと上記半導体チップが装着された支持
体と、上記半導体チップと電気的に接続されたコンデン
サとを有し、上記コンデンサは、積層状に形成された絶
縁層と導体層によって構成されていることを特徴とする
電子回路装置。 ２、上記支持体が絶縁性基板からなり、この絶縁性基板
上の上記半導体チップが装着される位置に形成された導
体領域と、この導体領域の上に形成された絶縁層と、こ
の絶縁層の上に積層された導体層とによって、上記コン
デンサが形成されていることを特徴とする特許請求の範
囲第１項記載の電子回路装置。 ３、上記支持体が、半導体チップをパッケージ内で支持
する金属タブであって、このタブ上の上記半導体チップ
が装着される位置に形成された絶縁層と、この絶縁層の
上に積層された導体層とによって、上記コンデンサが形
成されていることを特徴とする特許請求の範囲第１項ま
たは第２項記載の半導体集積回路装置。 ４、上記コンデンサの一方の電極をなす導体層の面に上
記半導体チップの端子部が対面状態で直接接続されてい
ることを特徴とする特許請求の範囲第１項から第３項ま
でのいずれかに記載の電子回路装置。[Claims] 1. A semiconductor chip, a support body on which the semiconductor chip is mounted, and a capacitor electrically connected to the semiconductor chip, the capacitor comprising an insulating layer formed in a laminated manner. An electronic circuit device comprising: and a conductor layer. 2. The support body is made of an insulating substrate, a conductive region formed on the insulating substrate at a position where the semiconductor chip is mounted, an insulating layer formed on the conductive region, and the insulating layer. 2. The electronic circuit device according to claim 1, wherein the capacitor is formed by a conductor layer laminated thereon. 3. The support is a metal tab that supports the semiconductor chip within the package, and an insulating layer is formed on the tab at a position where the semiconductor chip is mounted, and the insulating layer is laminated on the insulating layer. 3. The semiconductor integrated circuit device according to claim 1, wherein the capacitor is formed by a conductor layer. 4. Any one of claims 1 to 3, characterized in that the terminal portion of the semiconductor chip is directly connected to the surface of the conductor layer forming one electrode of the capacitor in a facing state. The electronic circuit device described in .
JP61146884A 1986-06-25 1986-06-25 Electronic circuit device Pending JPS634662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61146884A JPS634662A (en) 1986-06-25 1986-06-25 Electronic circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61146884A JPS634662A (en) 1986-06-25 1986-06-25 Electronic circuit device

Publications (1)

Publication Number Publication Date
JPS634662A true JPS634662A (en) 1988-01-09

Family

ID=15417752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61146884A Pending JPS634662A (en) 1986-06-25 1986-06-25 Electronic circuit device

Country Status (1)

Country Link
JP (1) JPS634662A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0376759A2 (en) * 1988-12-29 1990-07-04 Sharp Kabushiki Kaisha Liquid crystal display apparatus
WO2007029445A1 (en) * 2005-09-06 2007-03-15 Matsushita Electric Industrial Co., Ltd. Capacitor-equipped semiconductor device
WO2016031206A1 (en) * 2014-08-29 2016-03-03 パナソニックＩｐマネジメント株式会社 Semiconductor device, assembly, and vehicle

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0376759A2 (en) * 1988-12-29 1990-07-04 Sharp Kabushiki Kaisha Liquid crystal display apparatus
WO2007029445A1 (en) * 2005-09-06 2007-03-15 Matsushita Electric Industrial Co., Ltd. Capacitor-equipped semiconductor device
JPWO2007029445A1 (en) * 2005-09-06 2009-03-26 パナソニック株式会社 Capacitor-mounted semiconductor device
US7884443B2 (en) 2005-09-06 2011-02-08 Panasonic Corporation Semiconductor device having a mounting substrate with a capacitor interposed therebetween
JP4811406B2 (en) * 2005-09-06 2011-11-09 パナソニック株式会社 Capacitor-mounted semiconductor device
WO2016031206A1 (en) * 2014-08-29 2016-03-03 パナソニックＩｐマネジメント株式会社 Semiconductor device, assembly, and vehicle
JPWO2016031206A1 (en) * 2014-08-29 2017-06-15 パナソニックＩｐマネジメント株式会社 Semiconductor device, mounting body, vehicle
US10186479B2 (en) 2014-08-29 2019-01-22 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device, package, and vehicle

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