JP2001148457A - High-frequency semiconductor device - Google Patents

High-frequency semiconductor device

Info

Publication number
JP2001148457A
JP2001148457A JP33209699A JP33209699A JP2001148457A JP 2001148457 A JP2001148457 A JP 2001148457A JP 33209699 A JP33209699 A JP 33209699A JP 33209699 A JP33209699 A JP 33209699A JP 2001148457 A JP2001148457 A JP 2001148457A
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor chip
substrate
metal
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33209699A
Other languages
Japanese (ja)
Inventor
Kunihiko Kanazawa
邦彦 金澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP33209699A priority Critical patent/JP2001148457A/en
Publication of JP2001148457A publication Critical patent/JP2001148457A/en
Pending legal-status Critical Current

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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Abstract

PROBLEM TO BE SOLVED: To provide a high-frequency semiconductor device which can keep high-frequency characteristics and mounted with various semiconductor elements, which are laminated in a very small area. SOLUTION: A back electrode 7 is provided on a semiconductor chip 1, and a wiring 12 of a circuit integrated part 1 provided on a front surface is connected electrically to the back electrode 7 via a metal layer 6 provided inside a via hole 5. The semiconductor chip 1 is mounted, making its circuit integrated part 11 face upward (opposite to a multilayered board 20), and the back electrode 7 and a metal wiring 9 provided to the multilayered board 20 are connected together electrically.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、高周波用半導体装
置に関し、特に、高周波回路を設けた半導体チップと回
路基板とを電気的に接続するマルチチップ半導体実装に
適した構造の高周波半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency semiconductor device, and more particularly to a high-frequency semiconductor device having a structure suitable for multi-chip semiconductor mounting for electrically connecting a semiconductor chip provided with a high-frequency circuit to a circuit board.

【０００２】[0002]

【従来の技術】従来、半導体チップを回路基板へ実装し
た後の半導体チップと回路基板との電気的接続は、一般
に、ワイヤー接続またはバンプ接続により行われてい
た。2. Description of the Related Art Conventionally, electrical connection between a semiconductor chip and a circuit board after the semiconductor chip is mounted on the circuit board has been generally made by wire connection or bump connection.

【０００３】図５は、ワイヤー接続を用いた第一の従来
の高周波用半導体装置の概略構成を示す断面図である。
この図５において、１は半導体チップ、２はワイヤー、
３は誘電体または半導体からなる回路基板、１１は半導
体チップ１の表面に設けられた高周波増幅回路からなる
回路集積部、１２は半導体チップ１の表面に設けられた
金属配線（または電極）、１３は回路基板３上に設けら
れた金属配線である。回路基板３が誘電体からなる場
合、回路基板上３にはロジック系回路部品などの回路部
品が実装されている。また、この回路基板３が半導体か
らなる場合、それらの回路部品が半導体基板上に同様に
して実装されるか、またはそれらの部品の一部もしくは
全部が半導体製造法により半導体基板内に作り込まれ
る。半導体チップ１は、このような回路部品を搭載した
回路基板３上に、回路集積部１１を設けた面と反対側の
面を回路基板３側に向けて実装され、半導体チップ１上
の金属配線１２と回路基板３上の金属配線１３とがワイ
ヤー２により電気的に接続される。FIG. 5 is a sectional view showing a schematic structure of a first conventional high frequency semiconductor device using wire connection.
In FIG. 5, 1 is a semiconductor chip, 2 is a wire,
3 is a circuit board made of a dielectric or semiconductor, 11 is a circuit integrated part made up of a high-frequency amplifier circuit provided on the surface of the semiconductor chip 1, 12 is metal wiring (or electrode) provided on the surface of the semiconductor chip 1, 13 Is a metal wiring provided on the circuit board 3. When the circuit board 3 is made of a dielectric, circuit components such as logic circuit components are mounted on the circuit board 3. When the circuit board 3 is made of a semiconductor, the circuit components are mounted on the semiconductor substrate in the same manner, or a part or all of the components are formed in the semiconductor substrate by a semiconductor manufacturing method. . The semiconductor chip 1 is mounted on a circuit board 3 on which such a circuit component is mounted, with the surface opposite to the surface on which the circuit integrated portion 11 is provided facing the circuit board 3 side. 12 and the metal wiring 13 on the circuit board 3 are electrically connected by the wire 2.

【０００４】図６は、バンプ接続を用いた第二の従来の
高周波半導体装置の概略構成を示す断面図である。ここ
では、半導体チップ１の表面に設けられた回路集積部１
１が回路基板３側に面するように、半導体チップ１が回
路基板３に実装され、半導体チップ１上の金属配線１２
と回路基板３上の金属配線１３とがバンプ電極４により
電気的に接続される。この構造では、半導体チップ１に
おいて回路集積部１１を設けた面と反対側の面には、回
路集積部１１と電気的に接続された配線（電極）は形成
されていない。FIG. 6 is a sectional view showing a schematic configuration of a second conventional high-frequency semiconductor device using a bump connection. Here, the circuit integrated unit 1 provided on the surface of the semiconductor chip 1
The semiconductor chip 1 is mounted on the circuit board 3 such that the metal wiring 12 faces the circuit board 3 side.
And the metal wiring 13 on the circuit board 3 are electrically connected by the bump electrode 4. In this structure, no wiring (electrode) electrically connected to the circuit integrated unit 11 is formed on the surface of the semiconductor chip 1 opposite to the surface on which the circuit integrated unit 11 is provided.

【０００５】[0005]

【発明が解決しようとする課題】上述のような高周波用
半導体装置の電気的接続においては、インダクタンスの
周波数特性を小さくすることが重要である。In the electrical connection of the high-frequency semiconductor device as described above, it is important to reduce the frequency characteristics of the inductance.

【０００６】しかしながら、図５に示した第一の従来の
高周波用半導体装置では、ワイヤーのインダクタンス成
分が高周波特性を悪化させるという欠点があり、特に、
それによって利得の低下を招くという問題があった。However, the first conventional high frequency semiconductor device shown in FIG. 5 has a disadvantage that the inductance component of the wire deteriorates the high frequency characteristics.
As a result, there is a problem that the gain is reduced.

【０００７】また、図６に示した第二の従来の高周波用
半導体装置では、半導体チップ上の素子面が、半導体チ
ップが実装される誘電体基板や半導体基板に近いため
に、帰還容量が大きくなって高周波での利得低下を招く
という問題があった。In the second conventional high-frequency semiconductor device shown in FIG. 6, since the element surface on the semiconductor chip is close to the dielectric substrate or the semiconductor substrate on which the semiconductor chip is mounted, the feedback capacitance is large. As a result, there is a problem that the gain is reduced at a high frequency.

【０００８】また、ワイヤ接続技術を用いた場合には、
それぞれの半導体素子を重ねて電気接続すると、ワイヤ
ー接続用パッド電極をチップ周辺に多く設ける必要があ
り、チップ面積が非常に大きくなるという問題があっ
た。[0008] When the wire connection technique is used,
When the respective semiconductor elements are overlapped and electrically connected, it is necessary to provide a large number of wire connection pad electrodes around the chip, and there is a problem that the chip area becomes very large.

【０００９】さらに、従来の構成では、セラミック製の
容量や抵抗、インダクタ等を加えて実装することができ
なかったので、高周波特性の改善や電源ＩＣの特性改善
が困難であった。Furthermore, in the conventional configuration, it was not possible to mount a ceramic capacitor, resistor, inductor, and the like in addition, so that it was difficult to improve the high-frequency characteristics and the characteristics of the power supply IC.

【００１０】本発明は、このような従来技術の課題を解
決するためになされたものであり、高周波特性を維持す
ることができ、しかも種々の半導体素子を非常に小さい
面積で重ねて実装することが可能な高周波用半導体装置
を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve such problems of the prior art, and can maintain high-frequency characteristics and mount various semiconductor elements in a very small area. It is an object of the present invention to provide a high-frequency semiconductor device that can operate.

【００１１】[0011]

【課題を解決するための手段】上記課題を達成するため
に、本発明の高周波用半導体装置は、半導体チップの表
面に複数設けられた半導体素子の配線電極または半導体
集積回路の配線電極と、該半導体チップの裏面に設けら
れ、互いに電気的に接続されていない複数の金属電極と
が、１つの表面側の配線電極に対して１つの裏面側の金
属電極が対応して、それぞれ独立して半導体チップを貫
通する貫通穴に形成された金属層により電気的に接続さ
れ、該半導体チップの裏面の金属電極が、誘電体基板上
もしくは半導体基板上に設けられた金属配線、または金
属製リードと電気的に接続されていることを特徴とす
る。In order to achieve the above object, a high frequency semiconductor device according to the present invention comprises: a plurality of wiring electrodes of a semiconductor element or a plurality of wiring electrodes of a semiconductor integrated circuit provided on a surface of a semiconductor chip; A plurality of metal electrodes provided on the back surface of the semiconductor chip and not electrically connected to each other, and one metal electrode on the back surface corresponds to one wiring electrode on the front surface, and the semiconductor electrodes are independently formed. Electrical connection is made by a metal layer formed in a through hole penetrating the chip, and a metal electrode on the back surface of the semiconductor chip is electrically connected to a metal wiring or a metal lead provided on a dielectric substrate or a semiconductor substrate. It is characterized by being electrically connected.

【００１２】前記誘電体基板もしくは半導体基板上の金
属配線が、該誘電体基板上もしくは半導体基板上に設け
られた絶縁層より凸であってもよい。The metal wiring on the dielectric substrate or the semiconductor substrate may be more convex than the insulating layer provided on the dielectric substrate or the semiconductor substrate.

【００１３】前記半導体チップの裏面側の金属電極と、
前記誘電体基板上もしくは半導体基板上の金属配線と
が、金属により電気的に接続され、該半導体チップと、
該誘電体基板もしくは半導体基板との間隙が樹脂で埋め
られていてもよい。A metal electrode on the back side of the semiconductor chip;
The metal wiring on the dielectric substrate or the semiconductor substrate is electrically connected by metal, and the semiconductor chip,
The gap between the dielectric substrate and the semiconductor substrate may be filled with a resin.

【００１４】前記半導体チップ上に、その表面側の配線
電極および裏面側の金属電極が貫通穴に形成された金属
層により電気的に接続された別の半導体チップが配置さ
れ、下側の半導体チップの表面側の配線電極と、上側の
半導体チップの裏面側の金属電極とが電気的に接続さ
れ、下側の半導体チップの裏面側の金属電極と、前記誘
電体基板上もしくは半導体基板上に設けられた金属配
線、または金属製リードとが電気的に接続されていても
よい。On the semiconductor chip, another semiconductor chip in which wiring electrodes on the front side and metal electrodes on the back side are electrically connected by a metal layer formed in a through hole is disposed. The wiring electrode on the front surface of the semiconductor chip is electrically connected to the metal electrode on the back surface of the upper semiconductor chip, and the metal electrode on the back surface of the lower semiconductor chip is provided on the dielectric substrate or the semiconductor substrate. Metal wiring or a metal lead may be electrically connected.

【００１５】前記半導体チップ上に、その表面側の配線
電極および裏面側の金属電極が貫通穴に形成された金属
層により電気的に接続された別の半導体チップの複数が
縦積みされ、下側の半導体チップの表面側の配線電極
と、上側の半導体チップの裏面側の金属電極とが電気的
に接続され、最も下側の半導体チップの裏面側の金属電
極と、前記誘電体基板上もしくは半導体基板上に設けら
れた金属配線、または金属製リードとが電気的に接続さ
れていてもよい。On the semiconductor chip, a plurality of other semiconductor chips in which wiring electrodes on the front surface side and metal electrodes on the rear surface side are electrically connected by a metal layer formed in a through hole are vertically stacked. The wiring electrode on the front side of the semiconductor chip is electrically connected to the metal electrode on the back side of the upper semiconductor chip, and the metal electrode on the back side of the lowermost semiconductor chip is formed on the dielectric substrate or the semiconductor. A metal wiring or a metal lead provided on the substrate may be electrically connected.

【００１６】前記半導体基板もしくは誘電体基板が、セ
ラミック多層基板、樹脂多層基板または多層配線半導体
基板からなっていてもよい。[0016] The semiconductor substrate or the dielectric substrate may be a ceramic multilayer substrate, a resin multilayer substrate, or a multilayer wiring semiconductor substrate.

【００１７】前記セラミック多層基板、樹脂多層基板ま
たは多層配線半導体基板がキャビティー構造を有し、該
キャビティー構造内に前記半導体チップが配置されてい
るのが好ましい。It is preferable that the ceramic multilayer substrate, the resin multilayer substrate or the multilayer wiring semiconductor substrate has a cavity structure, and the semiconductor chip is arranged in the cavity structure.

【００１８】前記半導体チップの表面側の配線電極と、
前記セラミック多層基板、樹脂多層基板または多層配線
半導体基板の配線とが、ワイヤーを用いて電気的に接続
されていてもよい。A wiring electrode on the front side of the semiconductor chip;
The wiring of the ceramic multilayer substrate, the resin multilayer substrate, or the multilayer wiring semiconductor substrate may be electrically connected using a wire.

【００１９】前記セラミック多層基板、樹脂多層基板ま
たは多層配線半導体基板上に、セラミックまたは半導体
からなる容量、インダクタまたは抵抗が実装されていて
もよい。A capacitor, inductor or resistor made of ceramic or semiconductor may be mounted on the ceramic multilayer substrate, resin multilayer substrate or multilayer wiring semiconductor substrate.

【００２０】以下、本発明の作用について説明する。Hereinafter, the operation of the present invention will be described.

【００２１】本発明にあっては、半導体チップの裏面側
に金属電極を設けて、半導体チップを貫通する穴に形成
された金属層により表面側の配線や電極と裏面側の金属
電極を電気的に接続し、この裏面側の金属電極と半導体
基板や誘電体基板等からなる回路基板上の金属配線とを
電気的に接続している。よって、インダクタンス成分を
非常に小さくすることができ、従来に比べて高周波での
利得が２倍程度向上する。また、ワイヤー接続方法と異
なり、半導体チップ面積を小型化することが可能であ
る。また、半導体チップのどの部分からでも半導体チッ
プ裏面側の金属配線と電気的に接続でき、集積回路内の
配線の引き回しを短くすることができるので、高周波特
性や高速動作能力を大幅に改善することが可能である。
また、非常に小さい実装面積の装置を実現することが可
能である。また、バンプ技術のように半導体チップの素
子面のすぐ近くに回路基板の誘電体や金属配線が配置さ
れないので、帰還容量を形成して高周波特性が低下する
ということもない。In the present invention, a metal electrode is provided on the back side of the semiconductor chip, and the wiring and electrodes on the front side and the metal electrode on the back side are electrically connected by the metal layer formed in the hole penetrating the semiconductor chip. And electrically connects the metal electrode on the back surface to metal wiring on a circuit board made of a semiconductor substrate, a dielectric substrate, or the like. Therefore, the inductance component can be made very small, and the gain at a high frequency is improved about twice as compared with the related art. Also, unlike the wire connection method, the semiconductor chip area can be reduced. In addition, since any part of the semiconductor chip can be electrically connected to the metal wiring on the back side of the semiconductor chip and wiring of the integrated circuit can be shortened, high-frequency characteristics and high-speed operation performance can be significantly improved. Is possible.
Further, it is possible to realize a device having a very small mounting area. Further, since the dielectric or metal wiring of the circuit board is not disposed immediately near the element surface of the semiconductor chip as in the bump technique, a high-frequency characteristic is not reduced due to the formation of a feedback capacitance.

【００２２】また、誘電体基板や半導体基板等からなる
回路基板上の金属配線を、回路基板上に設けられた絶縁
層より凸に形成して、絶縁層の面よりも金属配線の上面
が突き出ているようにすることにより、半導体チップの
裏面側の電極との電気接続が容易になる。Further, the metal wiring on the circuit board composed of a dielectric substrate, a semiconductor substrate or the like is formed to be more convex than the insulating layer provided on the circuit board, and the upper surface of the metal wiring protrudes from the surface of the insulating layer. By doing so, electrical connection with the electrode on the back surface side of the semiconductor chip becomes easy.

【００２３】上記半導体チップの裏面側の金属電極と、
回路基板上の金属配線とを、金属により電気的に接続
し、半導体チップと回路基板との間隙を樹脂で埋めるこ
とにより、信頼性が向上する。A metal electrode on the back side of the semiconductor chip;
Reliability is improved by electrically connecting the metal wiring on the circuit board with a metal and filling the gap between the semiconductor chip and the circuit board with a resin.

【００２４】高周波用ガリウム砒素素子とロジック系の
シリコン素子等、電気的接続のために別のプロセスを必
要とするマルチチップ半導体実装においては、半導体チ
ップ上に、表面側の配線や電極と裏面側の金属電極が貫
通穴に形成された金属層により電気的に接続された別の
半導体チップをさらに実装し、下側の半導体チップの表
面側の配線や電極と上側の半導体チップの裏面側の金属
電極とを電気的に接続することにより、約半分の非常に
小さい面積により、半導体チップを重ねて実装可能とな
る。さらに、複数の半導体チップを縦積み実装して実装
面積を小さくすることが可能である。In a multi-chip semiconductor mounting that requires another process for electrical connection, such as a high-frequency gallium arsenide element and a logic silicon element, wiring and electrodes on the front side and electrodes on the back side are placed on the semiconductor chip. Further mounting another semiconductor chip in which metal electrodes are electrically connected by a metal layer formed in the through hole, and wiring and electrodes on the front side of the lower semiconductor chip and the metal on the back side of the upper semiconductor chip. By electrically connecting the electrodes, the semiconductor chips can be stacked and mounted with a very small area of about half. Further, it is possible to reduce the mounting area by vertically mounting a plurality of semiconductor chips.

【００２５】上記半導体基板もしくは誘電体基板とし
て、セラミック多層基板、樹脂多層基板または多層配線
半導体基板等の多層基板を用いることにより、基板の端
から遠い、中ほどにある配線電極から、その配線電極ま
で達する穴を通して直に信号を取り出すことが可能であ
る。本発明は単層の基板にも適用可能であるが、配線が
重なるため、基板側や半導体チップ側で最適配線が困難
であり、面積が大きくなってしまうので、多層基板とす
ることが好ましい。By using a multi-layer substrate such as a ceramic multi-layer substrate, a resin multi-layer substrate or a multi-layer wiring semiconductor substrate as the semiconductor substrate or the dielectric substrate, the wiring electrodes located far from the middle of the substrate and in the middle can be separated from the wiring electrodes. It is possible to take out the signal directly through the hole reaching up to. Although the present invention can be applied to a single-layer substrate, it is difficult to optimize the wiring on the substrate side or the semiconductor chip side because the wirings overlap, and the area becomes large. Therefore, a multilayer substrate is preferable.

【００２６】さらに、このセラミック多層基板、樹脂多
層基板または多層配線半導体基板にキャビティー構造を
設けて、そのキャビティー構造内に半導体チップを配置
することにより、ハンダマスクをかけることができる。
よって、基板表面に容量やインダクタ、抵抗等をはんだ
実装して大きな容量を実現し、高周波特性の向上や電源
回路の簡素化等を図ることが可能となる。Further, by providing a cavity structure in the ceramic multilayer substrate, the resin multilayer substrate or the multilayer wiring semiconductor substrate and disposing a semiconductor chip in the cavity structure, a solder mask can be applied.
Therefore, a large capacitance can be realized by soldering a capacitance, an inductor, a resistor, and the like on the surface of the substrate, and it is possible to improve high-frequency characteristics, simplify a power supply circuit, and the like.

【００２７】さらに、セラミック多層基板、樹脂多層基
板または多層配線半導体基板等の多層基板上に複数の半
導体チップを重ねて実装する場合、上側の半導体チップ
の表面側の配線電極と多層基板の金属配線とを直接電気
的に接続する必要が生じることもある。このような場
合、ワイヤーを用いてジャンパー接続することにより、
半導体チップに接続用の穴を別途形成することなく、非
常に小さい面積で実装することが可能である。Further, when a plurality of semiconductor chips are stacked and mounted on a multilayer substrate such as a ceramic multilayer substrate, a resin multilayer substrate, or a multilayer wiring semiconductor substrate, the wiring electrodes on the surface side of the upper semiconductor chip and the metal wiring of the multilayer substrate are mounted. May need to be electrically connected directly. In such a case, by jumper connection using a wire,
It is possible to mount the semiconductor chip in a very small area without separately forming a connection hole in the semiconductor chip.

【００２８】[0028]

【発明の実施の形態】以下、本発明の実施の形態につい
て、図面を参照しながら説明する。Embodiments of the present invention will be described below with reference to the drawings.

【００２９】（実施の形態１）図１（ａ）は実施の形態
１の高周波用半導体装置の構造を示す断面図であり、
（ｂ）はその平面図である。この高周波用半導体装置
は、ガリウム砒素基板またはシリコン基板からなる半導
体チップ１の表面に、高周波増幅回路からなる回路集積
部１１が設けられている。半導体チップ１にはそれを貫
通する穴であるビアホール５が形成され、そのビアホー
ル５内には金属層６が形成されている。この金属層６
は、ビアホール内に充填されていてもよく、ビアホール
５の内壁面だけに形成してもよい。さらに、半導体チッ
プ１の表面には、回路集積部１１の配線となる金属配線
１２が設けられている。この金属配線１２は、半導体チ
ップ１の裏面に設けられた金属からなる裏面電極７とビ
アホール５内に形成された金属層６を介して電気的に接
続されている。(Embodiment 1) FIG. 1A is a sectional view showing the structure of a high-frequency semiconductor device according to Embodiment 1.
(B) is a plan view thereof. In this high frequency semiconductor device, a circuit integrated unit 11 composed of a high frequency amplifier circuit is provided on the surface of a semiconductor chip 1 composed of a gallium arsenide substrate or a silicon substrate. A via hole 5 is formed in the semiconductor chip 1 as a hole therethrough, and a metal layer 6 is formed in the via hole 5. This metal layer 6
May be filled in the via hole, or may be formed only on the inner wall surface of the via hole 5. Further, on the surface of the semiconductor chip 1, a metal wiring 12 serving as a wiring of the circuit integrated unit 11 is provided. The metal wiring 12 is electrically connected to a back electrode 7 made of metal provided on the back of the semiconductor chip 1 via a metal layer 6 formed in the via hole 5.

【００３０】この半導体チップ１は、セラミック多層基
板２０の中央部に設けられた凹部２２内に、半導体チッ
プ１の裏面をセラミック多層基板２０側に配して搭載さ
れている。そして、セラミック多層基板２０上に設けら
れた金属配線９は、接続金属１０により半導体チップ１
の裏面電極７と電気的に接続されている。The semiconductor chip 1 is mounted in a concave portion 22 provided at the center of the ceramic multilayer substrate 20 with the back surface of the semiconductor chip 1 disposed on the ceramic multilayer substrate 20 side. The metal wiring 9 provided on the ceramic multilayer substrate 20 is connected to the semiconductor chip 1 by the connection metal 10.
Is electrically connected to the back surface electrode 7 of FIG.

【００３１】セラミック多層基板２０には金属からなる
セラミック内層配線２１が設けられ、この内層配線２１
は、セラミック多層基板２０の凹部２２の外周部に搭載
した容量、抵抗またはインダクタ等の電子部品２３と電
気的に接続している。セラミック多層基板２０の凹部２
２はキャビティー構造であり、半導体チップ１を保護し
てハンダマスクをかけられるようにする封止樹脂２５が
凹部２２の開口部にかかっている。このため、容量、抵
抗またはインダクタ等の電子部品２３をセラミック多層
基板２０の凹部の外周部に実装して、非常に大きな容量
やＱ値の高いインダクタを実現することができる。The ceramic multilayer substrate 20 is provided with a ceramic inner layer wiring 21 made of metal.
Are electrically connected to an electronic component 23 such as a capacitor, a resistor, or an inductor mounted on the outer peripheral portion of the concave portion 22 of the ceramic multilayer substrate 20. Concave part 2 of ceramic multilayer substrate 20
Reference numeral 2 denotes a cavity structure, in which a sealing resin 25 for protecting the semiconductor chip 1 and applying a solder mask is applied to the opening of the recess 22. For this reason, an electronic component 23 such as a capacitor, a resistor, or an inductor can be mounted on the outer peripheral portion of the concave portion of the ceramic multilayer substrate 20 to realize an inductor having a very large capacity and a high Q value.

【００３２】半導体チップ１の回路集積部１１として
は、高周波用増幅器としてのガリウム砒素電界効果トラ
ンジスタまたはバイポーラトランジスタ等を用いること
ができる。ビアホール５内の金属層６としては、金、銅
またはアルミニウムを用いることにより低抵抗を実現す
ることができる。半導体チップ１の裏面電極７と表面側
の金属配線（または電極）１２との接続は、金で行うか
錫を含むハンダで行うことができる。As the circuit integrated portion 11 of the semiconductor chip 1, a gallium arsenide field effect transistor or a bipolar transistor as a high frequency amplifier can be used. Low resistance can be realized by using gold, copper or aluminum as the metal layer 6 in the via hole 5. The connection between the back surface electrode 7 of the semiconductor chip 1 and the metal wiring (or electrode) 12 on the front side can be made with gold or with solder containing tin.

【００３３】この構成によれば、半導体チップ１の表面
に設けた高周波増幅回路からなる回路集積部１１が、セ
ラミック多層基板２０側とは反対の面に配置されている
ので、回路集積部１１とセラミック多層基板２０との間
で帰還容量を形成することがない。よって、帰還容量の
増大を防止することができ、高周波での利得低下を起こ
すのを防ぐことができる。また、半導体チップ１を貫通
するビアホール５に形成された金属層６により電気的に
接続しているので、非常にインダクタンス成分を小さく
することができ、高周波での利得を２倍程度向上するこ
とができる。また、ワイヤー技術を用いて電気的接続を
行っていないので、非常に小さい半導体実装面積を実現
することができる。さらに、容量、抵抗またはインダク
タ等の電子部品２３を実装することができるので、非常
に大きな容量やＱ値の高いインダクタを実現でき、高周
波特性や電源としての特性を非常に向上することができ
る。According to this configuration, the circuit integrated section 11 composed of the high-frequency amplifier circuit provided on the surface of the semiconductor chip 1 is arranged on the surface opposite to the ceramic multilayer substrate 20 side. No feedback capacitance is formed with the ceramic multilayer substrate 20. Therefore, an increase in the feedback capacitance can be prevented, and a decrease in gain at a high frequency can be prevented. Further, since the electrical connection is made by the metal layer 6 formed in the via hole 5 penetrating the semiconductor chip 1, the inductance component can be extremely reduced, and the gain at high frequency can be improved about twice. it can. Further, since the electrical connection is not performed using the wire technology, a very small semiconductor mounting area can be realized. Further, since an electronic component 23 such as a capacitance, a resistor, or an inductor can be mounted, a very large capacitance and an inductor with a high Q value can be realized, and the high-frequency characteristics and the characteristics as a power supply can be greatly improved.

【００３４】なお、回路基板としては、セラミック多層
基板２０のかわりに、樹脂多層基板や多層配線半導体基
板等の多層基板を用いることもできる。このような多層
基板を用いた場合、内層配線２１に達する穴２１ａを通
して内層配線２１から直に信号を取り出すことができ
る。本発明は、単層の基板についても適用可能である
が、多層基板の方が基板側や半導体チップ側で最適配線
が容易であり、面積も縮小することができる。As the circuit board, instead of the ceramic multilayer substrate 20, a multilayer substrate such as a resin multilayer substrate or a multilayer wiring semiconductor substrate can be used. When such a multilayer substrate is used, a signal can be directly extracted from the inner layer wiring 21 through the hole 21a reaching the inner layer wiring 21. The present invention can be applied to a single-layer substrate, but a multilayer substrate allows easier optimal wiring on the substrate side or semiconductor chip side and can reduce the area.

【００３５】また、回路基板上の金属配線９のかわり
に、従来の樹脂リードパッケージにおける金属リードを
用いることもできる。In place of the metal wiring 9 on the circuit board, a metal lead in a conventional resin lead package can be used.

【００３６】さらに、半導体チップの接続強度向上のた
めに、半導体チップの裏面電極が裏面側の誘電体または
半導体基板上の金属配線間、あるいは金属製リード間を
金属で接続し、半導体チップと裏面側の誘電体または半
導体との間隙を樹脂で埋めると信頼性を向上することが
できる。これは、衝撃力や、温度変化に対して熱膨張率
の違いから生じる応力が、接続金属部分に集中するのを
防ぐことができるからである。Further, in order to improve the connection strength of the semiconductor chip, the back electrode of the semiconductor chip is connected between the metal wiring on the back surface side dielectric or the semiconductor substrate or between the metal leads by metal, and the semiconductor chip and the back surface are connected. If the gap between the dielectric and the semiconductor on the side is filled with a resin, the reliability can be improved. This is because an impact force and a stress generated due to a difference in thermal expansion coefficient with respect to a temperature change can be prevented from being concentrated on the connecting metal portion.

【００３７】さらに、図２に示すように、回路基板上の
金属配線の上面を、その回路基板上に設けた絶縁層の面
よりも突出させるようにすれば、半導体チップの裏面電
極をその金属配線と適切に接続させることができ、不所
望な箇所での電気接続を避けることができる。この場
合、金属配線の上面が絶縁層の面よりも上に突出してい
れば、図２（ａ）に示すように、金属配線を絶縁層の上
に形成してもよく、図２（ｂ）に示すように、金属配線
が絶縁層から一部露出していてもよい。Further, as shown in FIG. 2, if the upper surface of the metal wiring on the circuit board is made to protrude beyond the surface of the insulating layer provided on the circuit board, the back electrode of the semiconductor chip can be It can be appropriately connected to the wiring, and electrical connection at an undesired portion can be avoided. In this case, if the upper surface of the metal wiring protrudes above the surface of the insulating layer, the metal wiring may be formed on the insulating layer as shown in FIG. As shown in (1), the metal wiring may be partially exposed from the insulating layer.

【００３８】（実施の形態２）本実施の形態２では、半
導体チップ上に、さらに別の半導体チップを実装した構
成について説明する。(Embodiment 2) In Embodiment 2, a configuration in which another semiconductor chip is mounted on a semiconductor chip will be described.

【００３９】図３は、実施の形態２の高周波用半導体装
置の概略構成を示す断面図である。この高周波用半導体
装置において、第１の半導体チップ１は、シリコン素子
からなるロジック系等の回路素子であり、その上に重ね
て搭載した第２の半導体チップ１４は、ガリウム砒素素
子からなる高周波増幅回路素子である。FIG. 3 is a sectional view showing a schematic configuration of a high-frequency semiconductor device according to the second embodiment. In this high-frequency semiconductor device, the first semiconductor chip 1 is a circuit element such as a logic system composed of a silicon element, and the second semiconductor chip 14 mounted thereon is a high-frequency amplifier composed of a gallium arsenide element. Circuit element.

【００４０】第１の半導体チップ１の表面にはロジック
系等の回路からなる回路集積部１１が設けられ、第２の
半導体チップ１４の表面には高周波増幅回路からなる回
路集積部１１が設けられている。第１の半導体チップ１
と第２の半導体チップ１４内にはそれらをそれぞれ貫通
するビアホール５が設けられ、そのビアホール５内には
金属層６が形成されている。そして、第１の半導体チッ
プ１と第２の半導体チップ１４のそれぞれの表面には回
路集積部１１の配線となる金属配線１２が設けられてい
る。これらの金属配線１２は、第１の半導体チップ１と
第２の半導体チップ１４のそれぞれの裏面に設けられた
金属からなる裏面電極７と、ビアホール５内に形成され
た金属層６を介して電気的に接続されている。On the surface of the first semiconductor chip 1 is provided a circuit integrated unit 11 composed of a circuit such as a logic system, and on the surface of the second semiconductor chip 14 is provided a circuit integrated unit 11 composed of a high-frequency amplifier circuit. ing. First semiconductor chip 1
The second semiconductor chip 14 is provided with a via hole 5 penetrating them, and a metal layer 6 is formed in the via hole 5. Further, a metal wiring 12 serving as a wiring of the circuit integrated unit 11 is provided on each surface of the first semiconductor chip 1 and the second semiconductor chip 14. These metal wirings 12 are electrically connected via a back electrode 7 made of metal provided on the back surface of each of the first semiconductor chip 1 and the second semiconductor chip 14 and a metal layer 6 formed in the via hole 5. Connected.

【００４１】第１の半導体チップ１は、セラミック多層
基板２０の中央部に設けられた凹部２２内に、半導体チ
ップ１の裏面をセラミック多層基板２０側に配して搭載
されている。また、第２の半導体チップ１４は、第１の
半導体チップ１上に第２の半導体チップ１４の裏面を第
１の半導体チップ１側に配して搭載されている。そし
て、第１の半導体チップ１が実装されているセラミック
多層基板２０の凹部２２部分の表面上には金属配線９が
設けられている。この金属配線９と第１の半導体チップ
１の裏面電極７との電気的接続、および第１の半導体チ
ップ１の表面側の金属配線１２と第２の半導体チップ１
４の裏面電極７との電気的接続は、接続金属１０により
行われている。The first semiconductor chip 1 is mounted in a concave portion 22 provided at the center of the ceramic multilayer substrate 20 with the back surface of the semiconductor chip 1 disposed on the ceramic multilayer substrate 20 side. In addition, the second semiconductor chip 14 is mounted on the first semiconductor chip 1 with the back surface of the second semiconductor chip 14 disposed on the first semiconductor chip 1 side. The metal wiring 9 is provided on the surface of the concave portion 22 of the ceramic multilayer substrate 20 on which the first semiconductor chip 1 is mounted. The electrical connection between the metal wiring 9 and the back electrode 7 of the first semiconductor chip 1 and the metal wiring 12 on the front side of the first semiconductor chip 1 and the second semiconductor chip 1
4 is electrically connected to the back electrode 7 by a connection metal 10.

【００４２】この構成によれば、セラミック多層基板２
０の凹部２２内に、ロジック系等の回路素子からなる半
導体チップ１が搭載され、その半導体チップ１上に、高
周波増幅回路素子からなる第２の半導体チップ１４がそ
の回路集積部１１を上面にして搭載されているので、半
導体チップ１４表面の高周波増幅回路からなる回路集積
部１１は、近傍に半導体基板や誘電体であるセラミック
多層基板が存在しない。よって、帰還容量の増大を防止
することができ、高周波での利得低下を起こすのを防ぐ
ことができる。また、半導体チップ１上に別の半導体チ
ップ１４をさらに実装して、別の半導体チップ１４に形
成されたビアホール５内にある金属層６を用いて下の半
導体チップ１に電気的に接続しているので、非常に小さ
い面積で複数の半導体チップを重ねて実装することがで
きる。ワイヤー技術でマルチチップを縦積みした場合に
比べて約半分の実装面積にすることができる。また、上
側の半導体チップ１４として高周波用ガリウム砒素素子
を用い、下側の半導体チップ１としてロジック系のシリ
コン素子等として用いたマルチチップ構造にすることに
よって、非常に小さい実装面積で、最高の高周波特性と
多機能を得ることができる。さらに、キャビティー構造
２２の中に半導体チップを実装するため、ハンダマスク
をかけることが容易で、容量、抵抗またはインダクタ等
の電子部品２３を実装することができ、非常に大きな容
量やＱ値の高いインダクタを実現することができる。According to this configuration, the ceramic multilayer substrate 2
The semiconductor chip 1 made of a circuit element such as a logic system is mounted in the recess 22 of the “0”, and a second semiconductor chip 14 made of a high-frequency amplifier circuit element is placed on the semiconductor chip 1 with its circuit integrated part 11 facing upward. Since the circuit integrated portion 11 composed of the high-frequency amplifier circuit on the surface of the semiconductor chip 14 does not have a semiconductor substrate or a ceramic multi-layer substrate as a dielectric material in the vicinity. Therefore, an increase in the feedback capacitance can be prevented, and a decrease in gain at a high frequency can be prevented. Further, another semiconductor chip 14 is further mounted on the semiconductor chip 1, and is electrically connected to the lower semiconductor chip 1 by using the metal layer 6 in the via hole 5 formed in the other semiconductor chip 14. Therefore, a plurality of semiconductor chips can be stacked and mounted in a very small area. The mounting area can be reduced to about half as compared with the case where multiple chips are stacked vertically by wire technology. Also, by using a multi-chip structure in which a high-frequency gallium arsenide element is used as the upper semiconductor chip 14 and a logic-type silicon element or the like is used as the lower semiconductor chip 1, a very small mounting area and the highest high-frequency Features and multi-functionality can be obtained. Furthermore, since a semiconductor chip is mounted in the cavity structure 22, it is easy to apply a solder mask, and an electronic component 23 such as a capacitor, a resistor or an inductor can be mounted. A high inductor can be realized.

【００４３】本技術によれば、ロジックマイコン半導体
チップ上にメモリーチップを実装可能であり、メモリー
チップを縦積みすることにより、大きなメモリー容量を
小さい面積で実現することできる。さらに、電源用ＩＣ
や高周波半導体素子等、異なるプロセスを必要とする半
導体チップも同時に縦積み実装することが可能であり、
容量、抵抗またはインダクタ等も実装可能である。よっ
て、あらゆる分野の電子機器を、非常に小さい面積で実
装することが可能な画期的な技術である。According to the present technology, a memory chip can be mounted on a logic microcomputer semiconductor chip, and a large memory capacity can be realized in a small area by vertically stacking memory chips. Furthermore, power supply IC
Semiconductor chips that require different processes, such as high-frequency and high-frequency semiconductor elements, can be mounted vertically at the same time.
A capacitance, a resistor, an inductor, or the like can be mounted. Therefore, this is a revolutionary technology that can mount electronic devices in all fields with a very small area.

【００４４】（実施の形態３）図４は、実施の形態３の
高周波用半導体装置の概略構成を示す断面図である。(Embodiment 3) FIG. 4 is a sectional view showing a schematic configuration of a high-frequency semiconductor device according to Embodiment 3.

【００４５】この高周波用半導体装置は、実施の形態２
と同様に、半導体チップ１上に別の半導体チップ１４が
重ねて実装されている。各半導体チップ１、１４は、各
々表面側の金属配線１２と裏面電極７とがビアホール５
内に形成された金属層６により接続されている。これら
の半導体チップ１、１４はセラミック多層基板２０内の
凹部２２に実装され、セラミック多層基板２０の金属配
線９と第１の半導体チップ１の裏面電極７との電気的接
続、および第１の半導体チップ１の表面側の金属配線１
２と第２の半導体チップ１４の裏面電極７との電気的接
続は、接続金属１０により行われている。さらに、この
高周波用半導体装置では、セラミック多層基板２０の配
線９ａとがワイヤー２４により電気的に接続されてい
る。This high-frequency semiconductor device is similar to that of the second embodiment.
Similarly, another semiconductor chip 14 is mounted on the semiconductor chip 1 in an overlapping manner. In each of the semiconductor chips 1 and 14, the metal wiring 12 on the front side and the back electrode 7 are formed in the via holes 5 respectively.
Are connected by a metal layer 6 formed therein. These semiconductor chips 1 and 14 are mounted in the recesses 22 in the ceramic multilayer substrate 20, and electrically connect the metal wiring 9 of the ceramic multilayer substrate 20 to the back electrode 7 of the first semiconductor chip 1 and the first semiconductor chip. Metal wiring 1 on the front side of chip 1
The electrical connection between the second semiconductor chip 14 and the back electrode 7 of the second semiconductor chip 14 is made by a connection metal 10. Further, in this high frequency semiconductor device, the wires 9 a of the ceramic multilayer substrate 20 are electrically connected by wires 24.

【００４６】この構成によれば、多層基板２０と半導体
チップ１４を直接接続する必要がある場合であっても、
ワイヤー２４でジャンパー接続することにより、半導体
チップ１に接続用の穴を別途形成する必要がない。よっ
て、非常に小さい面積で複数の半導体チップを重ねて実
装することができる。According to this structure, even when it is necessary to directly connect the multilayer substrate 20 and the semiconductor chip 14,
By making a jumper connection with the wire 24, it is not necessary to separately form a connection hole in the semiconductor chip 1. Therefore, a plurality of semiconductor chips can be mounted on each other with a very small area.

【００４７】なお、この場合のワイヤー２４は、インダ
クタとして設計する。すなわち、ワイヤーを回路の一部
として使用しても良いところにのみ用い、従来のように
インダクタ成分に影響を与えないようにする。In this case, the wire 24 is designed as an inductor. That is, the wire is used only where it may be used as a part of the circuit, so that the inductor component is not affected unlike the related art.

【００４８】[0048]

【発明の効果】以上詳述したように、本発明によれば、
従来の半導体実装方法では得ることのできなかった高周
波特性の利得や、従来には無かった超小型の実装面積を
実現することができ、さらに、多機能特性を有する高周
波用半導体装置を得ることができる。As described in detail above, according to the present invention,
It is possible to realize a gain of high-frequency characteristics that could not be obtained by the conventional semiconductor mounting method, an ultra-small mounting area that has never been obtained, and to obtain a high-frequency semiconductor device having multifunctional characteristics. it can.

【００４９】また、本発明によれば、ロジックマイコン
半導体上にメモリーチップを実装することも可能であ
り、メモリーチップを縦積みすることにより、大きなメ
モリー容量を小さい面積で実現することができる。さら
に、電源用ＩＣや高周波半導体等素子、異なるプロセス
の半導体チップも同時に縦積みで実装することができる
ため、あらゆる分野の電子機器を非常に小さい面積で実
装することが可能な高周波用半導体装置を実現すること
ができる。According to the present invention, a memory chip can be mounted on a logic microcomputer semiconductor, and a large memory capacity can be realized in a small area by vertically stacking memory chips. Furthermore, since a power supply IC, a high-frequency semiconductor element, and a semiconductor chip of a different process can be simultaneously mounted vertically, a high-frequency semiconductor device capable of mounting electronic devices in various fields with a very small area can be provided. Can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図１】（ａ）は実施の形態１の高周波用半導体装置の
概略構成を示す断面図であり、（ｂ）はその平面図であ
る。FIG. 1A is a cross-sectional view illustrating a schematic configuration of a high-frequency semiconductor device according to a first embodiment, and FIG. 1B is a plan view thereof.

【図２】（ａ）および（ｂ）は、実施の形態における回
路基板上の金属配線の他の配置例を示す断面図である。FIGS. 2A and 2B are cross-sectional views illustrating another example of the arrangement of metal wiring on a circuit board according to the embodiment.

【図３】実施の形態２の高周波用半導体装置の概略構成
を示す断面図である。FIG. 3 is a sectional view illustrating a schematic configuration of a high-frequency semiconductor device according to a second embodiment;

【図４】実施の形態３の高周波用半導体装置の概略構成
を示す断面図である。FIG. 4 is a cross-sectional view illustrating a schematic configuration of a high-frequency semiconductor device according to a third embodiment;

【図５】従来の高周波用半導体装置の概略構成を示す断
面図である。FIG. 5 is a sectional view showing a schematic configuration of a conventional high frequency semiconductor device.

【図６】従来の高周波用半導体装置の概略構成を示す断
面図である。FIG. 6 is a sectional view showing a schematic configuration of a conventional high frequency semiconductor device.

【符号の説明】[Explanation of symbols]

１、１４ 半導体チップ ２、２４ ワイヤー ３ 回路基板 ４ バンプ電極 ５ ビアホール ６ ビアホール内に形成された金属層 ７ 半導体チップの裏面電極 ９、１３ 回路基板上に設けられた金属配線 ９ａ 回路基板の配線 １１ 回路集積部 １２ 半導体チップ表面に設けられた配線金属 ２０ セラミック多層基板 ２１ 内層配線 ２１ａ 内層配線に達する穴 ２２ 凹部 ２３ 電子部品 ２５ 封止樹脂 DESCRIPTION OF SYMBOLS 1, 14 Semiconductor chip 2, 24 Wire 3 Circuit board 4 Bump electrode 5 Via hole 6 Metal layer formed in via hole 7 Back electrode of semiconductor chip 9, 13 Metal wiring provided on circuit board 9a Circuit board wiring 11 Circuit integrated part 12 Wiring metal provided on semiconductor chip surface 20 Ceramic multilayer substrate 21 Inner layer wiring 21a Hole reaching inner layer wiring 22 Depression 23 Electronic component 25 Sealing resin

Claims (9)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップの表面に複数設けられた半
導体素子の配線電極または半導体集積回路の配線電極
と、該半導体チップの裏面に設けられ、互いに電気的に
接続されていない複数の金属電極とが、１つの表面側の
配線電極に対して１つの裏面側の金属電極が対応して、
それぞれ独立して半導体チップを貫通する貫通穴に形成
された金属層により電気的に接続され、該半導体チップ
の裏面側の金属電極が、誘電体基板上もしくは半導体基
板上に設けられた金属配線、または金属製リードと電気
的に接続されていることを特徴とする高周波用半導体装
置。1. A plurality of wiring electrodes of a semiconductor element or a wiring electrode of a semiconductor integrated circuit provided on a front surface of a semiconductor chip, and a plurality of metal electrodes provided on a back surface of the semiconductor chip and not electrically connected to each other. However, one metal electrode on the back side corresponds to one wiring electrode on the front side,
Electrically connected by a metal layer formed in a through hole independently penetrating the semiconductor chip, and a metal electrode on the back side of the semiconductor chip is provided on a dielectric substrate or a semiconductor substrate; Alternatively, a high-frequency semiconductor device electrically connected to a metal lead. 【請求項２】 前記誘電体基板上もしくは半導体基板上
の金属配線が、該誘電体基板上もしくは半導体基板上に
設けられた絶縁層より凸であることを特徴とする請求項
１に記載の高周波用半導体装置。2. The high-frequency device according to claim 1, wherein the metal wiring on the dielectric substrate or the semiconductor substrate is more convex than an insulating layer provided on the dielectric substrate or the semiconductor substrate. For semiconductor devices. 【請求項３】 前記半導体チップの裏面側の金属電極
と、前記誘電体基板上もしくは半導体基板上の金属配線
とが、金属により電気的に接続され、該半導体チップ
と、該誘電体基板もしくは半導体基板との間隙が樹脂で
埋められていることを特徴とする請求項１または請求項
２に記載の高周波用半導体装置。3. A metal electrode on a back surface side of the semiconductor chip and a metal wiring on the dielectric substrate or the semiconductor substrate are electrically connected by a metal, and the semiconductor chip is connected to the dielectric substrate or the semiconductor. The high-frequency semiconductor device according to claim 1, wherein a gap between the substrate and the substrate is filled with a resin. 【請求項４】 前記半導体チップ上に、その表面側の配
線電極および裏面側の金属電極が貫通穴に形成された金
属層により電気的に接続された別の半導体チップが配置
され、下側の半導体チップの表面側の配線電極と、上側
の半導体チップの裏面側の金属電極とが電気的に接続さ
れ、下側の半導体チップの裏面側の金属電極と、前記誘
電体基板上もしくは半導体基板上に設けられた金属配
線、または金属製リードとが電気的に接続されているこ
とを特徴とする請求項１乃至請求項３のいずれかに記載
の高周波用半導体装置。4. A semiconductor chip in which a wiring electrode on the front side and a metal electrode on the back side are electrically connected by a metal layer formed in a through hole on the semiconductor chip, The wiring electrodes on the front side of the semiconductor chip and the metal electrodes on the back side of the upper semiconductor chip are electrically connected to each other, and the metal electrodes on the back side of the lower semiconductor chip and on the dielectric substrate or the semiconductor substrate. 4. The high-frequency semiconductor device according to claim 1, wherein a metal wire or a metal lead provided in the semiconductor device is electrically connected. 【請求項５】 前記半導体チップ上に、その表面側の配
線電極および裏面側の金属電極が貫通穴に形成された金
属層により電気的に接続された別の半導体チップの複数
が縦積みされ、下側の半導体チップの表面側の配線電極
と、上側の半導体チップの裏面側の金属電極とが電気的
に接続され、最も下側の半導体チップの裏面側の金属電
極と、前記誘電体基板上もしくは半導体基板上に設けら
れた金属配線、または金属製リードとが電気的に接続さ
れていることを特徴とする請求項１乃至請求項３のいず
れかに記載の高周波用半導体装置。5. A plurality of other semiconductor chips in which a wiring electrode on a front surface side and a metal electrode on a rear surface side are electrically connected by a metal layer formed in a through hole are vertically stacked on the semiconductor chip, A wiring electrode on the front side of the lower semiconductor chip and a metal electrode on the back side of the upper semiconductor chip are electrically connected to each other, and the metal electrode on the back side of the lowermost semiconductor chip is formed on the dielectric substrate. 4. The high-frequency semiconductor device according to claim 1, wherein a metal wiring or a metal lead provided on the semiconductor substrate is electrically connected. 【請求項６】 前記半導体基板もしくは誘電体基板が、
セラミック多層基板、樹脂多層基板または多層配線半導
体基板からなる請求項１乃至請求項５のいずれかに記載
の高周波用半導体装置。6. The semiconductor substrate or the dielectric substrate,
6. The high-frequency semiconductor device according to claim 1, comprising a ceramic multilayer substrate, a resin multilayer substrate, or a multilayer wiring semiconductor substrate. 【請求項７】 前記セラミック多層基板、樹脂多層基板
または多層配線半導体基板がキャビティー構造を有し、
該キャビティー構造内に前記半導体チップが配置されて
いることを特徴とする請求項６に記載の高周波用半導体
装置。7. The ceramic multilayer substrate, the resin multilayer substrate or the multilayer wiring semiconductor substrate has a cavity structure,
7. The high-frequency semiconductor device according to claim 6, wherein the semiconductor chip is arranged in the cavity structure. 【請求項８】 さらに、前記半導体チップの表面側の配
線電極と、前記セラミック多層基板、樹脂多層基板また
は多層配線半導体基板の配線とが、ワイヤーを用いて電
気的に接続されていることを特徴とする請求項６または
請求項７に記載の高周波用半導体装置。8. The semiconductor device according to claim 8, wherein the wiring electrodes on the front surface side of the semiconductor chip and the wiring of the ceramic multilayer substrate, the resin multilayer substrate or the multilayer wiring semiconductor substrate are electrically connected by using wires. The high-frequency semiconductor device according to claim 6 or 7, wherein 【請求項９】 前記セラミック多層基板、樹脂多層基板
または多層配線半導体基板上に、セラミックまたは半導
体からなる容量、インダクタまたは抵抗が実装されてい
ることを特徴とする請求項６乃至請求項８のいずれかに
記載の高周波用半導体装置。9. The ceramic multilayer substrate, resin multilayer substrate or multilayer wiring semiconductor substrate, wherein a capacitor, inductor or resistor made of ceramic or semiconductor is mounted. A high-frequency semiconductor device according to any one of the above.
JP33209699A 1999-11-22 1999-11-22 High-frequency semiconductor device Pending JP2001148457A (en)

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US6982487B2 (en) 2003-03-25 2006-01-03 Samsung Electronics Co., Ltd. Wafer level package and multi-package stack
KR100572737B1 (en) 2002-11-29 2006-04-24 가부시끼가이샤 르네사스 테크놀로지 Semiconductor device and method of manufacturing the same
JP2006147869A (en) * 2004-11-19 2006-06-08 Oki Electric Ind Co Ltd Substrate with built-in element, and its manufacturing method
JP2007103466A (en) * 2005-09-30 2007-04-19 Toshiba Corp Multilayered printed circuit board and its manufacturing method, and electronic apparatus
US7425747B2 (en) 2003-08-05 2008-09-16 Matsushita Electric Industrial Co., Ltd. Semiconductor device
CN102308435A (en) * 2009-02-25 2012-01-04 京瓷株式会社 High-frequency model

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100572737B1 (en) 2002-11-29 2006-04-24 가부시끼가이샤 르네사스 테크놀로지 Semiconductor device and method of manufacturing the same
US7335592B2 (en) 2003-03-25 2008-02-26 Samsung Electronics Co., Ltd. Wafer level package, multi-package stack, and method of manufacturing the same
US6982487B2 (en) 2003-03-25 2006-01-03 Samsung Electronics Co., Ltd. Wafer level package and multi-package stack
US7425747B2 (en) 2003-08-05 2008-09-16 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US8381394B2 (en) 2004-11-19 2013-02-26 Oki Semiconductor Co., Ltd. Circuit board with embedded component and method of manufacturing same
US7989706B2 (en) 2004-11-19 2011-08-02 Oki Semiconductor Co., Ltd. Circuit board with embedded component and method of manufacturing same
JP2006147869A (en) * 2004-11-19 2006-06-08 Oki Electric Ind Co Ltd Substrate with built-in element, and its manufacturing method
JP2007103466A (en) * 2005-09-30 2007-04-19 Toshiba Corp Multilayered printed circuit board and its manufacturing method, and electronic apparatus
CN102308435A (en) * 2009-02-25 2012-01-04 京瓷株式会社 High-frequency model
DE112010000886T5 (en) 2009-02-25 2012-05-10 Kyocera Corp. RF module
CN102308435B (en) * 2009-02-25 2014-07-30 京瓷株式会社 High-frequency module
US8854152B2 (en) 2009-02-25 2014-10-07 Kyocera Corporation High-frequency module including a conductor with a slot therein and a conductive wire crossing over the slot and physically contacting the conductor
DE112010000886B4 (en) 2009-02-25 2017-06-01 Kyocera Corp. RF module

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