JPS62109332A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS62109332A
JPS62109332A JP25020785A JP25020785A JPS62109332A JP S62109332 A JPS62109332 A JP S62109332A JP 25020785 A JP25020785 A JP 25020785A JP 25020785 A JP25020785 A JP 25020785A JP S62109332 A JPS62109332 A JP S62109332A
Authority
JP
Japan
Prior art keywords
conductor
pattern
collector
hybrid integrated
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25020785A
Other languages
Japanese (ja)
Inventor
Kazuyoshi Kamimura
上村　和義
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP25020785A priority Critical patent/JPS62109332A/en
Publication of JPS62109332A publication Critical patent/JPS62109332A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To reduce the irregularity of characteristics due to the irregularity of the mounting position of a bridge used as characteristics improvement of a transistor by replacing the bridge with a conductor pattern on a substrate. CONSTITUTION:A transistor chip 3 is mounted on part of a conductor pattern formed on an insulating substrate 1, and connected with other part of the pattern by metal wirings. For example, a collector-grounded transistor pellet 3 is mounted on a conductor 8 (collector land) formed on the substrate, and a base electrode 11 of the pellet 3 is connected with a conductor 9 (base pattern) by wirings 6. A grounding conductor 4 (emitter pattern) is constructed to surround the conductor 8 (collector land), and an emitter electrode 12 is bonded by metal wirings 5 to different points 4, 4'' of the conductor 4 (emitter pattern). The conductor 8 is connected by metal wirings 7 with the conductor 2 (collector pattern).

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、トランジスタチップが絶縁基板上に形成され
た導体パターン上にマウントされている構造を有する混
成集積回路に関し、特にトランジスタ回路の接地インダ
クタンスを軽減することを可能にした混成集積回路に関
する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a hybrid integrated circuit having a structure in which a transistor chip is mounted on a conductor pattern formed on an insulating substrate, and in particular, the present invention relates to a hybrid integrated circuit having a structure in which a transistor chip is mounted on a conductive pattern formed on an insulating substrate. This invention relates to a hybrid integrated circuit that makes it possible to reduce the

〔従来の技術〕[Conventional technology]

周知の様にトランジスタの接地インダクタンスとトラン
ジスタの利得には、関係があり、接地インダクタンスが
少回路構成はど高い利得が得られる。従って、高利得を
得ようとする回路構成ではトランジスタの接地インダク
タンスを少なくする必要がある。As is well known, there is a relationship between the ground inductance of a transistor and the gain of the transistor, and a circuit configuration with a small ground inductance can provide a high gain. Therefore, in a circuit configuration in which high gain is to be obtained, it is necessary to reduce the ground inductance of the transistor.

第２図（ａｌ〜（Ｃ１は、このような高利得を目的とす
る混成集積回路の一実施例で、コレクタ接地のトランジ
スタペレットをエミッタ接地の回路で使用している。第
２図で、セラミック基板ｌ上に形成された導体部２（コ
レクタパターン）上にトランジスタペレット３がマウン
トされ、前記トランジスタペレット３上のベース電極１
１は金属ワイヤ６により導体部９（ペースパターン）に
接続されている。又、エミッタ′ｄＬ極１２は、金属ワ
イヤ５により、接地導体４（エミッタパターン）及び前
記接地導体にロウ付された金属橋（以下、ブリッジと記
す）に接続されている。従って、エミッタの接地ワイヤ
（金属ワイヤ５）は電極１つあたりペレットの前後２本
、すなわち基板の接地導体４とブリッジ１０とにボンデ
ィングされていて、第３図のブリッジを使わない回路に
比べて、接地インダクタンスは約１／２近く減らすこと
ができる。Figure 2 (al~(C1) is an example of a hybrid integrated circuit aiming at such a high gain, in which a transistor pellet with a common collector is used in a circuit with a common emitter. A transistor pellet 3 is mounted on a conductor portion 2 (collector pattern) formed on a substrate l, and a base electrode 1 on the transistor pellet 3 is mounted.
1 is connected to a conductor portion 9 (pace pattern) by a metal wire 6. The emitter 'dL pole 12 is connected by a metal wire 5 to a ground conductor 4 (emitter pattern) and a metal bridge (hereinafter referred to as a bridge) brazed to the ground conductor. Therefore, the ground wire (metal wire 5) of the emitter is bonded to the two wires on the front and back of the pellet per electrode, that is, to the ground conductor 4 of the board and the bridge 10, compared to the circuit without a bridge shown in FIG. , the grounding inductance can be reduced by about 1/2.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の混成集積回路では、トランジスタペレッ
トの他にブリッジをマウントしな（てはならない。しか
るに、マウント位置精度には、限界があり前述した様に
、マウントしたベレットとブリッジを金属ワイヤで接続
して、電気回路の一部を構成する場合、マウント位置の
バラツキは、前記ベレットとブリクジ間の金属ワイヤ長
のバラツキを生じさせる。In the conventional hybrid integrated circuit described above, a bridge must be mounted in addition to the transistor pellet.However, there is a limit to the accuracy of the mounting position, and as mentioned above, the mounted pellet and bridge must be connected using metal wire. When forming part of an electric circuit, variations in the mounting position cause variations in the length of the metal wire between the bullet and the bridge.

一方、この様な混成集積回路で扱う周波数が高くなって
くると、上記金属ワイヤ長のバラツキが回路の電気的特
性に与える影響がだんだん顕著になっていき、しいては
、混成集積回路の特性バラツキをまねき、歩留を低下さ
せろという欠点がある。On the other hand, as the frequencies handled by such hybrid integrated circuits become higher, the influence of the above-mentioned variations in metal wire length on the electrical characteristics of the circuit becomes more and more noticeable, and the characteristics of the hybrid integrated circuits become increasingly noticeable. It has the disadvantage of causing variations and lowering the yield.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の混成集積回路は、ボンディングワイヤ長のバラ
ツキを生じる一原因となるブリッジのマウント位置精度
のバラツキをなくす為に、ブリッジの使用を廃止しブリ
ッジと同等の回路を基板上の回路パターンで構成するこ
とにより、電気的特性を補償している。The hybrid integrated circuit of the present invention eliminates the use of bridges and constructs a circuit equivalent to a bridge using a circuit pattern on the board in order to eliminate variations in the mounting position accuracy of the bridge, which is one of the causes of variations in bonding wire length. By doing so, the electrical characteristics are compensated.

〔実施例〕〔Example〕

次に本発明を説明する。 Next, the present invention will be explained.

第１図（ａ）、　（ｂ）は、本発明による混成集積回路
の一実施例で、絶縁基板ｌ上に構成された導体部８（コ
レクタランド）上にコレクタ接地のトランジスタベレッ
ト３がマウントされ、前記トランジスタベレット３上の
ベース電極１１は、ワイヤ６により導体部９（ベースパ
ターン）に接続されている。又、接地導体４（エミッタ
パターン）は、導体部８（コレクタランド）を囲む様に
構成されていて、エミッタ電極１１は金属ワイヤ５によ
り、前記接地導体４（エミッタパターン）のそれぞれ異
なる点４，４“にボンディングされる。又、導体部８は
金属ワイヤ７により導体部２（コレクタパターン）Ｋ接
続されている。FIGS. 1(a) and 1(b) show an embodiment of the hybrid integrated circuit according to the present invention, in which a transistor bellet 3 with a grounded collector is mounted on a conductor portion 8 (collector land) formed on an insulating substrate l. , the base electrode 11 on the transistor bellet 3 is connected to the conductor portion 9 (base pattern) by a wire 6. Further, the ground conductor 4 (emitter pattern) is configured to surround the conductor portion 8 (collector land), and the emitter electrode 11 is connected to the ground conductor 4 (emitter pattern) at different points 4, Furthermore, the conductor portion 8 is connected to the conductor portion 2 (collector pattern) K by a metal wire 7.

以上の構成による回路で、エミッタの接地ワイヤ（金属
ワイヤ５）は、電極１つあたりからベレットの前後２本
、すなわち導体部４の異なる点４′及び４″にボンディ
ングされていて、前述のブリッジを使用した回路と同様
にエミッタ接地インダクタンスが低減できる。In the circuit configured as described above, the emitter ground wire (metal wire 5) is bonded from each electrode to the two front and rear ends of the pellet, that is, to different points 4' and 4'' of the conductor section 4, and is bonded to the above-mentioned bridge. Emitter grounding inductance can be reduced similarly to circuits using .

〔発明の効果〕〔Effect of the invention〕

以上説明した様に本発明は、トランジスタの特性向上策
として使用されるブリッジを、基板上の導体パターンに
置き換えることにより、ブリッジのマウント位置のバラ
ツキが起因となる特性バラツキを低減した、混成集積回
路を実現することを可能にした。As explained above, the present invention provides a hybrid integrated circuit that reduces characteristic variations caused by variations in the mounting position of the bridge by replacing bridges used to improve transistor characteristics with conductive patterns on a substrate. made it possible to achieve this.

又、本発明による混成集積回路においては、ブリッジの
資材費及びブリッジのマウント工数を削減できる。Further, in the hybrid integrated circuit according to the present invention, the cost of materials for the bridge and the number of man-hours for mounting the bridge can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明の混成集積回路の一実施例の図で、第
１図（ａｌが上からの正面図、第１図（ｂｌが、第１図
（ａｌＯＡ−Ａ’　線断面図である。 第２図は、従来の混成集積回路の一実施例図で第２図（
ａｌが上からの正面図、第２図（ｂｌ及び第２図（Ｃ）
はそれぞれ第２図（ｄ）のＡ−Ａ’、　Ｂ−Ｂ’　　線
断面図である。第３図は、ブリッジを使わない従来の混
成集積回路の図である。 ｌ・・・・・・セラミック基板、２・・・・・・導体部
（コレクタパターン〕、３・・・・・・トランジスタペ
レット、４゜４　／　、　４　／／・・・・・・導体部
（エミッタパターン）、５・・・・・・金属ワイヤ（エ
ミッタ接地ワイヤ）、６・・・・・・金属ワイヤ（ベー
スワイヤ）、７・・・・・・金属ワイヤ、８・・・・・
・導体部（コレクタランド）、９・・・・・・導体部（
ベースパターン〕、１０・・・・・・金属槽（ブリッジ
）、１１・・・・・・ベース電極、１２・・・・・・エ
ミッタ電極。 ツ′・　　ノ 丈−２４，／ （α） 第１図 υノ　　　４％２　　図 第３図 手続補正書（方式） ％式％ １、事件の表示　　　昭和６０年特　許願第２５０２０
７号２、発明の名称　　混成集積回路 ３、補正をする者 事件との関係　　　　　　　出　願　人東京都港区芝五
丁目３３番１号 （４２３）　　　日本電気株式会社 代表者　関本忠弘 ４、代理人 〒１０８　　東京都港区芝五Ｔｇ３７番８号　住友三田
ビル電話　東京（０３）４５６−３１１１（大代表）　
１　′−！ ６、補正の対象 明細書の図面の簡単な説明の欄 ７、補正の内容 （１）　　明細書第６頁３行の「第２図（ｄ）」を「第
２図（ａ）」に訂正いたします。 代理人　弁理士　　内　原　　　日　　。FIG. 1 is a diagram of an embodiment of the hybrid integrated circuit of the present invention, in which FIG. 1 (al is a front view from above, and FIG. Figure 2 shows an example of a conventional hybrid integrated circuit.
al is a front view from above, Fig. 2 (bl and Fig. 2 (C)
are sectional views taken along lines AA' and BB' in FIG. 2(d), respectively. FIG. 3 is a diagram of a conventional hybrid integrated circuit that does not use bridges. l... Ceramic substrate, 2... Conductor part (collector pattern), 3... Transistor pellet, 4゜4/, 4 //... Conductor part (emitter pattern), 5...metal wire (emitter ground wire), 6...metal wire (base wire), 7...metal wire, 8...
・Conductor part (collector land), 9... Conductor part (
base pattern], 10... metal tank (bridge), 11... base electrode, 12... emitter electrode. TS′・ノlength−24,/(α) Figure 1 υノ 4% 2 Figure 3 Procedural amendment (method) % formula % 1. Indication of the case 1985 Patent Application No. 25020
No. 7 No. 2, Title of the invention: Hybrid integrated circuit 3, Relationship to the amended person's case Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative: Tadahiro Sekimoto 4, Agent: 108 Sumitomo Mita Building, 37-8 Shibago Tg, Minato-ku, Tokyo Telephone: Tokyo (03) 456-3111 (Main number)
1′-! 6. Column 7 for a brief explanation of the drawings in the specification subject to amendment. Contents of the amendment (1) Corrected "Fig. 2 (d)" in line 3 of page 6 of the specification to "Fig. 2 (a)". I will do it. Agent: Patent attorney Hi Uchihara.

Claims (1)

【特許請求の範囲】[Claims] 絶縁基板上に構成された導体パターン上の一部にトラン
ジスタチップがマウントされ、かつ、金属ワイヤにより
、前記導体パターンの他の一部に接続されたことを特徴
とする混成集積回路。1. A hybrid integrated circuit characterized in that a transistor chip is mounted on a part of a conductor pattern formed on an insulating substrate, and is connected to another part of the conductor pattern by a metal wire.
JP25020785A 1985-11-07 1985-11-07 Hybrid integrated circuit Pending JPS62109332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25020785A JPS62109332A (en) 1985-11-07 1985-11-07 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25020785A JPS62109332A (en) 1985-11-07 1985-11-07 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS62109332A true JPS62109332A (en) 1987-05-20

Family

ID=17204412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25020785A Pending JPS62109332A (en) 1985-11-07 1985-11-07 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS62109332A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5465007A (en) * 1991-09-05 1995-11-07 Mitsubishi Denki Kabushiki Kaisha High frequency transistor with reduced parasitic inductance
US5635751A (en) * 1991-09-05 1997-06-03 Mitsubishi Denki Kabushiki Kaisha High frequency transistor with reduced parasitic inductance

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5287363A (en) * 1976-01-17 1977-07-21 Nec Corp Semiconductor packdage
JPS6049639A (en) * 1983-08-29 1985-03-18 Fujitsu Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5287363A (en) * 1976-01-17 1977-07-21 Nec Corp Semiconductor packdage
JPS6049639A (en) * 1983-08-29 1985-03-18 Fujitsu Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5465007A (en) * 1991-09-05 1995-11-07 Mitsubishi Denki Kabushiki Kaisha High frequency transistor with reduced parasitic inductance
US5635751A (en) * 1991-09-05 1997-06-03 Mitsubishi Denki Kabushiki Kaisha High frequency transistor with reduced parasitic inductance

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