JPH0115144B2 - - Google Patents
Info
- Publication number
- JPH0115144B2 JPH0115144B2 JP58008052A JP805283A JPH0115144B2 JP H0115144 B2 JPH0115144 B2 JP H0115144B2 JP 58008052 A JP58008052 A JP 58008052A JP 805283 A JP805283 A JP 805283A JP H0115144 B2 JPH0115144 B2 JP H0115144B2
- Authority
- JP
- Japan
- Prior art keywords
- dielectric substrate
- metallized layer
- integrated circuit
- hybrid integrated
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 29
- 239000004065 semiconductor Substances 0.000 claims description 9
- 239000011810 insulating material Substances 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 238000005219 brazing Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 239000011521 glass Substances 0.000 description 6
- 230000003321 amplification Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000005336 cracking Methods 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Description
〔発明の技術分野〕
この発明は高周波信号増幅用の混成集積回路装
置に係り、特にその放熱板への取付け形態の改良
に関するものである。
〔従来技術〕
第１図は従来の混成集積回路装置の一例を示す
平面図、第２図はその−線での断面図であ
る。図において、１は銅からなる放熱板、２はア
ルミナ等からなる誘電体基板、３はこの誘電体基
板２に形成された銀（Ag）−パラジウム（Pd）
合金などからなる裏面メタライズ層、４は誘電体
基板２の表面に形成され、任意のパターンを有す
るAg−Pd等からなる表メタライズ層、５，６は
半田等（図示せず）で表メタライズ層４の所要位
置に接着された半導体素子、７，８はそれぞれ半
導体素子５，６の電極（図示せず）と表メタライ
ズ層４の所要部分とを接続する金などからなる金
属細線、９，１０はそれぞれ半導体素子５，６お
よび金属細線７，８を覆うワニス等の絶縁物、１
１，１２はインピーダンス整合回路を構成するよ
うに表面メタライズ層４の所要部分に半田付けさ
れたそれぞれコンデンサおよびコイルを示す。１
３は信号入力リード、１４は電源供給用リード、
１５は信号出力リード、１６は放熱板１と誘電体
基板２の裏面メタライズ層３とを接着する半田層
である。
以上のように構成された従来装置では、電源供
給用リード１４から直流電源電圧が供給されて動
作し、信号入力リード１３から入力された信号が
数百倍に増幅されて信号出力リード１５から取り
出され増幅器の機能を発揮する。
ところで、高周波信号の増幅用の混成集積回路
装置は、最近、高利得化、高出力化、高性能化が
要求され、半導体素子５，６の搭載数、並びにイ
ンピーダンス整合用素子であるコイル１２および
コンデンサ１１の数の増大、さらには表メタライ
ズ層４のパターンの占める面積等の増大により誘
電体基板２の面積は増大の一途をたどつている。
しかし、この誘電体基板２の大形化にともなつ
て、誘電体基板２が割れるという致命的な故障が
発生する傾向が大きくなつた。特に、放熱板１と
誘電体基板２とを半田層１６で200℃程度の温度
で接着した後、室温に、更には−20℃等の低温に
したときに発生する。その原因はアルミナからな
る誘電体基板２と銅からなる放熱板１との熱膨張
係数が下表に示すように大きな差を有するため
で、低温になるほど、また誘電体基板２が大形に
なるほど、誘電体基板２の受ける応力は大きくな
り、基板割れの発生につながる。
[Technical Field of the Invention] The present invention relates to a hybrid integrated circuit device for high frequency signal amplification, and particularly to an improvement in the form of attachment to a heat sink. [Prior Art] FIG. 1 is a plan view showing an example of a conventional hybrid integrated circuit device, and FIG. 2 is a cross-sectional view thereof taken along the - line. In the figure, 1 is a heat sink made of copper, 2 is a dielectric substrate made of alumina, etc., and 3 is silver (Ag)-palladium (Pd) formed on this dielectric substrate 2.
4 is a back metallized layer made of an alloy or the like, 4 is a front metallized layer formed on the surface of the dielectric substrate 2 and is made of Ag-Pd or the like and has an arbitrary pattern, 5 and 6 are front metallized layers made of solder or the like (not shown). Semiconductor elements 4 are bonded to the required positions; 7 and 8 are thin metal wires made of gold or the like that connect the electrodes (not shown) of the semiconductor elements 5 and 6 to the required portions of the surface metallized layer 4; 9 and 10; 1 is an insulating material such as varnish that covers the semiconductor elements 5 and 6 and the thin metal wires 7 and 8, respectively;
Reference numerals 1 and 12 indicate a capacitor and a coil, respectively, which are soldered to required portions of the surface metallized layer 4 to constitute an impedance matching circuit. 1
3 is a signal input lead, 14 is a power supply lead,
Reference numeral 15 represents a signal output lead, and reference numeral 16 represents a solder layer that adheres the heat sink 1 and the back metallized layer 3 of the dielectric substrate 2. In the conventional device configured as described above, the DC power supply voltage is supplied from the power supply lead 14 for operation, and the signal input from the signal input lead 13 is amplified several hundred times and taken out from the signal output lead 15. It performs the function of an amplifier. Incidentally, hybrid integrated circuit devices for amplifying high-frequency signals are recently required to have higher gain, higher output, and higher performance, and the number of mounted semiconductor elements 5 and 6, as well as the coil 12 and impedance matching elements, are increasing. The area of the dielectric substrate 2 continues to increase due to an increase in the number of capacitors 11 and an increase in the area occupied by the pattern of the front metallized layer 4.
However, as the size of the dielectric substrate 2 increases, there is a greater tendency for fatal failures such as cracking of the dielectric substrate 2 to occur. In particular, this occurs when the heat dissipation plate 1 and the dielectric substrate 2 are bonded together with the solder layer 16 at a temperature of about 200°C, and then the temperature is lowered to room temperature, or further to a low temperature such as -20°C. The reason for this is that the thermal expansion coefficients of the dielectric substrate 2 made of alumina and the heat sink 1 made of copper have a large difference as shown in the table below. , the stress applied to the dielectric substrate 2 increases, leading to the occurrence of substrate cracks.
この発明は以上のような点に鑑みてなされたも
ので、誘電体基板の裏面全面に形成されたメタラ
イズ層の一部に絶縁物をコーテイングして半田づ
け阻止領域を設け、半田づけ面積を制限すること
によつて、基板割れの発生の少ない高周波信号増
幅用の混成集積回路装置を提案するものである。
〔発明の実施例〕
第３図はこの発明の一実施例による高周波信号
増幅用の混成集積回路装置の構成を示す断面図、
第４図はこの実施例に用いる誘電体基板の裏面図
である。図において、第１図、第２図と同等部分
は同一符号で示し、説明の重複を避ける。この実
施例ではアルミナからなる誘電体基板２の表面に
表メタライズ層パターン４を、裏面全面に裏面メ
タライズ層３を従来例と同様に形成し、その後
に、裏面メタライズ層３の上に、その長手方向両
端部を所定幅で覆うようにガラスコーテイング１
７を施す。このガラスコーテイング１７は400〜
600℃程度で焼成できるものを用い、厚さは20μ
以下程度にする。このように形成した誘電体基板
２の表メタライズ層４に半導体素子５，６等を半
田などで取りつけ、最後にその誘電体基板２の裏
面を放熱板１に鉛（Pb）・スズ（Sn）系半田で接
着する。この場合、半田の融点は300℃以下であ
り、上記半田付け作業時にガラスコーテイング１
７は溶融することはなく、その部分は半田と接着
しない。従つて、放熱板１と誘電体基板２との接
着面積はガラスコーテイング１７の形成部分だけ
少なくなる。これによつて、大形化された誘電体
基板２を用い、搭載部品を増加させても、誘電体
基板２の受けるストレスを大幅に軽減できる。た
だし、半導体素子５，６が高出力素子の場合は十
分な熱放射を必要とするので、半導体素子５，６
は裏面にガラスコーテイングのない部分に取付け
る必要がある。
〔発明の効果〕
以上説明したように、この発明になる高周波信
号増幅用の混成集積回路装置では、誘電体基板の
裏面全面に形成されたメタライズ層の一部を半田
より融点の高い絶縁物でコーテイングし、誘電体
基板の放熱板への半田付けを所要部分に限定した
ので、温度変化による誘電体基板へのストレスの
発生を小さくすることができ、基板割れを少なく
することができる。
This invention was made in view of the above points, and includes coating a part of the metallized layer formed on the entire back surface of the dielectric substrate with an insulating material to provide a soldering prevention area to limit the soldering area. By doing so, the present invention proposes a hybrid integrated circuit device for high frequency signal amplification in which substrate cracking is less likely to occur. [Embodiment of the Invention] FIG. 3 is a cross-sectional view showing the configuration of a hybrid integrated circuit device for high frequency signal amplification according to an embodiment of the invention;
FIG. 4 is a back view of the dielectric substrate used in this embodiment. In the figures, parts equivalent to those in FIGS. 1 and 2 are indicated by the same reference numerals to avoid duplication of explanation. In this embodiment, a front metallized layer pattern 4 is formed on the front surface of a dielectric substrate 2 made of alumina, and a back metallized layer 3 is formed on the entire back surface in the same manner as in the conventional example. Glass coating 1 so as to cover both ends of the direction with a predetermined width.
Apply 7. This glass coating 17 is 400~
Use a material that can be fired at around 600℃, and the thickness is 20μ
Keep it below. Semiconductor elements 5, 6, etc. are attached to the front metallized layer 4 of the dielectric substrate 2 formed in this way by soldering, etc., and finally the back side of the dielectric substrate 2 is attached to the heat sink 1 using lead (Pb) and tin (Sn). Attach with solder. In this case, the melting point of the solder is below 300℃, and the glass coating 1 is
No. 7 does not melt, and that portion does not adhere to solder. Therefore, the bonding area between the heat sink 1 and the dielectric substrate 2 is reduced by the area where the glass coating 17 is formed. As a result, even if an enlarged dielectric substrate 2 is used and the number of mounted components is increased, the stress on the dielectric substrate 2 can be significantly reduced. However, if the semiconductor elements 5 and 6 are high-output elements, sufficient heat radiation is required, so the semiconductor elements 5 and 6
must be installed on a part that does not have a glass coating on the back. [Effects of the Invention] As explained above, in the hybrid integrated circuit device for high frequency signal amplification according to the present invention, a part of the metallized layer formed on the entire back surface of the dielectric substrate is made of an insulating material with a higher melting point than solder. Since the coating and soldering of the dielectric substrate to the heat sink are limited to the required portions, stress on the dielectric substrate due to temperature changes can be reduced, and substrate cracking can be reduced.
第１図は従来の混成集積回路装置の一例を示す
平面図、第２図はその−線での断面図、第３
図はこの発明の一実施例の構成を示す断面図、第
４図はこの実施例に用いる誘電体基板の裏面図で
ある。
図において、１は放熱板、２は誘電体基板、３
は裏面メタライズ層、４は表メタライズ層、５，
６は半導体素子、１１はコンデンサ（回路素子）、
１２はコイル（回路素子）、１６は半田層、１７
はガラス層（絶縁層）である。なお、図中同一符
号は同一または相当部分を示す。
Fig. 1 is a plan view showing an example of a conventional hybrid integrated circuit device, Fig. 2 is a sectional view taken along the - line, and Fig. 3
The figure is a sectional view showing the structure of an embodiment of the present invention, and FIG. 4 is a back view of a dielectric substrate used in this embodiment. In the figure, 1 is a heat sink, 2 is a dielectric substrate, and 3 is a heat sink.
is the back metallized layer, 4 is the front metallized layer, 5,
6 is a semiconductor element, 11 is a capacitor (circuit element),
12 is a coil (circuit element), 16 is a solder layer, 17
is a glass layer (insulating layer). Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
の回路素子を装着し、裏面全面にメタライズ層が
形成された誘電体基板を、その裏面側にて放熱板
に半田などのろう材で接着してなる混成集積回路
装置において、 上記誘電体基板の裏面メタライズ層の一部を上
記ろう材より融点の高い絶縁物でコーテイングし
たことを特徴とする混成集積回路装置。 ２ 上記誘電体基板は長方形をなし、その長手方
向の両端部を絶縁物でコーテイングしたことを特
徴とする特許請求の範囲第１項記載の混成集積回
路装置。 ３ 上記回路素子のうち発熱を伴う素子は絶縁物
でコーテイングされない部分に対応する部分に装
着したことを特徴とする特許請求の範囲第１項ま
たは第２項記載の混成集積回路装置。[Claims] 1. A dielectric substrate on which a circuit element such as a semiconductor element for amplifying high-frequency signals is mounted and a metallized layer formed on the entire back surface is soldered to a heat sink on the back side. What is claimed is: 1. A hybrid integrated circuit device in which a part of the backside metallized layer of the dielectric substrate is coated with an insulating material having a melting point higher than that of the brazing material. 2. The hybrid integrated circuit device according to claim 1, wherein the dielectric substrate has a rectangular shape, and both longitudinal ends thereof are coated with an insulating material. 3. The hybrid integrated circuit device according to claim 1 or 2, wherein among the circuit elements, an element that generates heat is mounted in a portion corresponding to a portion not coated with an insulating material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58008052A JPS59132153A (en) | 1983-01-18 | 1983-01-18 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58008052A JPS59132153A (en) | 1983-01-18 | 1983-01-18 | Hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59132153A JPS59132153A (en) | 1984-07-30 |
| JPH0115144B2 true JPH0115144B2 (en) | 1989-03-15 |
Family
ID=11682556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58008052A Granted JPS59132153A (en) | 1983-01-18 | 1983-01-18 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59132153A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7169685B2 (en) | 2002-02-25 | 2007-01-30 | Micron Technology, Inc. | Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57132448U (en) * | 1981-02-12 | 1982-08-18 |
-
1983
- 1983-01-18 JP JP58008052A patent/JPS59132153A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59132153A (en) | 1984-07-30 |
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