JP2583507B2 - Semiconductor mounting circuit device - Google Patents

Semiconductor mounting circuit device

Info

Publication number
JP2583507B2
JP2583507B2 JP62133149A JP13314987A JP2583507B2 JP 2583507 B2 JP2583507 B2 JP 2583507B2 JP 62133149 A JP62133149 A JP 62133149A JP 13314987 A JP13314987 A JP 13314987A JP 2583507 B2 JP2583507 B2 JP 2583507B2
Authority
JP
Japan
Prior art keywords
wiring board
mounting
layer
semiconductor element
concave portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62133149A
Other languages
Japanese (ja)
Other versions
JPS63299152A (en
Inventor
義孝 福岡
泰徳 仁井田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP62133149A priority Critical patent/JP2583507B2/en
Publication of JPS63299152A publication Critical patent/JPS63299152A/en
Application granted granted Critical
Publication of JP2583507B2 publication Critical patent/JP2583507B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は半導体素子を配線基板に実装、配設して成る
回路装置に係り、特に放熱性、高密度配線および高信頼
性を考慮した半導体実装回路装置の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a circuit device in which a semiconductor element is mounted and arranged on a wiring board. The present invention relates to improvement of a semiconductor mounting circuit device in consideration of performance.

(従来の技術) 集積回路素子(IC)、トランジスタ素子、電界効果型
トランジスタ(FET)、ダイオード素子などの半導体素
子を配線基板(プリント配線基板、セラミック配線基
板)に実装配設して成る実装回路装置(電子部品)は、
産業用電子機器、民生用電子機器の分野で多く使用され
ている。しかして、この種の配線基板に対する半導体素
子の実装、配設はいわゆる高密度実装技術として注目さ
れている。ここで、“搭載・実装するチップ面積の総和
/配線基板の面積×100%”で示される実装効率は、た
とえばマルチ・チップ・モジュールの場合、30〜70%が
要求されている。ところで、上記半導体素子を実装して
成る実装回路装置(もしくは集積回路部品)において
は、実装する半導体素子数の増加やチップサイズが大型
化するにつれ(高集積化)、それら半導体素子などによ
る発熱を、いかに効果的に放散するかが問題になる。つ
まり、実装する半導体素子などの動作に伴う発熱が、そ
れら半導体素子の性能に悪影響を及ぼすので、できるだ
け速やかな放熱が望まれる。こうした事情に対し、高密
度実装技術においては、従来、第2図に示す如き構成を
採るものが知られている。すなわち実装・配設する(搭
載する)半導体素子(半導体チップ)のサイズに合せ、
配線基板1に選択的に貫通孔を形設し、この貫通孔に係
合するような突出部2を設けたいわゆるヒートシンク3
を組合せる構成である。なお、この場合、ヒートシンク
3の突出部2の上端面は配線基板1面と略平面をなして
おり、また配線基板1とは接着剤層4によって一体化し
ている。しかして、上記配線基板1と係合一体化したヒ
ートシンク3の突出部2面上に絶縁的に半導体素子5を
実装・配設するとともに、入出力端子を配線基板1上の
回路パターン端子6にワイヤ7で電気的に接続してい
る。
(Prior art) A mounting circuit in which semiconductor elements such as integrated circuit elements (ICs), transistor elements, field effect transistors (FETs), and diode elements are mounted on a wiring board (printed wiring board, ceramic wiring board). The equipment (electronic parts)
It is widely used in the fields of industrial electronic equipment and consumer electronic equipment. The mounting and disposition of a semiconductor element on a wiring board of this type has attracted attention as a so-called high-density mounting technique. Here, for example, in the case of a multi-chip module, 30% to 70% is required for the mounting efficiency indicated by “total of chip areas to be mounted / mounted / area of wiring board × 100%”. By the way, in a mounted circuit device (or integrated circuit component) formed by mounting the above semiconductor elements, as the number of mounted semiconductor elements increases and the chip size increases (high integration), heat generated by the semiconductor elements and the like is reduced. The problem is how to effectively dissipate. That is, heat generated by the operation of the semiconductor elements to be mounted has a bad influence on the performance of the semiconductor elements. Under these circumstances, a high-density mounting technology that employs a configuration as shown in FIG. 2 is conventionally known. That is, according to the size of the semiconductor element (semiconductor chip) to be mounted / disposed (mounted),
A so-called heat sink 3 in which a through hole is selectively formed in the wiring board 1 and a projection 2 is provided so as to engage with the through hole.
Are combined. In this case, the upper end surface of the projecting portion 2 of the heat sink 3 is substantially flat with the surface of the wiring board 1, and is integrated with the wiring board 1 by an adhesive layer 4. Thus, the semiconductor element 5 is insulated and mounted on the surface of the protrusion 2 of the heat sink 3 integrated with the wiring board 1 and the input / output terminals are connected to the circuit pattern terminals 6 on the wiring board 1. They are electrically connected by wires 7.

しかし、上記構成においては、搭載・実装した半導体
素子5とヒートシンク3との電気絶縁性が不充分であっ
たり、また実装(搭載)する半導体素子の種類や容量に
よって絶縁の程度を調整しており、工程などの煩雑さを
避け得ない。加えて、この構成の場合には、ヒートシン
ク3を配線基板1と組合せた後でなければ、半導体素子
5の搭載・実装ができないし、さらに配設基板1は、穴
開けにより配線領域も減少するため高密度実装にも限界
が自ずからある。ここで、配線可能な領域が低減するこ
とは、配線密度の低下となり、回路機能としても高機能
化が損なわれることになる。
However, in the above configuration, the degree of insulation is adjusted depending on the electrical insulation between the mounted / mounted semiconductor element 5 and the heat sink 3 or the type and capacity of the mounted / mounted semiconductor element. Inevitably, the complexity of processes and the like cannot be avoided. In addition, in the case of this configuration, the semiconductor element 5 cannot be mounted and mounted only after the heat sink 3 is combined with the wiring board 1, and the wiring area of the mounting board 1 is reduced by drilling. Therefore, there is a limit to high-density mounting. Here, a reduction in the area where wiring is possible leads to a reduction in wiring density, which impairs the enhancement of circuit functions.

さらに、配線基板1とヒートシンク3とを接着剤層4
により一体化しているが、接着剤層4の濡れ性やボイド
などの影響、さらには配線基板1とヒートシンク3との
熱膨張係数の違いにより、接着剤層4にクラックが入っ
て気密性不良(リーク不良)を生じ信頼性面でも問題が
あった。また、必要配設領域を余分に確保する必要性が
生じ、このことは前記実装効率を低下することにつなが
る。
Further, the wiring board 1 and the heat sink 3 are bonded to the adhesive layer 4.
However, due to the effects of the wettability and voids of the adhesive layer 4 and the difference in the coefficient of thermal expansion between the wiring board 1 and the heat sink 3, cracks occur in the adhesive layer 4 and poor airtightness ( (Leakage defect), and there was also a problem in reliability. In addition, it is necessary to secure an extra necessary installation area, which leads to a decrease in the mounting efficiency.

(発明が解決しようとする問題点) したがって本発明は煩雑な工程など要せずに放熱性が
充分に達成され、かつ高密度の配線ひいては実装効率の
向上、高機能化および高信頼性化も可能な半導体実装回
路装置を提供することを目的とする。
(Problems to be Solved by the Invention) Therefore, the present invention achieves sufficient heat radiation without any complicated steps, and achieves high-density wiring, and thus, improvement in mounting efficiency, high functionality and high reliability. It is an object of the present invention to provide a possible semiconductor mounting circuit device.

[発明の構成] (問題を解決するための手段) 本発明に係る半導体実装回路装置は、厚さ方向に凹部
が選択的に形成され、かつ凹部の下側領域を含め所定の
内層回路パターンを有する配線基板と、前記配線基板の
凹部内に装着されたCu−W系金属片と、前記装着された
Cu−W系金属片の露出面上に実装配設された半導体素子
と、前記実装配設した半導体素子の入出力端子を所定の
回路パターン端子に電気的に接続する接続手段とを具備
して成り、前記凹部の下側領域には少くとも電源層およ
び接地層が配置内蔵(内層)されていることを特徴とす
る。
[Structure of the Invention] (Means for Solving the Problem) In a semiconductor mounting circuit device according to the present invention, a concave portion is selectively formed in a thickness direction, and a predetermined inner layer circuit pattern including a lower region of the concave portion is formed. Having a wiring board, a Cu-W-based metal piece mounted in a recess of the wiring board,
A semiconductor element mounted and disposed on the exposed surface of the Cu-W-based metal piece, and connection means for electrically connecting input / output terminals of the mounted semiconductor element to predetermined circuit pattern terminals. At least a power supply layer and a ground layer are arranged and built in (inner layer) in a lower region of the concave portion.

(作用) 本発明によれば、配線基板面の半導体素子が実装され
る領域には、没設するようにCu−W系金属片が装着さ
れ、このCu−W系金属片の上面(露出面)に半導体素子
が実装される。つまり、一方の面(裏面)側は連続した
配線基板面をなしたまま、他の面(表面)側に選択的に
金属層領域を形設し、この金属層領域面上に所要の素子
は実装され、かつヒートシンクとは電気的に絶縁を保持
している。このため、実装する各半導体素子の電気的絶
縁に対する処置を格別調整する必要もないし、さらに上
記Cu−W系金属片は熱膨張率が実装する素子や配線基板
と略等しいので、動作過程において、実装した素子のCu
−W系金属片からの剥離乃至離脱、およびCu−W系金属
片の配線基板からの剥離乃至離脱を招来する恐れもな
い。
(Operation) According to the present invention, a Cu-W-based metal piece is mounted so as to be immersed in a region of a wiring board surface where a semiconductor element is mounted, and the upper surface (exposed surface) of this Cu-W-based metal piece is mounted. The semiconductor element is mounted on (). In other words, a metal layer region is selectively formed on the other surface (front surface) side while a continuous wiring board surface is formed on one surface (back surface) side, and required elements are formed on the metal layer region surface. It is mounted and electrically insulated from the heat sink. For this reason, it is not necessary to particularly adjust the treatment for the electrical insulation of each semiconductor element to be mounted, and furthermore, since the Cu-W-based metal piece has a thermal expansion coefficient substantially equal to that of the mounted element or the wiring board, in the operation process, Cu of mounted element
There is no danger of peeling or detachment from the -W based metal piece and peeling or detaching of the Cu-W based metal piece from the wiring board.

特に、前記配線基板においては、凹部下側を配線領域
として確保し得ることは、それだけ配線による高機能化
および高密度化を図り得るばかりでなく、少くとも電源
層や接地層が配置内層されているため、搭載・実装した
半導体素子がパワー素子や高発熱高速素子などの場合、
その高機能性の要求に対応し得ることになる。加えて、
前記Cu−W系金属片の装着に伴い配線基板(パッケー
ジ)のリーク不良が生じる恐れも解消する。
In particular, in the wiring board, the fact that the lower side of the concave portion can be secured as a wiring area not only can improve the function and the density by wiring, but also at least the power supply layer and the grounding layer can be arranged in the inner layer. Therefore, when the semiconductor element mounted and mounted is a power element,
It can respond to the demand for high functionality. in addition,
It is also possible to eliminate the possibility that the wiring board (package) leaks due to the mounting of the Cu-W based metal piece.

(実施例) 以下、アルミナセラミック製の基板を用い、パワート
ラジスタチップを実装(搭載)した実施例について説明
する。
(Example) Hereinafter, an example in which a power transistor chip is mounted (mounted) using a substrate made of alumina ceramic will be described.

第1図は、パワートランジスタ素子を実装した集積回
路部品に、ヒートシンクを取着して成る半導体実装回路
装置(集積回路部品)を断面的に示したものである。第
1図において1は配線基板で、信号配線層、電源層、接
地層を含む内層配線1aを有する第一の回路基板層1bと凹
部1cを有する第二の回路基板層1dとから構成されてい
る。また、3は配線基板1の裏面側に接着一体化された
ヒートシンクを、5,5′はパワートランジスタ素子を、
6は表面の回路パターン端子を、7はAuもしくはAl細線
を、8は第一の回路基板層1b上に設けられたメタライズ
層を、9は配線基板1の凹部1c内に装着、配設されたCu
−W系金属片を、また10は信号配線層と電源層や接地層
を含む内層パターン1aとの間を電気的に接続する導体を
それぞ示す。
FIG. 1 is a sectional view showing a semiconductor mounted circuit device (integrated circuit component) in which a heat sink is attached to an integrated circuit component on which a power transistor element is mounted. In FIG. 1, reference numeral 1 denotes a wiring board, which includes a first circuit board layer 1b having an inner wiring 1a including a signal wiring layer, a power supply layer, and a ground layer, and a second circuit board layer 1d having a concave portion 1c. I have. Reference numeral 3 denotes a heat sink bonded and integrated to the back side of the wiring board 1, reference numerals 5 and 5 'denote power transistor elements,
6 is a circuit pattern terminal on the surface, 7 is an Au or Al thin wire, 8 is a metallized layer provided on the first circuit board layer 1b, and 9 is mounted and arranged in the recess 1c of the wiring board 1. Cu
Reference numeral 10 denotes a conductor for electrically connecting between the signal wiring layer and the inner layer pattern 1a including the power supply layer and the ground layer.

次に、前記構成の半導体実装回路装置の製造例につい
て説明する。先ず、いわゆるグリーンシートを用いて内
層配線を有する第一の回路基板層1bを作り、さらにその
上に半導体素子を実装する位置、領域および導通用の孔
をくり抜き、かつ表面に所要の回路パターンを形成した
グリーンシート(第二の回路基板層を指す)を積層して
一体に加圧、焼成した。なおこの場合、第一の回路基板
層1bの露出する面、つまりその上に積層されるグリーン
シートのくり抜き部に対応する部分にはメタライズ層が
予め形成してある。かくして得た所定領域に凹部を形成
した配線基板の前記凹部内のメタライズ層上にトランジ
スタ素子や配線基板と略同じの熱膨張率を有するCu−W
系金属片を装着、配設する。このCu−W系金属片の装着
・配設は、セラミック系配線基板の場合、グリーンシー
ト焼結後、Cu−W系金属片Agロウ付けして行えばよい。
Next, an example of manufacturing the semiconductor mounted circuit device having the above configuration will be described. First, a first circuit board layer 1b having an inner layer wiring is formed using a so-called green sheet, and furthermore, a position for mounting a semiconductor element, a region and a hole for conduction are cut out, and a required circuit pattern is formed on the surface. The formed green sheets (indicating the second circuit board layer) were laminated and integrally pressed and fired. In this case, a metallized layer is previously formed on the exposed surface of the first circuit board layer 1b, that is, on the portion corresponding to the hollow portion of the green sheet laminated thereon. Cu-W having substantially the same coefficient of thermal expansion as the transistor element and the wiring substrate on the metallized layer in the concave portion of the wiring substrate having the concave portion formed in the predetermined region thus obtained.
Attach and arrange the system metal pieces. In the case of a ceramic wiring board, the mounting and disposing of the Cu-W-based metal piece may be performed by sintering the green sheet and brazing the Cu-W-based metal piece Ag.

しかる後、上記配設したCu−W系金属片の露出面、つ
まり配線基板面と略同一面を成すCu−W系片の面上にト
ランジスタ素子をそれぞれ搭載・実装する。次いで、上
記実装したトランジスタ素子の入出力端子を配線基板面
上に予め形成してある回路パターン端子と、たとえばAu
線やAl線などの細線をワイヤボンディングすることによ
って、電気的に接続し所要の実装がなされる。
Thereafter, the transistor elements are mounted and mounted on the exposed surfaces of the arranged Cu-W-based metal pieces, that is, the surfaces of the Cu-W-based pieces that are substantially the same as the wiring board surface. Next, the input / output terminals of the mounted transistor element are connected to a circuit pattern terminal formed in advance on the wiring board surface, for example, Au.
By wire bonding a thin wire such as a wire or an Al wire, the wires are electrically connected and required mounting is performed.

なお、上記においては、パワートランジスタ素子を実
装した例について説明したため、配線基板1の凹部1c内
に装着したCu−W系金属片9をコレクタとの接続導体と
して利用したが、実装する半導体素子の種類によって適
宜、被実装面に絶縁層を形成してもよい。また、実装す
る半導体素子は、パワートランジスタに限らず集積回路
素子、FET素子、ダイオード素子、これらの組合せ、ま
たは他の電子部品、たとえばコンデンサ、抵抗体などと
の組み合せなどでも勿論支障ない。
In the above description, since the example in which the power transistor element is mounted is described, the Cu-W-based metal piece 9 mounted in the concave portion 1c of the wiring board 1 is used as a connection conductor with the collector. Depending on the type, an insulating layer may be appropriately formed on the mounting surface. Further, the semiconductor element to be mounted is not limited to the power transistor, but may be an integrated circuit element, an FET element, a diode element, a combination thereof, or a combination with another electronic component such as a capacitor or a resistor.

[発明の効果] 上記の如く本発明によれば、配線基板の半導体素子を
実装する領域が凹部に形成され、この凹部内にCu−W系
金属片が装着され、このCu−W系金属片上に前記素子が
実装された構成を成している。しかして前記Cu−W系金
属片は、それぞれ配線基板の主構成をなす絶縁体によっ
て電気的に絶縁されているため、実装される他の半導体
素子や取着されるヒートシンクを通じての電気的な悪影
響を招く恐れもない。つまり半導体素子の実装において
実装する半導体素子間の、あるいは別途ヒートシンクを
取着した場合も、そのヒートシンクとの間の電気的絶縁
を考慮せずに所要の実装を行い得る。特に放熱性の改善
を考慮してヒートシンクを取着する場合にも、半導体素
子の実装後、ヒートシンクの取着を行い得ることは量産
的な実装手段として有効である。さらに、前記Cu−W系
金属片の装着領域の下側に、少なくとも電源層や接地層
を内層・配置したことに伴い、高配線密度を維持し、実
装効率を低下させることがないばかりか、回路的にいわ
ゆるノイズ特性も大幅にアップされ、信頼性の向上が図
られる。そしてまた、前記Cu−W系金属片の装着に伴い
配線基板としは、パッケージのリーク不良を発生するこ
とも回避されるのて、高信頼の維持も可能である。
[Effects of the Invention] As described above, according to the present invention, a region for mounting a semiconductor element on a wiring board is formed in a concave portion, and a Cu-W-based metal piece is mounted in the concave portion. In which the device is mounted. Since the Cu-W-based metal pieces are electrically insulated by the insulator constituting the main component of the wiring board, the Cu-W-based metal pieces have an adverse electrical effect through other semiconductor elements to be mounted or a heat sink to be mounted. There is no fear of inviting. That is, even when a heat sink is attached between the semiconductor elements to be mounted in the mounting of the semiconductor element or when a separate heat sink is attached, required mounting can be performed without considering electrical insulation between the heat sink and the semiconductor element. In particular, even in the case where a heat sink is attached in consideration of improvement in heat dissipation, the ability to attach the heat sink after mounting the semiconductor element is effective as mass-production mounting means. In addition, at least a power supply layer and a ground layer are arranged and arranged below the mounting area of the Cu-W-based metal piece, thereby maintaining a high wiring density and not only lowering the mounting efficiency, The so-called noise characteristic is greatly improved in circuit, and the reliability is improved. In addition, since the occurrence of a package leak defect is avoided in the wiring board due to the mounting of the Cu-W-based metal piece, high reliability can be maintained.

かくして上記半導体素子を実装する領域が金属片であ
ることに伴い熱伝導性が良好で、それら実装素子からの
発熱も容易に放熱されること、さらに配線基板において
も回路配線領域が多く確保でき、高密度実装を図り易い
ことなどの点とあいまって実用上多くの利点をもたらす
ものと言える。
Thus, since the area where the semiconductor element is mounted is a metal piece, the thermal conductivity is good, the heat generated from the mounted element is easily radiated, and more circuit wiring areas can be secured in the wiring board, It can be said that the present invention brings many practical advantages in combination with the fact that high-density mounting is easy to achieve.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明方法によって半導体素子を実装して構成
した集積回路部品の一例を示す断面図、第2図は従来の
実装手段で構成した集積回路部品の一例を示す断面図で
ある。 1……配線基板 1d……凹部 5′……トランジスタ素子(半導体素子) 6……回路パターン端子 9……Cu−W系片(金属片)
FIG. 1 is a sectional view showing an example of an integrated circuit component formed by mounting a semiconductor element by the method of the present invention, and FIG. 2 is a sectional view showing an example of an integrated circuit component formed by a conventional mounting means. DESCRIPTION OF SYMBOLS 1 ... Wiring board 1d ... Depression 5 '... Transistor element (semiconductor element) 6 ... Circuit pattern terminal 9 ... Cu-W type piece (metal piece)

フロントページの続き (56)参考文献 特開 昭58−56443(JP,A) 特開 昭53−81957(JP,A) 特開 昭53−84164(JP,A)Continuation of the front page (56) References JP-A-58-56443 (JP, A) JP-A-53-81957 (JP, A) JP-A-53-84164 (JP, A)

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】厚さ方向に凹部が選択的に形設され、かつ
凹部の下側領域を含め所定の内層回路パターンを有する
配線基板と、 前記配線基板の凹部内に装着されたCu−W系金属片と、 前記装着されたCu−W系金属片の露出面上に実装配設さ
れた半導体素子と、 前記実装配線した半導体素子の入出力端子を所定の回路
パターン端子に電気的に接続する接続手段とを具備して
成り、 前記凹部の下側領域には少くとも電源層および接地層が
配置内蔵されていることを特徴とする半導体実装回路装
置。
1. A wiring board in which a concave portion is selectively formed in a thickness direction and has a predetermined inner layer circuit pattern including a lower region of the concave portion, and a Cu-W mounted in the concave portion of the wiring substrate. And a semiconductor element mounted on the exposed surface of the mounted Cu-W-based metal piece, and electrically connecting input / output terminals of the mounted semiconductor element to a predetermined circuit pattern terminal. And a connecting means for connecting the power supply layer and the grounding layer at least in a region below the concave portion.
JP62133149A 1987-05-28 1987-05-28 Semiconductor mounting circuit device Expired - Lifetime JP2583507B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62133149A JP2583507B2 (en) 1987-05-28 1987-05-28 Semiconductor mounting circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62133149A JP2583507B2 (en) 1987-05-28 1987-05-28 Semiconductor mounting circuit device

Publications (2)

Publication Number Publication Date
JPS63299152A JPS63299152A (en) 1988-12-06
JP2583507B2 true JP2583507B2 (en) 1997-02-19

Family

ID=15097861

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62133149A Expired - Lifetime JP2583507B2 (en) 1987-05-28 1987-05-28 Semiconductor mounting circuit device

Country Status (1)

Country Link
JP (1) JP2583507B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2917902B2 (en) * 1996-04-10 1999-07-12 日本電気株式会社 Semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856443A (en) * 1981-09-30 1983-04-04 Nec Corp Semiconductor device

Also Published As

Publication number Publication date
JPS63299152A (en) 1988-12-06

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