JPS63299152A - Method of mounting semiconductor element - Google Patents

Method of mounting semiconductor element

Info

Publication number
JPS63299152A
JPS63299152A JP13314987A JP13314987A JPS63299152A JP S63299152 A JPS63299152 A JP S63299152A JP 13314987 A JP13314987 A JP 13314987A JP 13314987 A JP13314987 A JP 13314987A JP S63299152 A JPS63299152 A JP S63299152A
Authority
JP
Japan
Prior art keywords
face
piece
semiconductor element
recess
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13314987A
Other languages
Japanese (ja)
Other versions
JP2583507B2 (en
Inventor
Yoshitaka Fukuoka
義孝 福岡
Yasutoku Niida
仁井田 泰徳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62133149A priority Critical patent/JP2583507B2/en
Publication of JPS63299152A publication Critical patent/JPS63299152A/en
Application granted granted Critical
Publication of JP2583507B2 publication Critical patent/JP2583507B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Abstract

PURPOSE:To attain a sufficient heat sink property without necessity of complicated steps and to perform mounting in a high density by forming in advance an indentation (a recess) in a predetermined region of a circuit substrate to be mounted and arranged with a predetermined semiconductor element, in the recess installing face to face a metal piece having substantially equal thermal expansion coefficient on that of the element to be mounted, and mounting the element on the face of the piece. CONSTITUTION:A first circuit substrate layer 1b having an inner layer wiring 1a is formed by using a green sheet, a hole for a position, region and conduction to mount a semiconductor element is opened thereon, a green sheet (second circuit substrate layer 1d) formed with h predetermined circuit pattern on its surface is laminated, integrally pressurized, and baked. A metal piece 9 having substantially equal thermal expansion coefficient as that of a transistor element, such as a Cu-W piece is mounted and arranged on a metallized layer in the recess of a circuit substrate 1 formed with the recess at the thus obtained predetermined region. Then, a transistor element 5' is mounted and arranged on the exposed face of the piece, i.e., the face of the piece formed substantially in the same plane as the face of the substrate.

Description

【発明の詳細な説明】 [発明の目的] 〈産業上の利用分野) 本発明は半導体素子を配線基板に実装、配設する方法に
係り、特に放熱性を考慮した配線基板への実装方法の改
良に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a method of mounting and arranging a semiconductor element on a wiring board, and particularly relates to a method of mounting a semiconductor element on a wiring board in consideration of heat dissipation. Regarding improvements.

(従来の技術) 集積回路素子(IC)、)ランジスタ素子、電界効果型
トランジスタ(PET) 、ダイオード素子等の半導体
素子を配線基板(プリント配線基板)に実装配設して成
る電子部品は産業用電子機器、民生用電気機器の分野で
多く使用されている。
(Prior art) Electronic components consisting of semiconductor elements such as integrated circuit elements (IC), transistor elements, field effect transistors (PET), and diode elements mounted on a wiring board (printed wiring board) are used for industrial purposes. It is widely used in the fields of electronic equipment and consumer electrical equipment.

しかしてこの種の配線基板に対する半導体素子の実装、
配役はいわゆる高密度実装技術として注目されている。
However, the mounting of semiconductor elements on this type of wiring board,
Casting is attracting attention as a so-called high-density packaging technology.

ところで上記半導体素子を実装して成る電子部品(S積
回路部品)においては、実装する半導体素子の数が増す
につれ(高密度化)、それら半導体素子等による発熱を
いかに放散するかが問題になる。つまり実装する半導体
素子等の動作に伴う発熱が、それら素子の性能に悪影響
を及ぼすので、できるだけ速やかな放熱が望まれる。
By the way, in electronic components (S-product circuit components) formed by mounting the above-mentioned semiconductor elements, as the number of semiconductor elements to be mounted increases (higher density), how to dissipate the heat generated by these semiconductor elements becomes a problem. . In other words, the heat generated by the operation of the semiconductor elements and the like to be mounted has an adverse effect on the performance of those elements, so it is desired that the heat be dissipated as quickly as possible.

こうした事情に対し高密度実装技術において、従来第2
図に示す如き構成を採るものが知られている。すなわち
実装、配設する(flailする)半導体素子のサイズ
に合せ配線基板1に選択的に貫通孔を形設し、この貫通
孔に係合するような突出部2を設けたいわゆる七−トシ
ンク3を組合せる構成である。なおこの場合、ヒートシ
ンク3の突出部−2の上端面は配線基板1面と略平面を
なしており、また配線基板1とは接着剤層4によって一
体化している。しかして上記配線基板1と係合一体化し
たヒートシンク3の突出部2面上に絶縁的に半導体素子
5を実装、配設するととも(:、入出力端子を配線基板
1上の回路パターン端子6にワイヤ7で電気的に接続し
ている。
In response to these circumstances, in high-density packaging technology, conventional
A device having a configuration as shown in the figure is known. That is, a so-called seven-tooth sink 3 has a through hole selectively formed in the wiring board 1 according to the size of the semiconductor element to be mounted and disposed (flailed), and a protrusion 2 that engages with the through hole. This is a configuration that combines the following. In this case, the upper end surface of the protruding portion -2 of the heat sink 3 is substantially flat with the surface of the wiring board 1, and is integrated with the wiring board 1 by the adhesive layer 4. Thus, the semiconductor element 5 is insulatively mounted and arranged on the two surfaces of the protruding portion of the heat sink 3 that is engaged and integrated with the wiring board 1 (:, the input/output terminals are connected to the circuit pattern terminals 6 on the wiring board 1). It is electrically connected to the wire 7 by a wire 7.

しかし上記の方式においては、実装した半導体素子5と
ヒートシンク3との電気絶縁性が不充分であったり、ま
た実装(搭載)する半導体素子の種類や容量によって絶
縁の程度を調整しており工程の煩雑さを避は得ない、加
えてこの方式の場合には、ヒートシンク3を配線基板1
と組合せた後でなければ半導体素子5の実装ができない
し、さ−らに配線基板1は穴開けにより配線領域も減少
するため高密度実装にも限界が自ずからある。
However, in the above method, the electrical insulation between the mounted semiconductor element 5 and the heat sink 3 is insufficient, and the degree of insulation is adjusted depending on the type and capacity of the semiconductor element to be mounted (mounted). Complication is unavoidable, and in addition, in the case of this method, the heat sink 3 is connected to the wiring board 1.
The semiconductor element 5 cannot be mounted unless it is combined with the wiring board 1, and the wiring area of the wiring board 1 is also reduced due to the holes, so there is a limit to high-density mounting.

(発明が解決しようとする問題点) したがって本発明は煩雑な工程など要せずに放熱性が充
分に達成され、かつ高密度の実装も可能な半導体素子の
実装方法を提供することを目的とする。
(Problems to be Solved by the Invention) Therefore, an object of the present invention is to provide a method for mounting semiconductor elements, which achieves sufficient heat dissipation without requiring complicated steps, and which also enables high-density mounting. do.

[発明の構成] (問題を解決するための手段) 本発明においては所要の半導体素子を実装、配設すべき
配m基板の所定領域に窪み(凹部)を予め形設しておき
、この凹部内に、実装する素子と略等しい熱膨脹率を有
する金属片を面を令せて装着し、この金属片の面上に半
導体素子を実装することを骨子としている。
[Structure of the Invention] (Means for Solving the Problem) In the present invention, a recess (recess) is formed in advance in a predetermined area of a mounting board on which a required semiconductor element is to be mounted and arranged, and the recess is The main idea is to mount a metal piece having a coefficient of thermal expansion substantially equal to that of the element to be mounted inside the semiconductor device with its surface parallel to that of the element to be mounted, and to mount the semiconductor element on the surface of this metal piece.

(作用) 本発明によれば、配線基板面の半導体素子が実装される
領域には没設するように金属片が装着され、この金属片
の上面(露出面)に半導体素子が実装される。つまり一
方の面(裏面)側は連続した配線基板面をなしたまま、
他の面(表面)側に選択的に金11L層領域を形設し、
この金属層領域面上に所要の素子は実装され、かつヒー
トシンクとは電気的に絶縁を保持している。このため実
装する各半導体素子の電気的絶縁に対する処置を格別調
整する必要もないし、さらに上記金属片は熱膨脹率が実
装する素子と略等しいものが選ばれている′ので動作瘍
程において、実装した素子の剥離乃至離脱を招来する恐
れもない。
(Function) According to the present invention, a metal piece is installed so as to be submerged in the area on the wiring board surface where the semiconductor element is to be mounted, and the semiconductor element is mounted on the upper surface (exposed surface) of this metal piece. In other words, one side (back side) remains a continuous wiring board surface,
selectively forming a gold 11L layer region on the other surface (front surface) side;
Required elements are mounted on the surface of this metal layer region and are electrically insulated from the heat sink. For this reason, there is no need to make special adjustments to the electrical insulation of each semiconductor element to be mounted, and since the metal piece is selected to have a coefficient of thermal expansion approximately equal to that of the element to be mounted, There is no fear of causing peeling or detachment of the element.

(実施例) 以下、本発明のアルミナセラミック製の基板を用い、パ
ワートランジスタチップを実装(搭載)した例について
説明する。
(Example) Hereinafter, an example in which a power transistor chip is mounted using an alumina ceramic substrate of the present invention will be described.

先ずいわゆるグリーンシートを用いて内層配線を有する
第一の回路基板層を作り、さらにその上梓半導体素子を
実装する位置、領域および導通用の孔をくり抜き、かつ
表面に所要の回路パータンを形成したグリーンシート(
第二の回路基板層を指す)を積層して一体的に加圧、焼
成した。なおこの場合、第一の回路基板層の露出する面
、つまりその上に積層されるグリーンのくり抜き部に対
応する部分にはメタライズ層が予め形成しである。
First, a first circuit board layer having inner layer wiring is made using a so-called green sheet, and then the position and area where the Azusa semiconductor element will be mounted and holes for conduction are cut out, and the required circuit pattern is formed on the surface of the green sheet. Sheet (
(referring to the second circuit board layer) were laminated and integrally pressed and fired. In this case, a metallized layer is previously formed on the exposed surface of the first circuit board layer, that is, on the portion corresponding to the hollowed out portion of the green layer laminated thereon.

かくして得た所定領域に凹部を形設した配線基板の前記
凹部内のメタライズ層上にトランジスタ素子と略同じの
熱IIJwA率を有する金属片、たとえばCu−W系片
を装着、配設する。しかる後、上記配設したCu−W系
片の露出面、つまり配線基板面と略同−面を成すCu−
W系片の面上にトランジスタ素子をそれぞれ実装、配設
する0次いで上記実装したトランジスタ素子の入出力端
子を配線基板面上に予め形成しである回路パターン端子
と、たとえばAg111mのはんだ付けによって電気的
に接続することによって、所要の実装がなされる。
A metal piece, such as a Cu-W type piece, having approximately the same thermal IIJwA rate as the transistor element is mounted and disposed on the metallized layer in the recess of the wiring board in which the recess is formed in the predetermined area thus obtained. After that, the exposed surface of the Cu-W-based piece disposed above, that is, the Cu-
Transistor elements are each mounted and arranged on the surface of the W-based piece.Next, the input/output terminals of the transistor elements mounted above are formed in advance on the surface of the wiring board, and electrical connections are made with circuit pattern terminals by soldering, for example, Ag111m. The required implementation is done by connecting the

第1図はかくしてパワートランジスタ素子を実装した集
積回路部品に、ヒートシンクを取着した集積回路部品を
断面的に示したものである。第1図はおいて1は配線基
板で、内層配線1aを有する第一の回路基板層1bと凹
部ICを有する第二の回路基板jlldとから構成され
ている。また3は配線基板1の裏面側に接着一体化され
たヒートシンクを、5a’はパワートランジスタ素子を
、6は表面の回路パターン端子を、7はAg細線を、8
は第一の回路基板層lb上に設けられたメタライズ層を
、9は配線基板1の凹部IC内に装着、配設されたCu
−W系金属片を、また10は内層パターン1aとの間を
電気的に接続する導体をそれぞ示す。
FIG. 1 is a cross-sectional view of an integrated circuit component in which a heat sink is attached to the integrated circuit component in which a power transistor element is thus mounted. In FIG. 1, reference numeral 1 denotes a wiring board, which is composed of a first circuit board layer 1b having inner layer wiring 1a and a second circuit board jlld having a recessed IC. Further, 3 is a heat sink integrated with adhesive on the back side of the wiring board 1, 5a' is a power transistor element, 6 is a circuit pattern terminal on the front surface, 7 is an Ag thin wire, and 8 is a heat sink integrated with adhesive on the back side of the wiring board 1.
9 is a metallized layer provided on the first circuit board layer 1b, and 9 is a Cu layer mounted and arranged in the recess IC of the wiring board 1.
- A W-based metal piece, and 10 represent a conductor that electrically connects with the inner layer pattern 1a.

なお上記においては、パワートランジスタ素子を実装し
た例について説明したため、配線基板1の四部1c内に
装着した金属片9をコレクタとの接続導体として利用し
たが、実装する半導体素子の種類によって適宜、被実装
面に絶縁層を形成してもよい、また配線基板1は上記の
如く内層配線層1aを備えたいわゆる多層配線型のもの
に限られない、さらに実装する半導体素子は、パワート
ランジスタに限らず集積回路素子、F E T素子、ダ
イオード素子、これらの組合せ、または他の電子部品、
たとえばコンデンサ、抵抗体等との組合せ等でも勿論支
障ない。
In the above description, since an example in which a power transistor element is mounted is described, the metal piece 9 mounted in the four parts 1c of the wiring board 1 is used as a connection conductor with the collector. An insulating layer may be formed on the mounting surface, and the wiring board 1 is not limited to the so-called multilayer wiring type having the inner wiring layer 1a as described above.Furthermore, the semiconductor elements to be mounted are not limited to power transistors. integrated circuit elements, FET elements, diode elements, combinations thereof, or other electronic components;
For example, there is no problem in combination with a capacitor, a resistor, etc.

[発明の効果] 上記の如く本発明によれば、配線基板の半導体素子を実
装する領域が凹部に形設され、この凹部内に金属片が装
着され、この金属片上に前記素子は実装される。しかし
て前記金属片はそれぞれ配線基板の主構成をなす絶縁体
によって電気的に絶縁されているため、実装される他の
半導体素子や取着されるヒートシンクを通じての電気的
な悪影響を招く恐れもない、つまり半導体素子の実装に
おいて実装する半導体素子間の、あるいは別途ヒートシ
ンクを取着した場合も、そのヒートシンクとの間の電気
的絶縁を考慮せずに所要の実装を行い得る。特に放熱性
の改善を考慮してヒートシンクを取着する場合にも、半
導体素子の実装後、ヒートシンクの取着を行い得ること
は量産的な実装手段として有効である。かくして上記半
導体素子を実装する領域が金属片であることに伴い熱伝
導性が良好で、それら実装素子からの発熱も容易に放熱
されること、さらに配線基板においても回路配線領域が
多く確保でき、高密度実装を図り易いことなどの点とあ
いまって実用上多くの利点をもたらすものと言える。
[Effects of the Invention] As described above, according to the present invention, a region of a wiring board in which a semiconductor element is mounted is formed in a recess, a metal piece is mounted in this recess, and the element is mounted on this metal piece. . However, since each of the metal pieces is electrically insulated by an insulator that constitutes the main component of the wiring board, there is no risk of adverse electrical effects passing through other mounted semiconductor elements or attached heat sinks. That is, when mounting semiconductor elements, the required mounting can be performed without considering electrical insulation between the semiconductor elements to be mounted, or even when a heat sink is separately attached. Particularly when attaching a heat sink in consideration of improving heat dissipation, the ability to attach the heat sink after mounting the semiconductor element is effective as a mass-production mounting means. In this way, since the area where the semiconductor elements are mounted is a metal piece, it has good thermal conductivity, and the heat generated from the mounted elements is easily dissipated, and furthermore, a large area for circuit wiring can be secured on the wiring board. Combined with the ease of high-density mounting, this can be said to bring many practical advantages.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明方法によって半導体素子を実装して構成
した集積回路部品の一例を示す断面図、第2図は従来の
実装手段で構成した集積回路部品の一例を示す断面図で
ある。 1・・・・・・・・・配線基板 1d・・・・・・凹部 5′・・・・・・トランジスタ素子(半導体素子)6・
・・・・・・・・回路パターン端子9・・・・・・・・
・Cu−W系片(金属片)出願人      株式会社
 東芝 代理人 弁理士  須 山 佐 − 第2図
FIG. 1 is a sectional view showing an example of an integrated circuit component constructed by mounting semiconductor elements by the method of the present invention, and FIG. 2 is a sectional view showing an example of an integrated circuit component constructed by conventional mounting means. 1...Wiring board 1d...Recessed portion 5'...Transistor element (semiconductor element) 6.
......Circuit pattern terminal 9...
・Cu-W type piece (metal piece) Applicant Toshiba Corporation Representative Patent Attorney Sasu Suyama - Figure 2

Claims (1)

【特許請求の範囲】 所定の回路パターンを有し、かつ厚さ方向に凹部を選択
的に形設した配線基板の前記凹部内に、実装する半導体
素子と熱膨脹率が略同等の金属片を装着する工程と、 前記装着した金属片の露出面上に半導体素子を実装配設
する工程と、 前記実装配設した半導体素子の入出力端子を所定の回路
パターン端子に電気的に接続する工程とを具備して成る
ことを特徴とする半導体素子の実装方法。
[Claims] A metal piece having approximately the same coefficient of thermal expansion as a semiconductor element to be mounted is mounted in the recess of a wiring board having a predetermined circuit pattern and recesses selectively formed in the thickness direction. a step of mounting and arranging a semiconductor element on the exposed surface of the mounted metal piece; and a step of electrically connecting input/output terminals of the mounted semiconductor element to predetermined circuit pattern terminals. A method for mounting a semiconductor device, comprising:
JP62133149A 1987-05-28 1987-05-28 Semiconductor mounting circuit device Expired - Lifetime JP2583507B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62133149A JP2583507B2 (en) 1987-05-28 1987-05-28 Semiconductor mounting circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62133149A JP2583507B2 (en) 1987-05-28 1987-05-28 Semiconductor mounting circuit device

Publications (2)

Publication Number Publication Date
JPS63299152A true JPS63299152A (en) 1988-12-06
JP2583507B2 JP2583507B2 (en) 1997-02-19

Family

ID=15097861

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62133149A Expired - Lifetime JP2583507B2 (en) 1987-05-28 1987-05-28 Semiconductor mounting circuit device

Country Status (1)

Country Link
JP (1) JP2583507B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09283668A (en) * 1996-04-10 1997-10-31 Nec Corp Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856443A (en) * 1981-09-30 1983-04-04 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856443A (en) * 1981-09-30 1983-04-04 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09283668A (en) * 1996-04-10 1997-10-31 Nec Corp Semiconductor device

Also Published As

Publication number Publication date
JP2583507B2 (en) 1997-02-19

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