JPH11191603A - Semiconductor integrated circuit and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve dissipation of the heat generated in a semiconductor chip as well as to simplify the connection structure of ground wiring layer which is arranged on a substrate. SOLUTION: A stepped recess 10 is provided on a multilayered substrate 1 made of glass ceramic for arranging a conductive heat sink 4 inside the recess 10 for fixing a power FET chip 5. The ground lines 2 formed between respective printed substrates 1a-1d are exposed inside the recess 10 on the multilayered substrate 1. In addition, the underside of the heat sink 4 is formed stepwise along the stepped parts of the recess 10 and makes contact with the exposed ground lines 2. The underside of the heat sink 4 is connected to connection parts 11 formed in the printed substrate 1a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device in which a semiconductor chip is bonded on a substrate and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIG. 13 is a sectional view showing a structure of a conventional semiconductor integrated circuit device. In FIG. 13, a conventional semiconductor integrated circuit device has a power FET (field effect transistor) in a concave portion 15 of a multilayer substrate 1 in which a plurality of printed boards (four layers in the illustrated example) 1a to 1d made of an insulating material are stacked. Etc. are arranged. The semiconductor chip 5 is disposed on the upper surface of the printed circuit board 1a serving as the bottom surface of the concave portion 15, and is electrically connected to a circuit wiring layer (not shown) formed on the surface of the printed circuit board 1b in the middle of the multilayer substrate 1 via bonding wires 6. Connected. Ground lines 2 are arranged between the printed boards. Each ground line 2 is connected by a connection portion 16 formed in the thickness direction of the multilayer substrate 1.

In the above-described semiconductor integrated circuit device, the semiconductor chip 5 generates heat during operation. On the other hand, a multilayer substrate 1 made of, for example, glass ceramic has a thermal conductivity of 2.5 W /
Since it is as low as about m · K, it is difficult to sufficiently absorb the heat generated in the semiconductor chip 5 and radiate the heat to the outside. Therefore, the temperature of the semiconductor chip 5 tends to increase. When the temperature of the semiconductor chip 5 rises, the operating characteristics of the semiconductor chip 5 deteriorate.

[0004] Therefore, as shown in FIG.
A concave portion 15 is provided on the multilayer substrate 1 to reduce the thickness of the portion where the semiconductor chip 5 is mounted. Further, a large number of through holes 3 penetrating through the back surface of the multilayer substrate 1 are formed in a portion where the semiconductor chip 5 is mounted, and the inside of the through holes 3 is filled with a heat conductive material to form a heat radiating portion 17. . Thereby, the heat generated in the semiconductor chip 5 is transmitted to the heat radiating portion 17 and is radiated from the back surface of the multilayer substrate 1, thereby suppressing the temperature rise of the semiconductor chip 5.

[0005]

However, in the structure using the heat radiating portion 17, the amount of heat radiated is limited. For example, when the amount of heat generated from the semiconductor chip 5 becomes 2 to 3 W or more, the amount of radiated heat becomes insufficient. In recent years, higher output has been demanded for the semiconductor chip 5 such as a power FET, and the amount of heat generated by the semiconductor chip 5 tends to increase. Therefore, the temperature of the semiconductor chip 5 rises, and the characteristics of the semiconductor chip 5 are deteriorated.

The ground line 2 formed between the printed boards of the multilayer substrate 1 and on the surface thereof is connected to the ground of the main substrate on which the semiconductor integrated circuit device is mounted via a connecting portion 16 extending to the back side of the multilayer substrate 1. Connected to line.
The through-hole in which the connecting portion 16 is formed is formed by forming a through-hole in a predetermined position on each of the printed boards 1a to 1d of the multilayer board 1 and then stacking the printed boards 1a to 1d. . For this reason, each printed circuit board 1a
In some cases, the conductive characteristics of the ground line 2 may change due to a shift in the formation positions of the through holes 1 to 1d, or a defective filling of the conductive metal material filled in the through holes.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device having improved heat dissipation of heat generated in a semiconductor chip and a simplified connection structure of a ground wiring layer provided on a substrate, and a method of manufacturing the same. It is to be.

[0008]

Means for Solving the Problems and Effects of the Invention (1)
First Invention A semiconductor integrated circuit device according to a first invention has a semiconductor chip provided via a heat sink on a substrate on which a wiring layer is formed, and the wiring layer is electrically connected to the heat sink. .

In the semiconductor integrated circuit device according to the present invention, since the semiconductor chip is disposed on the heat sink, heat generated in the semiconductor chip during operation is transmitted to the heat sink and diffused. Therefore, the temperature rise of the semiconductor chip is suppressed, and the semiconductor chip can perform a stable operation.

[0010] The wiring layer is connected via a heat sink. For this reason, the connection part for connecting the wiring layers can be omitted, the structure is simplified, and the wiring layers can be reliably connected.

(2) Second invention A semiconductor integrated circuit device according to a second invention is the semiconductor integrated circuit device according to the first invention, wherein the wiring layer is a ground wiring layer.

In this case, the ground wiring layer can be easily and reliably connected by the heat sink.

(3) Third invention A semiconductor integrated circuit device according to a third invention is the semiconductor integrated circuit device according to the first or second invention, wherein the heat sink is made of a material having conductivity and heat conductivity. It becomes.

In this case, the wiring layers are electrically connected by the conductivity of the heat sink, and heat is absorbed from the semiconductor chip by the heat conductivity, so that the temperature rise of the semiconductor chip can be suppressed.

(4) Fourth Invention A semiconductor integrated circuit device according to a fourth invention has a substrate having an opening and a ground wiring layer formed thereon, and a ground wiring layer disposed in the opening of the substrate. It is provided with a heat sink to be connected and a semiconductor chip arranged on the heat sink.

In the semiconductor integrated circuit device according to the present invention, an opening is provided in the substrate, a heat sink is arranged in the opening, and a semiconductor chip is arranged on the heat sink. For this reason, the heat generated during the operation of the semiconductor chip is transmitted to the heat sink, whereby the temperature rise of the semiconductor chip can be suppressed. Further, by disposing the semiconductor chip on the heat sink, the distance between the wiring layer formed on the upper surface of the substrate and the semiconductor chip is reduced,
Thereby, the connecting wires can be shortened.

(5) Fifth Invention A semiconductor integrated circuit device according to a fifth invention is the semiconductor integrated circuit device according to the fourth invention, wherein the substrate is a multi-layer substrate in which a plurality of wiring substrates are stacked. Wherein the ground wiring layer comprises one or more ground conductors formed on the front or back surface of one or more wiring boards of the multilayer substrate, and the heat sink is electrically connected to at least one ground conductor in the opening. Things.

In this case, the use of the multi-layer substrate reduces the plane occupied area of the semiconductor integrated circuit device, and can increase the mounting density of the device on which the semiconductor integrated circuit device is mounted.

(6) Sixth invention A semiconductor integrated circuit device according to a sixth invention is the semiconductor integrated circuit device according to the fifth invention, wherein the ground wiring layer comprises a plurality of ground conductors and a plurality of ground conductors. A part of at least two of the conductors is exposed in the opening, and the heat sink is in contact with a part of the at least two grounding conductors exposed in the opening.

In this case, a part of at least two ground conductors exposed in the opening are electrically connected by contacting the heat sink. Therefore, it is not necessary to provide a connecting portion for connecting at least two ground conductors, and the wiring structure of the semiconductor integrated circuit device can be simplified.

(7) Seventh invention A semiconductor integrated circuit device according to a seventh invention is the semiconductor integrated circuit device according to the fifth or sixth invention, wherein the opening comprises a recess having a bottom surface, A portion of the at least one ground conductor is exposed in the recess, and the heat sink is in contact with a portion of the at least one ground conductor exposed in the recess.

In this case, a concave portion is provided in the substrate, and a heat sink is arranged in the concave portion. For this reason, the region where heat is transmitted from the semiconductor chip via the heat sink, that is, the thickness of the substrate at the bottom of the concave portion is reduced, and the heat dissipation of the substrate itself is improved.

(8) Eighth Invention A semiconductor integrated circuit device according to an eighth invention is the semiconductor integrated circuit device according to the seventh invention, wherein the recess is formed in a stepped shape, and at least one ground conductor is provided. A part is exposed on the bottom surface or the step in the recess, and the heat sink has a step corresponding to the step-shaped recess, and the step is in contact with a part of the ground conductor exposed in the recess. It is.

In this case, a part of the ground conductor can be easily exposed on the step by forming the recess in a step shape. Further, by forming a stepped portion corresponding to the stepped concave portion on the heatsink, it becomes easy to connect the heatsink to the ground conductor exposed in the concaved portion.

(9) Ninth Invention A semiconductor integrated circuit device according to a ninth invention is the same as the semiconductor integrated circuit device according to the eighth invention, except that a conductive through portion is provided on the bottom surface of the concave portion. is there.

In this case, by connecting the conductive through-hole exposed on the lower surface of the multilayer substrate to an external ground wiring, each ground conductor in the multilayer substrate can be electrically connected to the external ground wiring.

(10) Tenth invention A semiconductor integrated circuit device according to a tenth invention is the semiconductor integrated circuit device according to the fifth or sixth invention,
The opening comprises a through hole, at least a part of the at least one ground conductor is exposed in the through hole, and the heat sink is in contact with a part of the at least one ground conductor exposed in the through hole.

In this case, by exposing a part of the ground conductor inside the through hole and disposing a heat sink inside the through hole, the heat sink can be used as a connection portion of the ground conductor. Can be simplified.

(11) Eleventh invention A semiconductor integrated circuit device according to an eleventh invention is the semiconductor integrated circuit device according to the tenth invention, wherein the through hole is formed in a stepped shape, and the heat sink is formed in a stepped shape. A step portion corresponding to the through hole, a part of at least one ground conductor is exposed at a lower end opening in the through hole, a step upper surface or a step lower surface, and the heat sink is provided at the step portion corresponding to the step-shaped through hole. And the step portion is in contact with a part of the ground conductor exposed in the through hole.

In this case, by forming the through hole in a step shape, a part of the ground conductor can be easily exposed to the step upper surface or the step lower surface. Further, by forming a step portion corresponding to the stepped through hole in the heat sink, it becomes easy to connect the heat sink to the ground conductor exposed in the through hole.

(12) Twelfth Invention A semiconductor integrated circuit device according to a twelfth invention is the semiconductor integrated circuit device according to the eleventh invention, wherein the lower surface of the heat sink is arranged substantially flush with the rear surface of the multilayer substrate. It was done.

In this case, when the rear surface of the multilayer substrate is mounted on a substrate or the like outside the semiconductor integrated circuit device, the lower surface of the heat sink can be used as a connection portion with the wiring of the external substrate. Connection with the camera becomes easy.

(13) Thirteenth Invention The semiconductor integrated circuit device according to the thirteenth invention is characterized in that:
In the configuration of the semiconductor integrated circuit device according to any one of the second inventions, a connection hole for electrically connecting at least two ground conductors is formed in a wiring board between at least two ground conductors among the plurality of ground conductors. Things.

In this case, the ground conductor formed at a position distant from the heat sink can be easily connected using the connection hole.

(14) Fourteenth Invention A method of manufacturing a semiconductor integrated circuit device according to a fourteenth invention is described below.
In a method of manufacturing a semiconductor integrated circuit in which a semiconductor chip is provided on a multilayer substrate having a ground wiring layer formed thereon, the multilayer substrate having an opening and a plurality of ground wiring layers exposed in the opening is formed. Preparing, and forming a heat sink having a shape connectable to the plurality of ground wiring layers exposed in the opening, arranging the heat sink in the opening, and connecting the heat sink to the ground wiring layer, Mounting a semiconductor chip on a heat sink.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a multilayer substrate having a stepped opening and a ground wiring layer exposed in the opening is prepared. Further, the heat sink is formed in a shape connectable to the plurality of ground wiring layers exposed in the opening. Then, the ground wiring layer is electrically connected by disposing the heat sink in the opening, and the semiconductor chip is mounted on the heat sink. As a result, it is possible to obtain a semiconductor integrated circuit device in which the connection structure of the ground wiring layer is simplified and the temperature rise of the semiconductor chip is suppressed.

(15) Fifteenth Invention A method of manufacturing a semiconductor integrated circuit device according to the fifteenth invention is as follows.
In the configuration of the method of manufacturing a semiconductor integrated circuit device according to a fourteenth aspect, the inner surface of the opening of the multilayer substrate is formed in a step shape, and the step of forming the heat sink includes: A step-shaped surface corresponding to the step is formed.

In this case, by forming a step-like surface corresponding to the inner surface of the step-like opening in the heat sink,
It becomes easy to expose a part of the ground wiring layer in the opening, and in addition, it becomes easy to make the exposed surface of the ground wiring layer contact the stepped surface of the heat sink to make electrical connection.

[0039]

FIG. 1 is a sectional view of a semiconductor integrated circuit device according to a first embodiment of the present invention. In the semiconductor integrated circuit device of FIG. 1, a power FET chip 5 is arranged in a concave portion 10 of a multilayer substrate 1 via a heat sink 4.

The multilayer substrate 1 is formed by stacking a plurality of printed boards (wiring boards) made of glass ceramic, in the illustrated example, four printed boards 1a to 1d in the vertical direction. On the upper and lower surfaces, a ground line (ground wiring layer) 2 or a circuit wiring layer (not shown) composed of a ground conductor pattern is provided. Further, a stepped concave portion 10 is formed in the multilayer substrate 1, and a part of the ground line 2 is exposed on the upper surface of the stepped portion of the concave portion 10.

A large number of through holes 3 are formed in the lowermost printed circuit board 1a of the multilayer substrate 1, and the inside of the through holes 3 is a connection portion 1 filled with a conductive metal material.
1 is formed.

The heat sink 4 is arranged in the concave portion 10 of the multilayer substrate 1. The heat sink 4 is made of Cu (copper),
It is made of a metal material such as a copper alloy such as Fe (iron), Al (aluminum), and CuW (copper-tungsten) alloy or an AgPt (silver-platinum) alloy, and has a stepped portion along the inner surface of the stepped recess 10. Have. When the heat sink 4 is arranged in the concave portion 10 of the multilayer board 1, the bottom surface 4a of the heat sink 4 is connected to the ground line 2 formed on the upper surface of the printed board 1a, and each stepped portion at the lower part of the heat sink 4 is connected to the intermediate printed board. It is connected to the ground line 2 exposed on the upper surfaces of 1b and 1c.

The power FET chip 5 is mounted on the upper surface of the heat sink 4. Then, the power FET chip 5, the circuit wiring layer (not shown) formed on the surface of the multilayer substrate 1, and the heat sink 4 are connected by bonding wires 6 and 7, respectively. On the upper surface of the multilayer substrate 1, chip components 9 such as a chip capacitor, a resistor, and an inductor are arranged.

Further, the concave portion 10 in which the power FET chip 5 and the heat sink 4 are arranged is covered with a protective layer 8 made of epoxy resin.

The semiconductor integrated circuit device shown in FIG. 1 is mounted on a main substrate 20 of a device in which the semiconductor integrated circuit device is incorporated so that the back surface of the multilayer substrate 1 is in contact. Then, a ground line (not shown) formed on the main substrate 20 is connected to the connection portion 11 exposed on the back surface of the multilayer substrate 1. Thereby, each ground line 2 provided in the multilayer substrate 1 is electrically connected to the ground line of the main substrate 20 via the connection portion 11 and the heat sink 4.

In one example of the semiconductor integrated circuit device having the above structure, the size of the glass ceramic multilayer substrate 1 is 10
× 10 mm, and the size of the recess 10 is 2 × 3 mm. The power FET chip 5 has a gate length of 1 μm,
Gate width is 16mm and chip size is 0.8 × 1.2
mm.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described. 2 to 6 are cross-sectional views illustrating the steps of manufacturing the semiconductor integrated circuit device of FIG.

In FIG. 2, first, a multilayer substrate 1 is formed. In the process of forming the multilayer substrate 1, a plurality of thin substrates made of glass ceramic or the like are prepared, and an opening for forming the concave portion 10, a ground line 2 and a circuit wiring layer are formed on each substrate, and the printed substrates 1a to 1d are formed. Form. Further, the ground line 2 and the plurality of connection portions 11 are formed on the printed board 1d. The connection part 11 is a printed circuit board 1
d, a through hole 3 is formed, and a conductive metal material is filled therein. Then, each printed circuit board 1
The multi-layer substrate 1 having the concave portions 10 is formed by laminating a to 1d.

Next, referring to FIG.
A heat sink 4 made of silver-plated copper is placed in the area 0. As described above, the lower portion of the heat sink 4 is formed in a step shape, and the lower surface of the step of the heat sink 4 contacts each of the ground lines 2 exposed in the concave portion 10. In this state, the lower surface of the step of the heat sink 4 and the ground line 2 are bonded using AuSn solder.

Further, in FIG. 4, the power FET chip 5 is placed on the upper surface of the heat sink 4 and bonded by soldering.

Further, in FIG. 5, the electrode pattern on the surface of the power FET chip 5 and the circuit wiring layer (not shown) on the surface of the multilayer substrate 1 and the heat sink 4 are connected by bonding wires 6 and 7 made of gold.

Further, in FIG. 6, an epoxy resin is dropped into the concave portion 10 of the multilayer substrate 1 and cured. Thus, a protective layer 8 covering the entire concave portion 10 in which the heat sink 4 and the power FET chip 5 are arranged is formed. Further, a chip component 9 such as a chip capacitor is soldered to the surface of the multilayer substrate 1 to manufacture the semiconductor integrated circuit device shown in FIG.

The above semiconductor integrated circuit device has a power FE
The heat sink 4 is attached directly below the T chip 5. The heat sink 4 is formed from a substrate material, for example, a material having a higher thermal conductivity than glass ceramic or the like, for example, copper. And while the thermal conductivity of glass ceramic is 2.5 W / m · K, copper is 403 W / m · K.
K. For this reason, the heat generated during the operation of the power FET chip 5 diffuses into the heat sink 4 and is transmitted, so that the temperature rise of the power FET chip 5 can be suppressed.

The thermal resistance of the semiconductor integrated circuit device having the heat sink 4 shown in FIG. For comparison, the thermal resistance of a conventional semiconductor integrated circuit device without using a heat sink was also measured. The size of the heat sink 4 used for the measurement is 1.5 × 1.5 mm at the bottom of the step and 2 × 3 mm at the top. FIG. 7 is a sectional view of a semiconductor integrated circuit device of a comparative example. The measurement samples of the semiconductor integrated circuit device A of FIG. 1 and the conventional semiconductor integrated circuit device B of FIG. 7 were mounted on an aluminum heat sink of 25 × 25 × 5 mm. And by the ΔVF method,
Power pulses were applied to the power FET chips of the semiconductor integrated circuit devices A and B of the present invention and the comparative example while changing the application time, and the forward voltage of the power FET chips at that time was measured. Further, the thermal resistance was calculated by converting the measured forward voltage value. The thermal resistance indicates a rise in the temperature of the channel of the power FET with respect to the power supplied to the power FET chip.

FIG. 8 is a diagram showing a calculation result of a transient thermal resistance characteristic of the semiconductor integrated circuit device. As can be seen from FIG. 8, when the application time of the power pulse applied to the power FET chip exceeds 0.1 second, the semiconductor integrated circuit device A of the present invention having the heat sink 4 attached thereto has The thermal resistance is reduced by about 10 ° C./W as compared with the integrated circuit device B. That is, the heat dissipation effect of the power FET chip is greater in the semiconductor integrated circuit device A of the present invention. In particular, when the application time of the power pulse is infinite, that is, in a steady state, the thermal resistance of the semiconductor integrated circuit device A of the present invention shows a low value of about 35 ° C./W as compared with the conventional semiconductor integrated circuit device B. ing. Thus, by providing the heat sink 4 directly below the power FET chip 5, the temperature rise of the power FET chip 5 is suppressed, and the operating characteristics of the power FET chip 5 are stabilized.

Further, the use of the heat sink 4 makes the distance between the power FET chip 5 and the circuit wiring layer on the upper surface of the multilayer substrate 1 shorter than in the conventional semiconductor integrated circuit device shown in FIG. Thereby, the bonding wire 6
Can be shortened.

FIG. 9 is a sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention. The semiconductor integrated circuit device according to the second embodiment is different from the semiconductor integrated circuit device according to the first embodiment in that a stepped through hole 12 is formed instead of the concave portion 10 of the multilayer substrate 1 and the lower surface of the heat sink 14 is That is, the through hole 12 exposes the rear surface of the multilayer substrate 1.

In this case, when the semiconductor integrated circuit device is mounted on the main board, the ground line formed on the main board and the exposed lowermost surface of the heat sink 14 come into contact. Thereby, the ground line of the main board and the ground line 2 formed in the multilayer board 1 can be electrically connected via the heat sink 1.

FIG. 10 is a sectional view of a semiconductor integrated circuit device according to a third embodiment of the present invention. The difference between the semiconductor integrated circuit device according to the third embodiment and the semiconductor integrated circuit device according to the first embodiment is that the ground line 2 or the circuit wiring layer (not shown) formed at different positions in the thickness direction of the multilayer substrate 1 is provided. ) Are connected by the conductive connection portion 13 formed in the multilayer substrate 1. In the example of FIG.
A ground line 2 formed between the printed board 1b and the printed board 1c and a ground line 2 formed on the upper surface of the multilayer board 1 are connected by a connection portion 13.
The connection is not limited to the example of FIG. 10, and the other ground lines 2 may be connected by the connection unit 13. In this case, it is possible to easily connect the ground lines 2 formed at positions away from the heat sink 4 by using the connection portions 13.

FIG. 11 is a sectional view of a semiconductor integrated circuit device according to a fourth embodiment of the present invention. The semiconductor integrated circuit device according to the fourth embodiment is different from the semiconductor integrated circuit device according to the first embodiment in that a stepped through hole 33 is formed instead of the concave portion 10 of the multilayer substrate 1. The through hole 33 of the multilayer substrate 1 has an opening in the upper printed board 1d, and is formed in a stepped shape such that the opening width increases toward the lower printed board 1a. The heat sink 34
Is formed stepwise so that the upper part thereof is along the stepped through hole 33 of the multilayer substrate 1. The lower surface of the heat sink 34 is connected to the back metal 18 formed on the lower surface of the multilayer substrate 1.

At the time of mounting, the back metal 18 of the semiconductor integrated circuit device is connected to the ground line of the main substrate. Thereby, the ground line of the main board and the ground line 2 in the multilayer board 1 are electrically connected via the heat sink 34. In the semiconductor integrated circuit device according to this embodiment, the mounting area on the upper surface of the multilayer substrate 1 can be increased as compared with the conventional semiconductor integrated circuit device. For this reason,
Chip components 9 such as resistors, capacitors, and inductors can be mounted on the upper surface of the multilayer substrate 1 at high density.

FIG. 12 is a sectional view of a semiconductor integrated circuit device according to a fifth embodiment of the present invention. In the semiconductor integrated circuit device according to the fifth embodiment, a through hole 43 having an inner surface parallel to the thickness direction of the multilayer substrate 1 is formed. The end of the ground line 2 formed between the layers of the multilayer substrate 1 is exposed on the inner surface of the through hole 43. In addition, the through hole 4
A conductive heat sink 44 is arranged in 3.
A conductive adhesive such as AuSn (gold-tin), solder, or Ag paste is inserted into a gap between the heat sink 44 and the through hole 43 of the multilayer substrate 1, and the heat sink 44 and each ground line 2 are bonded. The lower surface of the heat sink 44 is formed on the back metal 18 formed on the back surface of the multilayer substrate 1.
It is connected to the.

When the semiconductor integrated circuit device of this embodiment is mounted on a main substrate, the ground line of the main substrate is connected to the back metal 18. Thereby, the ground line of the main board and the ground line 2 of the multilayer board 1 are connected to the heat sink 4.
4 are electrically connected. In this semiconductor integrated circuit device, since the processing of the through-hole 43 is facilitated, the cost for processing the substrate can be reduced.

As described above, the semiconductor integrated circuit device according to the present invention uses the power FE by using the heat sink.
The heat radiation characteristics of the semiconductor chip such as T can be improved, and stable operation characteristics can be maintained. Furthermore, by connecting the ground lines using a conductive heat sink, it is possible to easily connect the ground lines, and to secure stable conductivity.

The present invention can be applied not only to a semiconductor integrated circuit device provided with the power FET chip 5 but also to a semiconductor integrated circuit device provided with another semiconductor chip.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the semiconductor integrated circuit device of FIG. 1;

FIG. 3 is a sectional view showing a manufacturing process of the semiconductor integrated circuit device of FIG. 1;

FIG. 4 is a sectional view showing a manufacturing step of the semiconductor integrated circuit device of FIG. 1;

FIG. 5 is a sectional view showing a manufacturing step of the semiconductor integrated circuit device of FIG. 1;

FIG. 6 is a sectional view showing a manufacturing step of the semiconductor integrated circuit device of FIG. 1;

FIG. 7 is a sectional view of a semiconductor integrated circuit device according to a comparative example of the present invention.

FIG. 8 is a diagram showing transient thermal resistance characteristics of the semiconductor integrated circuit devices of the present invention and a comparative example.

FIG. 9 is a sectional view of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 10 is a sectional view of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 11 is a sectional view of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 12 is a sectional view of a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

FIG. 13 is a sectional view of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multilayer board 2 Ground line 3 Through hole 4,14,34,44 Heat sink 5 Power FET chip 6,7 Bonding wire 10,23 Concave part 33,43 Through hole 11,13 Connection part

Claims (15)

[Claims] 1. A semiconductor integrated circuit device, wherein a semiconductor chip is provided on a substrate on which a wiring layer is formed via a heat sink, and the wiring layer is electrically connected to the heat sink. 2. The semiconductor integrated circuit device according to claim 1, wherein said wiring layer is a ground wiring layer. 3. The semiconductor integrated circuit device according to claim 1, wherein said heat sink is made of a material having conductivity and heat conductivity. 4. A substrate having an opening and a ground wiring layer formed thereon, a heat sink disposed in the opening of the substrate and connected to the ground wiring layer, and a semiconductor disposed on the heat sink. A semiconductor integrated circuit device comprising a chip. 5. The multi-layer board in which a plurality of wiring boards are stacked, wherein the ground wiring layer is one or a plurality of grounds formed on a surface or a back surface of one or more wiring boards of the multi-layer board. 5. The semiconductor integrated circuit device according to claim 4, comprising a conductor, wherein the heat sink is electrically connected to at least one ground conductor in the opening. 6. The ground wiring layer includes a plurality of ground conductors, at least two of the plurality of ground conductors are exposed in the opening, and the heat sink is exposed in the opening. 6. The semiconductor integrated circuit device according to claim 5, wherein said semiconductor integrated circuit device is in contact with a part of at least two ground conductors. 7. The opening comprises a recess having a bottom surface, a part of at least one ground conductor is exposed in the recess, and the heat sink is a part of the at least one ground conductor exposed in the recess. 7. The semiconductor integrated circuit device according to claim 5, wherein the semiconductor integrated circuit device is in contact with a part. 8. The recess is formed in a step shape, a part of the at least one ground conductor is exposed on a bottom surface or a step in the recess, and the heat sink is a step corresponding to the step-shaped recess. 8. The semiconductor integrated circuit device according to claim 7, further comprising a portion, wherein the step portion is in contact with a part of the ground conductor exposed in the concave portion. 9. The semiconductor integrated circuit device according to claim 8, wherein a conductive through portion is provided on a bottom surface of said concave portion. 10. The opening comprises a through hole, a part of at least one ground conductor is exposed in the through hole, and the heat sink is a part of the at least one ground conductor exposed in the through hole. 7. The semiconductor integrated circuit device according to claim 5, wherein the semiconductor integrated circuit device is in contact with the semiconductor integrated circuit device. 11. The through hole is formed in a stepped shape, the heat sink has a stepped portion corresponding to the stepped through hole, and a part of the at least one ground conductor is a lower end in the through hole. The heat sink has a step corresponding to the step-shaped through-hole, the step being in contact with a part of the ground conductor exposed in the through-hole. 11. The method according to claim 10, wherein
13. The semiconductor integrated circuit device according to claim 1. 12. The semiconductor integrated circuit device according to claim 11, wherein a lower surface of said heat sink is arranged substantially flush with a rear surface of said multilayer substrate. 13. The wiring board between at least two ground conductors among the plurality of ground conductors, wherein a connection hole for electrically connecting the at least two ground conductors is formed. 13. The semiconductor integrated circuit device according to any one of 12. 14. A method for manufacturing a semiconductor integrated circuit in which a semiconductor chip is provided on a multilayer substrate having a ground wiring layer formed thereon, wherein the plurality of ground wiring layers having an opening and being exposed to the opening are provided. Preparing the multi-layer substrate on which is formed; forming a heat sink having a shape connectable to the plurality of ground wiring layers exposed in the opening; and disposing the heat sink in the opening. A method for manufacturing a semiconductor integrated circuit device, comprising: a step of connecting the heat sink to the ground wiring layer; and a step of mounting the semiconductor chip on the heat sink. 15. The step of forming the heat sink, wherein the inner surface of the opening of the multilayer substrate is formed in a step shape, wherein the step of forming the heat sink corresponds to the step of the inner surface of the opening of the multilayer substrate in the heat sink. The method for manufacturing a semiconductor integrated circuit device according to claim 14, wherein a stepped surface is formed.