JP3578366B2 - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device Download PDF

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Publication number
JP3578366B2
JP3578366B2 JP26835495A JP26835495A JP3578366B2 JP 3578366 B2 JP3578366 B2 JP 3578366B2 JP 26835495 A JP26835495 A JP 26835495A JP 26835495 A JP26835495 A JP 26835495A JP 3578366 B2 JP3578366 B2 JP 3578366B2
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Prior art keywords
wiring board
multilayer wiring
electrode terminals
integrated circuit
circuit device
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JPH09116091A (en
Inventor
雅仁 沼波
勝治 土屋
恒雄 遠藤
康弘 布川
岩道 神代
徹朗 安達
一雄 須藤
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Renesas Technology Corp
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Renesas Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce the mounting area by connecting the electrode of an active component mounted on the major plane of a multilayer interconnection board with the interconnection of the multilayer interconnection board with wire and fixing the major plane of the multilayer interconnection board by covering it with a cap and providing a plurality of electrode terminals of the multilayer interconnection at the rear plane. SOLUTION: On the major plane of a multilayer interconnection board 2, a semiconductor chip 45, being an active component, and a Zener diode 50, capacitor 53, etc., being passive components, are mounted. Then, the electrode of the semiconductor chip 45 is connected with first layer interconnection 30 by conductive wire 46. In such conditions, a cap 4 is fixed by permitting the cap to cover the major plane of the multilayer interconnection board 2 through solder 3, and a plurality of electrode terminals are provided at the rear plane of the multilayer interconnection board 2. Thus, the size of the interconnection board is reduced and the size of the package is reduced. As a result, mounting area can be reduced.

Description

【０００１】
【発明の属する技術分野】
本発明は低温焼成多層配線基板を用いた混成集積回路装置に関し、特にセルラー電話機等の送信部に用いる小型の高周波電力増幅装置（高周波パワーモジュール：ＲＦパワーモジュール）に適用して有効な技術に関する。
【０００２】
【従来の技術】
自動車電話，携帯電話等の移動通信機器無線部に使用されるＲＦパワーモジュールは、金属製のフランジとキャップとによってパッケージが形成されている。また、前記パッケージの一側面から信号端子等の電極端子を突出させるとともに、パッケージの両端下部からグランド電極を兼ねた取付用フィンを突出させる構造となっている。
【０００３】
また、前記パッケージ内において、前記フランジ上には両面に導体を有する配線基板が固定されている。この配線基板は、誘電体基板の表面に回路パターンを設け、裏面にグランド（ＧＮＤ）パターンを設けた所謂マイクロストリップライン構造となっている。また、前記配線基板は、部分的に穴が設けられている。そして、前記穴底のフランジ部分には熱伝導性の良好なヒートシンクが固定されている。前記ヒートシンクには電界効果トランジスタからなる半導体チップが固定されている。
【０００４】
高周波パワーモジュール（高周波電力増幅用ＭＯＳ・パワーモジュール）については、日立評論社発行「日立評論」１９９３年第４号、同年４月２５日発行、Ｐ１２〜Ｐ２６に記載されている。同文献には、幅２２ｍｍ，奥行き１２ｍｍ，高さ３．７ｍｍのＥ型の高周波パワーモジュールが開示されている。
【０００５】
【発明が解決しようとする課題】
従来の高周波パワーモジュールは、大別すると、金属製のフランジ（ヘッダ）と、このフランジ上に固定される配線基板と、前記配線基板に設けた穴を利用しかつ前記フランジに固定したヒートシンク上に固定される半導体チップと、前記フランジに固定され前記配線基板を覆うキャップと、前記配線基板に固定され先端を前記キャップの外に突出させる電極端子（リード）とからなっている。また、前記フランジの両端は部分的にキャップの外側に突出してグランド電極を兼ねた取付用フィンを構成している。
【０００６】
なお、前記配線基板の表面にはコンデンサ，抵抗，ツェナーダイオード等の電子部品が搭載されている。また、配線基板の表面の配線と前記半導体チップの電極とは導電性のワイヤで接続されている。
【０００７】
従来の高周波パワーモジュールの小型化，高性能化，低コスト化等を検討した結果、以下の事項が小型化，高機能化，低コスト化等を妨げるということが判明した。
【０００８】
（１）配線基板は、誘電体基板の表面に信号配線や電源配線等の回路パターンを設け、裏面にグランド（ＧＮＤ）パターンを設けたマイクロストリップライン構造となっている。これは、配線基板の作製後、抵抗をトリミングしたり、線路幅の調整を行って特性の調整を行うためである。しかし、誘電体基板の一面に信号配線を形成するマイクロストリップライン構造では、所望の電気特性を得るために、信号配線の引き回し長さが長いことから、配線基板が大型化し、この配線基板を内蔵するパッケージが大きくなり、高周波パワーモジュールの小型化が妨げられている。
【０００９】
（２）フランジ上に配線基板を固定し、さらにキャップで覆う構造となるため、パッケージの高さが大きくなり、高周波パワーモジュールの小型化が妨げられている。
【００１０】
（３）フランジの両端の一部は、キャップの外側に突出してグランド電極を兼ねた取付用フィンを構成することから高周波パワーモジュールが大型化する。したがって、実装面積も大きくなる。
【００１１】
（４）パッケージ（キャップ）の一側面から長くリードを突出させることから高周波パワーモジュールが大型化する。したがって、実装面積も大きくなる。
【００１２】
（５）半導体チップの表面と、配線基板の配線面の高さが異なるため、半導体チップの電極と配線を接続するワイヤが長くなる。また、半導体チップは、配線基板に設けた穴の底部分のフランジに固定されたヒートシンク上に固定されるため、半導体チップの電極と配線との間隔が長くなり、ワイヤが長くなる。ワイヤが長くなると抵抗が増大し高周波特性が低くなる。例えば出力ゲインが小さくなる。
【００１３】
（６）配線基板は誘電体基板で形成されているため、発熱量の大きい半導体チップを直接配線基板に搭載することができないため、配線基板に穴を設け、この穴底の金属製のフランジ部分に熱伝導性の良好なヒートシンクを固定し、このヒートシンクに半導体チップを固定する構造となるため、部品点数の増大と、組立工数の増大から高周波パワーモジュールのコストの高騰を招いている。
【００１４】
（７）支持部材，放熱部材，グランド電極を兼ねるフランジを配線基板に固定する構造となっていることから、部品点数が増大する。
【００１５】
（８）高周波パワーモジュールの実装のため、フランジの一部を成形して取付用フィンを形成しているが、成形のため各取付用フィンの実装面高さがばらつきやすくなり、実装の信頼性を損なうこともある。
【００１６】
本発明の目的は、実装面積の縮小化が図れる小型の混成集積回路装置を提供することにある。
【００１７】
本発明の他の目的は、高性能な混成集積回路装置を提供することにある。
【００１８】
本発明の他の目的は、製造コストの低減が達成できる混成集積回路装置を提供することにある。
【００１９】
本発明の前記ならびにそのほかの目的と新規な特徴は、本明細書の記述および添付図面からあきらかになるであろう。
【００２０】
【課題を解決するための手段】
本願において開示される発明のうち代表的なものの概要を簡単に説明すれば、下記のとおりである。
【００２１】
（１）混成集積回路装置は以下の構造となっている。
【００２２】
（ａ）多層配線基板と、前記多層配線基板の主面に搭載される少なくとも一つ以上の能動部品および受動部品と、前記能動部品の電極と前記多層配線基板の配線とを接続する導電性のワイヤと、前記多層配線基板の主面を覆うように多層配線基板に固定されるキャップと、前記多層配線基板の裏面に設けられた前記多層配線の複数の電極端子とを有する。
【００２３】
（ｂ）前記多層配線基板には電界効果トランジスタを構成する半導体チップが多段に接続配置されて高周波パワーモジュールを構成している。
【００２４】
（ｃ）前記多層配線基板は配線を介在させて誘電体層を多段に積み重ねた構造となるとともに、前記誘電体層間に設けられた信号配線はその上下を誘電体層を介してグランド配線で挟まれるストリップライン構造となっている。また、多層配線基板の上部分はマイクロストリップライン構造となっている。
【００２５】
（ｄ）前記グランド配線は編み目構造となっている。
【００２６】
（ｅ）前記能動部品において半導体チップは前記多層配線基板の主面に設けられた窪みに固定され、前記半導体チップの電極面と前記多層配線基板の配線面の高さは略同一高さとなり、前記半導体チップの電極と前記配線を接続する前記ワイヤは略直線状に延在している。
【００２７】
（ｆ）前記多層配線基板の所望部分には、所望の誘電体層から最下層の誘電体層まで貫通延在するサーマルビィアが設けられている。
【００２８】
（ｇ）前記サーマルビィアの上には半導体チップが位置している。
【００２９】
（ｈ）前記多層配線基板の裏面の電極端子において、グランド電極端子はその表面が実装用接合材に濡れないレジスト膜で部分的に覆われて相互に独立した複数の電極端子となっている。
【００３０】
（ｉ）前記多層配線基板の裏面の電極端子の配列間隔は同一ピッチとなっている。
【００３１】
（ｊ）前記多層配線基板の裏面の電極端子のうち、少なくともグランド電極以外の電極端子は多層配線基板の側面の上下に延在する端面スルーホール端子を介して各層の配線に接続されている。
【００３２】
（ｋ）前記多層配線基板は低温焼成多層セラミック基板となり、配線は銀系金属からなる高導電性金属で形成されている。
【００３３】
（２）前記手段（１）の構成において、前記キャップは多層配線基板に設けた窪みにフックを介して着脱自在に取り付けられている。
【００３４】
前記（１）の手段によれば、（ａ）高周波パワーモジュールは、電界効果トランジスタ等の能動部品や受動部品を主面に搭載した多層配線基板と、この多層配線基板の主面側に固定されたキャップとによって形成された矩形体構造となっていることから、従来のようにパッケージからリードを突出させたり、取付用フィンを突出させないため小型となる。
【００３５】
（ｂ）前記多層配線基板はストリップライン構造にマイクロストリップライン構造を積み重ねた構造となるため、伝送線路（信号配線等）の長さを長くとっても、伝送線路は２段に設けられるため、多層配線基板の大きさは小さくでき、高周波パワーモジュールの小型化が達成できる。
【００３６】
（ｃ）誘電体層間に設けられた信号配線はその上下を誘電体層を介してグランド配線で挟まれる構造となることから、電気・電磁的シールドがなされ、高周波特性が安定する。
【００３７】
（ｄ）前記グランド配線は編み目構造となっていることから、編み目部分には誘電体層が入り込み、グランド配線の上下の誘電体層の接合強度が高くなり、剥がれ難い多層配線基板となる。したがって、耐湿性に優れた高周波パワーモジュールとなる。
【００３８】
（ｅ）前記能動部品において半導体チップは前記多層配線基板の主面に設けられた窪みに固定され、前記半導体チップの電極面と前記多層配線基板の配線面の高さは略同一高さとなり、前記半導体チップの電極と前記配線を接続する前記ワイヤは略直線状に延在している。したがって、ワイヤが短くなり、抵抗が軽減されて高周波特性が良好となる。例えば出力ゲインが大きくなる。
【００３９】
（ｆ）前記多層配線基板の所望部分には、所望の誘電体層から最下層の誘電体層まで貫通延在するサーマルビィアが設けられている。したがって、熱放散性が高くなり、安定した電気特性が得られる。
【００４０】
（ｇ）前記サーマルビィアの上には半導体チップが位置している。したがって、半導体チップで発熱した熱は速やかに外部に放散され、電界効果トランジスタが安定動作する。
【００４１】
（ｈ）前記多層配線基板の裏面の電極端子において、グランド電極端子はその表面が実装用接合材に濡れないレジスト膜で部分的に覆われて相互に独立した複数の電極端子となっている。したがって、各電極端子に均一に実装用接合材が濡れるため、各電極端子は確実に実装用接合材を介して実装基板に固定される。
【００４２】
（ｉ）前記多層配線基板の裏面の電極端子の配列間隔は同一ピッチとなっている。したがって、各電極端子は実装用接合材の片寄りもなく実装用接合材のブリッジ等の不良も発生しなくなる。また、実装のセルフアライン化も可能となる。
【００４３】
（ｊ）前記多層配線基板の裏面の電極端子のうち、少なくともグランド電極以外の電極端子は多層配線基板の側面の上下に延在する端面スルーホール端子を介して各層の配線に接続されている。すなわち、高周波パワーモジュールはＬＣＣ（リードレス・チップ・キャリア）構造となり、小型化が達成できる。
【００４４】
（ｋ）前記多層配線基板は低温焼成多層セラミック基板となることから、配線は融点の低い銀系金属（Ａｇ−Ｐｔ）からなる高導電性金属で形成できるため、抵抗の低減から高周波特性が良好となる。すなわち、出力ゲインの向上を図ることができる。
【００４５】
前記（２）の手段によれば、キャップは多層配線基板に設けた窪みにフックを介して着脱自在に取り付けられていることから、多層配線基板へのキャップの着脱が容易である。
【００４６】
【発明の実施の形態】
以下、図面を参照して本発明の実施の形態を詳細に説明する。
【００４７】
なお、発明の実施の形態を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。
【００４８】
図１乃至図９は本発明の一実施形態である高周波パワーモジュールに係わる図であり、図１は高周波パワーモジュールの外観を示す斜視図、図２は高周波パワーモジュールの断面図、図３はキャップを取り外した高周波パワーモジュールを示す平面図、図４は高周波パワーモジュールを構成する多層配線基板の構造を示す一部の斜視図、図５は前記多層配線基板の表面、すなわち上段誘電体層の露出面に形成される配線パターン（第１層配線）を示す平面図、図６は前記多層配線基板の上段誘電体層と中段誘電体層との間に形成される配線パターン（第２層配線）を示す平面図、図７は前記多層配線基板の中段誘電体層と下段誘電体層との間に形成される配線パターン（第３層配線）を示す平面図、図８は前記多層配線基板の裏面、すなわち下段誘電体層の露出面に形成される配線パターン（第４層配線）を示す底面図、図９は前記多層配線基板におけるグランド配線となる第２層配線および第４層配線の一部を示す平面図である。
【００４９】
本実施形態の混成集積回路装置（高周波パワーモジュール）１は、図１に示すように、板状の多層配線基板２と、この多層配線基板２の主面（上面）に被せるように半田３（例えば、Ｐｂ／Ｓｎ＝９５／５の高温半田）を介して固定されたキャップ４とからなり、外観的には、偏平な矩形体となっている。高周波パワーモジュール１は、例えば、幅８ｍｍ，長さ１２．３ｍｍ，高さ２．５ｍｍとなり、従来のＥ型の高周波パワーモジュールの幅２２ｍｍ，奥行き１２ｍｍ，高さ３．７ｍｍに比較して大幅に小型となる。
【００５０】
また、図８の多層配線基板２の底面図に示すように、前記多層配線基板２の裏面には、複数の電極端子（外部端子）５が設けられている。電極端子５は多層配線基板２の両側にそれぞれ設けられ、多層配線基板２の長手方向に沿って一定ピッチで並び、一側（図中上側）では左から右に向かって入力端子（Ｐｉｎ）６，グランド端子（ＧＮＤ）７，グランド端子（ＧＮＤ）８，ゲインコントロール端子（Ｖａｐｃ ）９となる。また、他側（図中下側）では左から右に向かって出力端子（Ｐｏｕｔ ）１０，グランド端子（ＧＮＤ）１１，グランド端子（ＧＮＤ）１２，電源端子（Ｖｄｄ）１３となる。
【００５１】
前記入力端子６，ゲインコントロール端子９，出力端子１０，電源端子１３に対応する多層配線基板２の側面には、多層配線基板２の表面から裏面に至る部分に端面スルーホールが設けられている。これは、高周波パワーモジュール１を実装基板に実装する際、各電極端子が多層配線基板２の裏面の電極部分と側面の端面スルーホール２０部分で接続されて実装されることになり、確実な実装が行える。
【００５２】
以上のことから、本実施形態の高周波パワーモジュール１は、混成集積回路装置ではあるが、単体の半導体チップをパッケージ内に組み込んだＬＣＣ構造となり、製品の小型化が達成できる。
【００５３】
一方、図８において４つのグランド端子（ＧＮＤ）７，８，１１，１２を区画するように延在するハッチング部分は、高周波パワーモジュール１を実装基板に実装する際使用される実装用接合材に濡れない材料で形成されたレジスト膜１４である。例えば、高周波パワーモジュール１は半田によって実装基板に実装されることから、前記レジスト膜１４は厚さ２０μｍ前後のソルダーレジスト膜となる。
【００５４】
前記レジスト膜１４はグランド配線を覆うように設けられている。したがって、多層配線基板２の裏面には、前記４つのグランド端子（ＧＮＤ）７，８，１１，１２が延在する領域と、レジスト膜１４とによって覆われる領域に亘って一体となるグランド（ＧＮＤ）配線１５が延在することになる。これは、後述するが、信号配線および電源配線等を上下で誘電体層を介してグランド配線で挟む所謂ストリップライン構造とし、電気・電磁的なシールドを行うためである。
【００５５】
また、前記一体のグランド配線１５をレジスト膜１４で部分的に覆い、独立した複数のグランド端子７，８，１１，１２とすることは、各電極端子の面積差を余り大きくしないことにある。すなわち、高周波パワーモジュール１を半田実装した場合、各電極端子の面積差が極端に大きいと、半田の表面張力によって広い面積部分での高周波パワーモジュール１の浮き上がり高さが大きくなり、四方に設けられた小面積部分では、一部で接合不良が発生するおそれがある。そこで、本実施形態では、各電極端子の面積比率は最大でも２倍程度としてある。
【００５６】
また、一列に並ぶ電極端子において各電極端子を等しいピッチで配列することによって、セルフアライメントを促進する。また、半田ブリッジ等の実装不良も防止できる。
【００５７】
また、図８において示す小丸は、高周波パワーモジュール１内で発生した熱を外部に伝達するサーマルビィア１６であり、同図では一部のみを示してある。サーマルビィア１６は、サーマルビィアホールに熱伝導性の良好な金属を充填した構造となっている。サーマルビィア１６は、例えば発熱量の大きい能動部品である半導体チップの下部に設けられている。
【００５８】
高周波パワーモジュール１を構成するキャップ４は、例えば金属板を成形して周壁を形成した構造となり、両端の端面壁２１で多層配線基板２の両端を覆い、両側の側壁２２から突出する接続片２３で多層配線基板２の側面と重なり、半田３を介して多層配線基板２に固定されている。また、側壁２２の一部は開口されている。キャップ４は厚さ０．１ｍｍとなり、例えばメッキレスの洋白、あるいはニッケルメッキを施したリン青銅で形成されている。
【００５９】
多層配線基板２は、図２および図４に示すように、上段誘電体層（上段誘電体板）２５，中段誘電体層（中段誘電体板）２６，下段誘電体層（下段誘電体板）２７と誘電体層（誘電体板）を３段に重ねた構造となっている。
【００６０】
また、上段誘電体層２５の上面（露出面）には、図５に示すような配線パターン（第１層配線３０）が設けられている。また、前記上段誘電体層２５と中段誘電体層２６との間には図６に示すような配線パターン（第２層配線３１）が設けられ、前記中段誘電体層２６と下段誘電体層２７との間には図７に示すような配線パターン（第３層配線３２）が設けられ、下段誘電体層２７の裏面（露出面）には図８に示すような配線パターン（第４層配線３３）が設けられている。
【００６１】
多層配線基板２は、例えば、ガラスセラミックスを積層させた低温焼成多層配線基板からなり、配線は高導電性金属、例えば銀系金属を使用している。すなわち、外層配線はＡｇ−Ｐｔを使用し、内装配線はＡｇを使用している。低温焼成は６００℃程度となり、融点の低いＡｇの使用が可能となる。Ａｇは抵抗値が低い高導電性金属となるため、高周波特性の向上が達成できる。
【００６２】
図５乃至図８において、３５は信号配線、３６は電源配線、１５はグランド配線である。これにより、中段誘電体層２６と下段誘電体層２７との間の第３層配線３２は、中段誘電体層２６上の第２層配線３１と下段誘電体層２７の下の第４層配線３３がいずれもグランド配線１５となることから、ストリップライン構造となる。また、上段誘電体層２５上の第１層配線３０は上段誘電体層２５の下面にグランド配線１５となる第２層配線３１が設けられていることから、マイクロストリップライン構造となる。
【００６３】
内層の信号配線は上下を誘電体層を介して挟まれることから、電気・電磁的シールドが可能となり、高周波特性が安定する。
【００６４】
また、上段誘電体層２５と中段誘電体層２６との間のグランド配線１５は、図９に示すように、編み目（メッシュ）構造となっている。このため、編み目部分５５には、上段誘電体層２５と中段誘電体層２６の誘電体層が入り込み、グランド配線の上下の誘電体層の接合強度が高くなり、剥がれ難い多層配線基板２となる。
【００６５】
前記第１層配線３０，第２層配線３１，第３層配線３２，第４層配線３３の各配線は１０〜２０μｍ程度の厚さとなっている。そして、多層配線基板２全体の厚さは、例えば０．９ｍｍとなる。
【００６６】
一方、第１層配線３０，第２層配線３１，第３層配線３２，第４層配線３３の各配線は、図２および図４に示すように、所望の誘電体層から所望の深さの誘電体層まで貫通延在するブラインド型ビィア４０や最上段の誘電体層から最下段の誘電体層まで貫通延在する貫通型ビィア４１、さらには所望の誘電体層から最下段の誘電体層まで貫通延在するサーマルビィア１６によって電気的に接続されている。これらブラインド型ビィア４０，貫通型ビィア４１およびサーマルビィア１６はビィアホールにＡｇを充填させた構造となっている。
【００６７】
また、３枚の重なる上段誘電体層２５，中段誘電体層２６，下段誘電体層２７の両側面にも、半円弧断面の端面スルーホール２０が設けられ、下段誘電体層２７の第４層配線３３で形成される各外部端子５（入力端子６、グランド端子７，８１１，１２、ゲインコントロール端子９、出力端子１０、電源端子１３）に接続されている。
【００６８】
前記上段誘電体層２５には、図２乃至図５に示すように、矩形の窪み４２，４３が設けられ、これら窪み４２，４３の底には半導体チップ４４，４５が固定されている。窪み４２，４３によって、半導体チップ４４，４５の図示しない上面の電極面と、配線面の高さは略同じ高さとなる。このため、半導体チップ４４，４５の電極と配線とを接続する導電性のワイヤ４６はその張り高さ（ループ）を低く形成できるため、短い長さで配線と半導体チップの電極を接続できることになり、抵抗の低減から高周波特性の向上が達成できる。例えば出力ゲインの向上を達成することができる。
【００６９】
前記半導体チップ４５は、図２および図４に示すように、グランド配線１５となる第２層配線３１に銀ペースト等の接合材４７を使用して固定される。また、半導体チップ４４，４５が固定される部分には、多数のサーマルビィア１６が設けられ、半導体チップ４４，４５から発生する熱を速やかに外部に伝達するようになっている。熱は、多層配線基板２の裏面のグランド配線１５およびレジスト膜１４を介して実装基板に放熱される。したがって、半導体チップ４４，４５は安定した動作を行う。
【００７０】
多層配線基板２の表面には、図２乃至図４に示すように、能動部品としてツェナーダイオード（ＺＤ）５０が搭載されている。また、受動部品としてはチップ型の抵抗（Ｒ１ 〜Ｒ６ ）５１、チップ型のコンデンサ（Ｃ１ 〜Ｃ９ ）５２，コンデンサ（バイパスコンデンサ）５３が搭載されている。
【００７１】
また、図２および図３に示すように、半導体チップ４４，４５、ワイヤ４６、一部の抵抗５１，コンデンサ５２，コンデンサ５３等は、耐湿性向上のためにレジン５４によって被覆されている。
【００７２】
なお、本実施形態では内層の配線は修正できない。このため、線路特性を測定した後、線路特性に合った各部品（抵抗，コンデンサ等）を選択して組み込むことによって所望の電気特性を得ることができる。
【００７３】
本実施形態では、電界効果トランジスタを２段に組み込んで、８００〜１０００ＭＨｚとなる携帯電話用の高周波パワーモジュールとなる。
【００７４】
本実施形態の高周波パワーモジュールは以下の効果を有する。
【００７５】
（１）高周波パワーモジュールは、電界効果トランジスタ等の能動部品や受動部品を主面に搭載した多層配線基板２と、この多層配線基板２の主面側に固定されたキャップ４とによって形成された矩形体構造となっていることから、従来のようにパッケージからリードを突出させたり、取付用フィンを突出させないため小型となる。特に長くリードを突出させないため、実装面積の大幅な縮小が達成できる。実装の場合、Ｅ型の場合、実装面積は２０ｍｍ×１４．３５ｍｍとなるが、本実施形態の場合は１２．３ｍｍ×８ｍｍと大幅に小さくなる。
【００７６】
（２）多層配線基板２はストリップライン構造にマイクロストリップライン構造を積み重ねた構造となるため、伝送線路（信号配線等）の長さを長くとっても、伝送線路は２段に設けられるため、多層配線基板の大きさは小さくでき、高周波パワーモジュールの小型化が達成できる。
【００７７】
（３）誘電体層間に設けられた信号配線はその上下を誘電体層を介してグランド配線で挟まれる構造となることから、電気・電磁的シールドがなされ、高周波特性が安定する。
【００７８】
（４）内層のグランド配線は編み目構造となっていることから、編み目部分には誘電体層が入り込み、グランド配線の上下の誘電体層の接合強度が高くなり、剥がれ難い多層配線基板となる。したがって、耐湿性に優れた高周波パワーモジュールとなる。
【００７９】
（５）能動部品において、半導体チップ４４，４５は多層配線基板２の主面に設けられた窪み４２，４３に固定され、半導体チップの電極面と多層配線基板の配線面の高さは略同一高さとなり、前記半導体チップの電極と前記配線を接続する前記ワイヤ４６は略直線状に延在している。したがって、ワイヤが短くなり、抵抗が軽減されて高周波特性が良好となる。例えば出力ゲインが大きくなる。
【００８０】
（６）多層配線基板２の所望部分には、所望の誘電体層から最下層の誘電体層まで貫通延在するサーマルビィア１６が設けられている。したがって、熱放散性が高くなり、安定した電気特性が得られる。
【００８１】
（７）サーマルビィア１６の上には半導体チップ４４，４５が位置している。したがって、半導体チップ４４，４５で発熱した熱は速やかに外部に放散され、電界効果トランジスタが安定動作する。
【００８２】
（８）多層配線基板２裏面の電極端子５において、グランド配線１５はその表面が実装用接合材に濡れないレジスト膜１４で部分的に覆われて相互に独立した複数のグランド端子７，８，１１，１２となっている。したがって、各電極端子５に均一に実装用接合材が濡れるため、各電極端子５は確実に実装用接合材を介して実装基板に固定される。
【００８３】
（９）多層配線基板２の裏面の電極端子５の配列間隔は同一ピッチとなっている。したがって、各電極端子５は実装用接合材の片寄りもなく実装用接合材のブリッジ等の不良も発生しなくなる。また、実装のセルフアライン化も可能となる。
【００８４】
（１０）多層配線基板２の裏面の電極端子５のうち、少なくともグランド端子７，８，１１，１２以外の電極端子は、多層配線基板２の側面の上下に延在する端面スルーホール２０を介して各層の配線に接続されている。すなわち、高周波パワーモジュールはＬＣＣ（リードレス・チップ・キャリア）構造となり、小型化が達成できる。
【００８５】
（１１）多層配線基板２は低温焼成多層セラミック基板となることから、配線は融点の低い銀系金属（Ａｇ−Ｐｔ）からなる高導電性金属で形成できるため、抵抗の低減から高周波特性が良好となる。すなわち、出力ゲインの向上を図ることができる。
【００８６】
以上本発明者によってなされた発明を実施形態に基づき具体的に説明したが、本発明は上記実施形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない、たとえば、図１０に示すように、キャップ４は、多層配線基板２に設けた窪み６０の縁にフック６１を介して着脱自在に取り付ける構造とすれば、多層配線基板２へのキャップ４の着脱が容易となる。
【００８７】
また、前記実施形態では、多層配線基板２は多層配線構造となっていることから、誘電体層の厚さをさらに薄くでき、容量の増大を図ることができる。また、多層配線基板２となることから、信号配線の長さもさらに長くできるため、特性インピーダンスの増大を図ることも可能である。この場合、酸化チタンやチタン酸バリウム等誘電率の高い材料を誘電体層（誘電体板）として使用すれば、容量の増大はさらに高くなる。
【００８８】
また、前記多層配線基板２は、ガラスセラミック以外の配線基板材料を用いて形成できる。
【００８９】
また、低温焼成多層配線基板の場合、高導電性金属による配線としては、金や銅を使用できる。
【００９０】
以上の説明では主として本発明者によってなされた発明をその背景となった利用分野である高周波パワーモジュールに適用した場合について説明したが、それに限定されるものではない。本発明は少なくとも混成集積回路装置には適用できる。
【００９１】
【発明の効果】
本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。
【００９２】
（１）高周波パワーモジュールは、ＬＣＣ構造となるため小型となる。また、配線基板は多層配線基板となるため、信号配線は各段に形成できるため所定の長さを得ることができ、配線基板の大きさも小さくでき、パッケージの大きさを小さくできる。これらによって高周波パワーモジュールの小型化，実装面積の縮小化が達成できる。
【００９３】
（２）高周波パワーモジュールは低温焼成多層配線基板を使用するため、高導電性金属で配線を形成できること、内層の信号配線はストリップライン構造となることから電気・電磁的にシールドされること、半導体チップで発生した熱はサーマルビィアによって速やかにパッケージ外に放熱されること等によって高周波特性の向上が達成できる。
【００９４】
（３）多層配線基板の裏面に電極端子を設けるとともに、多層配線基板をキャップで覆うことによって高周波パワーモジュールを形成していることから、部品点数が少なくなり、組立工数の低減，材料費の低減から製造コストの低減が達成できる。
【図面の簡単な説明】
【図１】本発明の一実施形態である高周波パワーモジュールの外観を示す斜視図である。
【図２】本実施形態の高周波パワーモジュールの断面図である。
【図３】本実施形態のキャップを取り外した高周波パワーモジュールを示す平面図である。
【図４】本実施形態の高周波パワーモジュールにおける多層配線基板の構造を示す一部の斜視図である。
【図５】本実施形態の高周波パワーモジュールにおける多層配線基板の表面、すなわち上段誘電体層の露出面に形成される配線パターン（第１層配線）を示す平面図である。
【図６】本実施形態の高周波パワーモジュールにおける多層配線基板の上段誘電体層と中段誘電体層との間に形成される配線パターン（第２層配線）を示す平面図である。
【図７】本実施形態の高周波パワーモジュールにおける多層配線基板の中段誘電体層と下段誘電体層との間に形成される配線パターン（第３層配線）を示す平面図である。
【図８】本実施形態の高周波パワーモジュールにおける多層配線基板の裏面、すなわち下段誘電体層の露出面に形成される配線パターン（第４層配線）を示す底面図である。
【図９】本実施形態の高周波パワーモジュールにおけるグランド配線となる第２層配線および第４層配線の一部を示す平面図である。
【図１０】本発明の他の実施形態である高周波パワーモジュールを示す断面図である。
【符号の説明】
１…混成集積回路装置（高周波パワーモジュール）、２…多層配線基板、３…半田、４…キャップ、５…電極端子（外部端子）、６…入力端子（Ｐｉｎ）、７…グランド端子（ＧＮＤ）、８…グランド端子（ＧＮＤ）、９…ゲインコントロール端子（Ｖａｐｃ ）、１０…出力端子（Ｐｏｕｔ ）、１１，１２…グランド端子（ＧＮＤ）、１３…電源端子（Ｖｄｄ）、１４…レジスト膜、１５…グランド配線、１６…サーマルビィア、２０…端面スルーホール、２１…端面壁、２２…側壁、２３…接続片、２５…上段誘電体層、２６…中段誘電体層、２７…下段誘電体層、３０…第１層配線、３１…第２層配線、３２…第３層配線、３３…第４層配線、３５…信号配線、３６…電源配線、４０…ブラインド型ビィア、４１…貫通型ビィア、４２，４３…窪み、４４，４５…半導体チップ、４６…ワイヤ、４７…接合材、５０…ツェナーダイオード、５１…抵抗、５２…コンデンサ、５３…コンデンサ、５４…レジン。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a hybrid integrated circuit device using a low-temperature fired multilayer wiring board, and more particularly to a technique which is effective when applied to a small high-frequency power amplifier (high-frequency power module: RF power module) used for a transmission unit of a cellular telephone or the like.
[0002]
[Prior art]
2. Description of the Related Art An RF power module used in a wireless communication section of a mobile communication device such as a mobile phone or a mobile phone has a package formed by a metal flange and a cap. In addition, electrode terminals such as signal terminals protrude from one side surface of the package, and mounting fins also serving as ground electrodes protrude from lower portions of both ends of the package.
[0003]
In the package, the flange has conductors on both sides. Distribution The wire substrate is fixed. This wiring board has a so-called microstrip line structure in which a circuit pattern is provided on the front surface of a dielectric substrate and a ground (GND) pattern is provided on the back surface. The wiring board is partially provided with a hole. A heat sink having good thermal conductivity is fixed to the flange at the bottom of the hole. A semiconductor chip made of a field effect transistor is fixed to the heat sink.
[0004]
The high-frequency power module (MOS / power module for high-frequency power amplification) is described in "Hitachi Hyoron," issued by Hitachi Hyoron Co., Ltd., No. 4, 1993, April 25, pp. 12-26. The document discloses an E-type high-frequency power module having a width of 22 mm, a depth of 12 mm, and a height of 3.7 mm.
[0005]
[Problems to be solved by the invention]
Conventional high-frequency power modules are roughly classified into a metal flange (header), a wiring board fixed on the flange, and a heat sink fixed to the flange using holes provided in the wiring board. It comprises a semiconductor chip to be fixed, a cap fixed to the flange to cover the wiring board, and an electrode terminal (lead) fixed to the wiring board and having a tip protruding out of the cap. Both ends of the flange partially protrude outside the cap to form mounting fins that also serve as ground electrodes.
[0006]
Electronic components such as capacitors, resistors and zener diodes are mounted on the surface of the wiring board. Further, the wiring on the surface of the wiring board and the electrode of the semiconductor chip are connected by a conductive wire.
[0007]
As a result of studying the miniaturization, high performance, and low cost of the conventional high-frequency power module, it was found that the following matters hindered miniaturization, high functionality, low cost, and the like.
[0008]
(1) The wiring board has a microstrip line structure in which circuit patterns such as signal wiring and power supply wiring are provided on the front surface of a dielectric substrate, and a ground (GND) pattern is provided on the back surface. This is for adjusting the characteristics by trimming the resistance or adjusting the line width after the wiring board is manufactured. However, in the microstrip line structure in which the signal wiring is formed on one surface of the dielectric substrate, the wiring length of the signal wiring is long in order to obtain desired electrical characteristics. This increases the size of the package, which hinders miniaturization of the high-frequency power module.
[0009]
(2) Since the wiring board is fixed on the flange and further covered with the cap, the height of the package is increased, and miniaturization of the high-frequency power module is hindered.
[0010]
(3) Since a part of both ends of the flange protrudes outside the cap to form a mounting fin that also serves as a ground electrode, the size of the high-frequency power module increases. Therefore, the mounting area also increases.
[0011]
(4) Since the leads protrude long from one side of the package (cap), the high-frequency power module becomes large. Therefore, the mounting area also increases.
[0012]
(5) Since the height of the surface of the semiconductor chip is different from the height of the wiring surface of the wiring board, the wire connecting the electrode of the semiconductor chip and the wiring becomes longer. Further, since the semiconductor chip is fixed on the heat sink fixed to the flange at the bottom of the hole provided in the wiring board, the distance between the electrode of the semiconductor chip and the wiring becomes longer, and the wire becomes longer. The longer the wire, the higher the resistance and the lower the high frequency characteristics. For example, the output gain decreases.
[0013]
(6) Since the wiring substrate is formed of a dielectric substrate, it is not possible to directly mount a semiconductor chip generating a large amount of heat on the wiring substrate. Therefore, a hole is formed in the wiring substrate, and a metal flange at the bottom of the hole is provided. Since a heat sink having good heat conductivity is fixed to the heat sink and the semiconductor chip is fixed to the heat sink, the cost of the high-frequency power module is increased due to an increase in the number of components and an increase in the number of assembly steps.
[0014]
(7) Since the support member, the heat radiation member, and the flange serving also as the ground electrode are fixed to the wiring board, the number of components is increased.
[0015]
(8) For mounting the high-frequency power module, a part of the flange is formed to form the mounting fins. However, the mounting surface height of each mounting fin tends to vary due to the molding, and the mounting reliability is increased. May be impaired.
[0016]
An object of the present invention is to provide a small-sized hybrid integrated circuit device capable of reducing a mounting area.
[0017]
It is another object of the present invention to provide a high-performance hybrid integrated circuit device.
[0018]
Another object of the present invention is to provide a hybrid integrated circuit device that can achieve a reduction in manufacturing cost.
[0019]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0020]
[Means for Solving the Problems]
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows.
[0021]
(1) The hybrid integrated circuit device has the following structure.
[0022]
(A) a multilayer wiring board, at least one or more active components and passive components mounted on a main surface of the multilayer wiring board, and a conductive property for connecting an electrode of the active component and a wiring of the multilayer wiring board. The multilayer wiring board includes a wire, a cap fixed to the multilayer wiring board so as to cover a main surface of the multilayer wiring board, and a plurality of electrode terminals of the multilayer wiring provided on a back surface of the multilayer wiring board.
[0023]
(B) On the multilayer wiring board, semiconductor chips constituting field effect transistors are connected and arranged in multiple stages to constitute a high-frequency power module.
[0024]
(C) The multilayer wiring board has a structure in which dielectric layers are stacked in multiple stages with wirings interposed therebetween, and the signal wiring provided between the dielectric layers is sandwiched above and below ground wiring via the dielectric layer. Strip line structure. The upper part of the multilayer wiring board has a microstrip line structure.
[0025]
(D) The ground wiring has a stitch structure.
[0026]
(E) In the active component, a semiconductor chip is fixed to a depression provided on a main surface of the multilayer wiring board, and an electrode surface of the semiconductor chip and a wiring surface of the multilayer wiring board have substantially the same height; The wire connecting the electrode of the semiconductor chip and the wiring extends substantially linearly.
[0027]
(F) A thermal via is provided at a desired portion of the multilayer wiring board so as to extend from a desired dielectric layer to a lowermost dielectric layer.
[0028]
(G) A semiconductor chip is located on the thermal via.
[0029]
(H) Among the electrode terminals on the rear surface of the multilayer wiring board, the ground electrode terminals are partially covered with a resist film which does not wet the bonding material for mounting, and are a plurality of electrode terminals independent of each other.
[0030]
(I) The arrangement intervals of the electrode terminals on the back surface of the multilayer wiring board are the same.
[0031]
(J) Among the electrode terminals on the back surface of the multilayer wiring board, at least the electrode terminals other than the ground electrode are connected to the wiring of each layer via end face through-hole terminals extending vertically on the side surface of the multilayer wiring board.
[0032]
(K) The multilayer wiring substrate is a low-temperature fired multilayer ceramic substrate, and the wiring is formed of a highly conductive metal made of a silver-based metal.
[0033]
(2) In the configuration of the means (1), the cap is removably attached to a recess provided in the multilayer wiring board via a hook.
[0034]
According to the means (1), (a) the high-frequency power module is a multilayer wiring board having active components and passive components such as a field effect transistor mounted on a main surface thereof, and is fixed to the main surface side of the multilayer wiring substrate. Since the rectangular structure is formed by the cap and the cap, the lead is not protruded from the package and the mounting fin is not protruded as in the related art, so that the size is reduced.
[0035]
(B) Since the multilayer wiring board has a structure in which a microstrip line structure is stacked on a strip line structure, even if the length of a transmission line (such as a signal wiring) is increased, the transmission line is provided in two stages. The size of the substrate can be reduced, and downsizing of the high-frequency power module can be achieved.
[0036]
(C) Since the signal wiring provided between the dielectric layers has a structure in which the signal wiring is sandwiched above and below by the ground wiring via the dielectric layer, an electric / electromagnetic shield is provided and the high-frequency characteristics are stabilized.
[0037]
(D) Since the ground wiring has a stitch structure, a dielectric layer enters the stitch portion, the bonding strength between the dielectric layers above and below the ground wiring is increased, and the multilayer wiring board is hard to peel. Therefore, a high-frequency power module having excellent moisture resistance is obtained.
[0038]
(E) In the active component, a semiconductor chip is fixed to a depression provided on a main surface of the multilayer wiring board, and an electrode surface of the semiconductor chip and a wiring surface of the multilayer wiring board have substantially the same height; The wire connecting the electrode of the semiconductor chip and the wiring extends substantially linearly. Therefore, the wire is shortened, the resistance is reduced, and the high-frequency characteristics are improved. For example, the output gain increases.
[0039]
(F) A thermal via is provided at a desired portion of the multilayer wiring board so as to extend from a desired dielectric layer to a lowermost dielectric layer. Therefore, heat dissipation is enhanced, and stable electric characteristics can be obtained.
[0040]
(G) A semiconductor chip is located on the thermal via. Therefore, the heat generated by the semiconductor chip is quickly dissipated to the outside, and the field effect transistor operates stably.
[0041]
(H) Among the electrode terminals on the rear surface of the multilayer wiring board, the ground electrode terminals are partially covered with a resist film which does not wet the bonding material for mounting, and are a plurality of electrode terminals independent of each other. Accordingly, since the bonding material for mounting is uniformly wetted on each electrode terminal, each electrode terminal is securely fixed to the mounting board via the bonding material for mounting.
[0042]
(I) The arrangement intervals of the electrode terminals on the back surface of the multilayer wiring board are the same. Therefore, each electrode terminal does not have a bias of the bonding material for mounting, and does not generate a defect such as a bridge of the bonding material for mounting. In addition, self-alignment of mounting becomes possible.
[0043]
(J) Among the electrode terminals on the back surface of the multilayer wiring board, at least the electrode terminals other than the ground electrode are connected to the wiring of each layer via end face through-hole terminals extending vertically on the side surface of the multilayer wiring board. That is, the high-frequency power module has an LCC (leadless chip carrier) structure, and can be reduced in size.
[0044]
(K) Since the multilayer wiring board is a multilayer ceramic substrate fired at a low temperature, the wiring can be formed of a highly conductive metal made of a silver-based metal (Ag-Pt) having a low melting point, so that high-frequency characteristics are good due to reduction in resistance. It becomes. That is, the output gain can be improved.
[0045]
According to the means (2), since the cap is detachably attached to the recess provided in the multilayer wiring board via the hook, the cap can be easily attached to and detached from the multilayer wiring board.
[0046]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0047]
In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.
[0048]
1 to 9 are views related to a high-frequency power module according to an embodiment of the present invention. FIG. 1 is a perspective view showing an appearance of the high-frequency power module, FIG. 2 is a cross-sectional view of the high-frequency power module, and FIG. FIG. 4 is a partial perspective view showing the structure of a multilayer wiring board constituting the high-frequency power module, and FIG. 5 is a front view of the multilayer wiring board, that is, an exposure of an upper dielectric layer. FIG. 6 is a plan view showing a wiring pattern (first-layer wiring) formed on the surface. FIG. 6 is a wiring pattern (second-layer wiring) formed between the upper dielectric layer and the middle dielectric layer of the multilayer wiring board. FIG. 7 is a plan view showing a wiring pattern (third layer wiring) formed between a middle dielectric layer and a lower dielectric layer of the multilayer wiring board, and FIG. 8 is a plan view of the multilayer wiring board. The back side, ie FIG. 9 is a bottom view showing a wiring pattern (fourth layer wiring) formed on an exposed surface of the stepped dielectric layer, and FIG. 9 shows a part of a second layer wiring and a fourth layer wiring serving as a ground wiring in the multilayer wiring board. It is a top view.
[0049]
As shown in FIG. 1, a hybrid integrated circuit device (high-frequency power module) 1 of the present embodiment has a plate-shaped multilayer wiring board 2 and solders 3 ( For example, the cap 4 is fixed via Pb / Sn = 95/5 high-temperature solder) and has a flat rectangular shape in appearance. The high-frequency power module 1 has, for example, a width of 8 mm, a length of 12.3 mm, and a height of 2.5 mm, which is significantly larger than the conventional E-type high-frequency power module having a width of 22 mm, a depth of 12 mm, and a height of 3.7 mm. It becomes small.
[0050]
Further, as shown in the bottom view of the multilayer wiring board 2 in FIG. 8, a plurality of electrode terminals (external terminals) 5 are provided on the back surface of the multilayer wiring board 2. The electrode terminals 5 are provided on both sides of the multilayer wiring board 2, respectively, and are arranged at a constant pitch along the longitudinal direction of the multilayer wiring board 2. On one side (upper side in the figure), the input terminals (P in ) 6, ground terminal (GND) 7, ground terminal (GND) 8, gain control terminal (V apc ) 9. On the other side (lower side in the figure), the output terminals (P out ) 10, ground terminal (GND) 11, ground terminal (GND) 12, power supply terminal (V dd ) 13.
[0051]
On the side surface of the multilayer wiring board 2 corresponding to the input terminal 6, the gain control terminal 9, the output terminal 10, and the power supply terminal 13, an end face through hole is formed on a portion from the front surface to the back surface of the multilayer wiring substrate 2. Is Is provided. That is, when the high-frequency power module 1 is mounted on the mounting board, each electrode terminal is connected and mounted at the electrode portion on the back surface of the multilayer wiring board 2 and the through-hole 20 on the side surface of the multilayer wiring board 2, thereby ensuring reliable mounting. Can be performed.
[0052]
As described above, although the high-frequency power module 1 of the present embodiment is a hybrid integrated circuit device, the high-frequency power module 1 has an LCC structure in which a single semiconductor chip is incorporated in a package, and the product can be downsized.
[0053]
On the other hand, in FIG. 8, the hatched portions extending so as to partition the four ground terminals (GND) 7, 8, 11, and 12 are used as mounting bonding materials used when mounting the high-frequency power module 1 on a mounting board. The resist film 14 is formed of a non-wetting material. For example, since the high-frequency power module 1 is mounted on a mounting board by soldering, the resist film 14 is a solder resist film having a thickness of about 20 μm.
[0054]
The resist film 14 is provided so as to cover the ground wiring. Therefore, on the back surface of the multilayer wiring board 2, a ground (GND) integrated over a region where the four ground terminals (GND) 7, 8, 11, 12 extend and a region covered with the resist film 14. ) The wiring 15 extends. This is because, as will be described later, a so-called strip line structure in which signal wiring, power supply wiring, and the like are sandwiched between ground wirings via dielectric layers on the upper and lower sides to provide electric and electromagnetic shielding.
[0055]
The reason why the integral ground wiring 15 is partially covered with the resist film 14 to form a plurality of independent ground terminals 7, 8, 11, and 12 is that the area difference between the electrode terminals is not so large. That is, when the high-frequency power module 1 is mounted by soldering, if the area difference between the electrode terminals is extremely large, the floating height of the high-frequency power module 1 in a wide area is increased due to the surface tension of the solder, and the electrode terminals are provided on all sides. In the small area portion, there is a possibility that a joining failure occurs in a part. Therefore, in the present embodiment, the area ratio of each electrode terminal is set to about twice at the maximum.
[0056]
In addition, self-alignment is promoted by arranging the electrode terminals at an equal pitch in the electrode terminals arranged in a line. Further, it is possible to prevent a mounting failure such as a solder bridge.
[0057]
The small circles shown in FIG. 8 are thermal vias 16 for transmitting the heat generated in the high-frequency power module 1 to the outside, and only a part is shown in FIG. The thermal via 16 has a structure in which a thermal via hole is filled with a metal having good thermal conductivity. The thermal via 16 is provided, for example, below a semiconductor chip that is an active component that generates a large amount of heat.
[0058]
The cap 4 constituting the high-frequency power module 1 has a structure in which, for example, a metal plate is formed to form a peripheral wall, and both ends of the multilayer wiring board 2 are covered with end walls 21 on both ends, and connection pieces 23 projecting from the side walls 22 on both sides. , And is fixed to the multilayer wiring board 2 via the solder 3. Further, a part of the side wall 22 is opened. The cap 4 has a thickness of 0.1 mm and is made of, for example, plating-free nickel-white or nickel-plated phosphor bronze.
[0059]
As shown in FIGS. 2 and 4, the multilayer wiring board 2 includes an upper dielectric layer (upper dielectric plate) 25, a middle dielectric layer (middle dielectric plate) 26, and a lower dielectric layer (lower dielectric plate). 27 and a dielectric layer (dielectric plate) in three layers.
[0060]
On the upper surface (exposed surface) of the upper dielectric layer 25, a wiring pattern (first-layer wiring 30) as shown in FIG. 5 is provided. A wiring pattern (second-layer wiring 31) as shown in FIG. 6 is provided between the upper dielectric layer 25 and the middle dielectric layer 26. Is set A wiring pattern (third layer wiring 32) as shown in FIG. 7 is provided between the middle dielectric layer 26 and the lower dielectric layer 27, and the back surface (exposed surface) of the lower dielectric layer 27 is provided. Is provided with a wiring pattern (fourth layer wiring 33) as shown in FIG.
[0061]
The multilayer wiring board 2 is composed of, for example, a low-temperature fired multilayer wiring board in which glass ceramics are laminated, and the wiring uses a highly conductive metal, for example, a silver-based metal. That is, the outer wiring uses Ag-Pt, and the interior wiring uses Ag. The low temperature firing is about 600 ° C., which makes it possible to use Ag having a low melting point. Since Ag is a highly conductive metal having a low resistance value, improvement in high frequency characteristics can be achieved.
[0062]
5 to 8, 35 is a signal wiring, 36 is a power supply wiring, and 15 is a ground wiring. As a result, the third-layer wiring 32 between the middle dielectric layer 26 and the lower dielectric layer 27 becomes the second wiring 31 on the middle dielectric layer 26 and the fourth wiring below the lower dielectric layer 27. Since all 33 are ground wirings 15, they have a strip line structure. Further, the first layer wiring 30 on the upper dielectric layer 25 has a microstrip line structure because the second layer wiring 31 serving as the ground wiring 15 is provided on the lower surface of the upper dielectric layer 25.
[0063]
Since the signal wiring of the inner layer is sandwiched between the upper and lower layers via the dielectric layer, electric and electromagnetic shielding becomes possible, and the high frequency characteristics are stabilized.
[0064]
The ground wiring 15 between the upper dielectric layer 25 and the middle dielectric layer 26 has a stitch (mesh) structure as shown in FIG. For this reason, the dielectric layers of the upper dielectric layer 25 and the middle dielectric layer 26 enter the stitch portion 55, the bonding strength between the dielectric layers above and below the ground wiring is increased, and the multilayer wiring board 2 is difficult to peel. .
[0065]
Each of the first layer wiring 30, the second layer wiring 31, the third layer wiring 32, and the fourth layer wiring 33 has a thickness of about 10 to 20 μm. The overall thickness of the multilayer wiring board 2 is, for example, 0.9 mm.
[0066]
On the other hand, as shown in FIGS. 2 and 4, each of the first layer wiring 30, the second layer wiring 31, the third layer wiring 32, and the fourth layer wiring 33 has a desired depth from a desired dielectric layer. Blind via 40 extending from the uppermost dielectric layer to the lowermost dielectric layer, and a blind via 40 extending from the uppermost dielectric layer to the lowermost dielectric layer. They are electrically connected by thermal vias 16 extending through the layers. The blind via 40, the through via 41, and the thermal via 16 have a structure in which a via hole is filled with Ag.
[0067]
Also, on both side surfaces of the three upper dielectric layers 25, the middle dielectric layer 26, and the lower dielectric layer 27 which are overlapped with each other, the end surface through holes 20 having a semicircular cross section are provided, and the fourth layer of the lower dielectric layer 27 is formed. The external terminals 5 (the input terminal 6, the ground terminals 7, 811 and 12, the gain control terminal 9, the output terminal 10, and the power supply terminal 13) formed by the wiring 33 are connected.
[0068]
As shown in FIGS. 2 to 5, rectangular recesses 42 and 43 are provided in the upper dielectric layer 25, and semiconductor chips 44 and 45 are fixed to the bottoms of the recesses 42 and 43. Due to the depressions 42 and 43, the height of the electrode surface on the upper surface (not shown) of the semiconductor chips 44 and 45 is substantially the same as the height of the wiring surface. For this reason, since the conductive wire 46 connecting the electrodes of the semiconductor chips 44 and 45 and the wiring can be formed with a low tension (loop), the wiring and the electrode of the semiconductor chip can be connected with a short length. In addition, improvement in high-frequency characteristics can be achieved from reduction in resistance. For example, an improvement in output gain can be achieved.
[0069]
As shown in FIGS. 2 and 4, the semiconductor chip 45 is fixed to the second layer wiring 31 serving as the ground wiring 15 using a bonding material 47 such as a silver paste. Further, a large number of thermal vias 16 are provided in portions where the semiconductor chips 44 and 45 are fixed, so that heat generated from the semiconductor chips 44 and 45 is quickly transmitted to the outside. The heat is radiated to the mounting board via the ground wiring 15 and the resist film 14 on the back surface of the multilayer wiring board 2. Therefore, the semiconductor chips 44 and 45 perform a stable operation.
[0070]
As shown in FIGS. 2 to 4, a Zener diode (ZD) 50 is mounted on the surface of the multilayer wiring board 2 as an active component. In addition, chip-type resistors (R 1 ~ R 6 ) 51, chip type capacitor (C 1 ~ C 9 ) 52 and a capacitor (bypass capacitor) 53 are mounted.
[0071]
As shown in FIGS. 2 and 3, the semiconductor chips 44 and 45, the wires 46, and some of the resistors 51, the capacitors 52, and the capacitors 53 are covered with a resin 54 for improving moisture resistance.
[0072]
In this embodiment, the wiring in the inner layer cannot be corrected. For this reason, after measuring the line characteristics, the desired electrical characteristics can be obtained by selecting and incorporating components (resistance, capacitor, etc.) that match the line characteristics.
[0073]
In the present embodiment, a high-frequency power module for mobile phones of 800 to 1000 MHz is provided by incorporating field-effect transistors in two stages.
[0074]
The high-frequency power module according to the present embodiment has the following effects.
[0075]
(1) The high-frequency power module is formed by a multilayer wiring board 2 on which active components and passive components such as a field effect transistor are mounted on a main surface, and a cap 4 fixed to the main surface side of the multilayer wiring substrate 2. Because of the rectangular structure, the leads are not protruded from the package and the mounting fins are not protruded as in the related art, so that the size is reduced. Particularly, since the leads do not protrude for a long time, the mounting area can be significantly reduced. In the case of mounting, in the case of the E type, the mounting area is 20 mm × 14.35 mm, but in the case of the present embodiment, it is significantly reduced to 12.3 mm × 8 mm.
[0076]
(2) Multilayer wiring board 2 Is Since the microstrip line structure is stacked on the strip line structure, the transmission line is provided in two stages even if the length of the transmission line (such as signal wiring) is increased, so that the size of the multilayer wiring board can be reduced. The miniaturization of the high-frequency power module can be achieved.
[0077]
(3) Since the signal wiring provided between the dielectric layers has a structure in which the signal wiring is sandwiched above and below by the ground wiring via the dielectric layer, an electric / electromagnetic shield is performed, and the high-frequency characteristics are stabilized.
[0078]
(4) Since the ground wiring in the inner layer has a stitch structure, the dielectric layer enters the stitch portion, the bonding strength between the dielectric layers above and below the ground wiring is increased, and the multilayer wiring board is hard to peel off. Therefore, a high-frequency power module having excellent moisture resistance is obtained.
[0079]
(5) In the active component, the semiconductor chips 44 and 45 are fixed to the depressions 42 and 43 provided on the main surface of the multilayer wiring board 2, and the heights of the electrode surface of the semiconductor chip and the wiring surface of the multilayer wiring board are substantially the same. The height of the wire 46 connects the electrode of the semiconductor chip and the wiring, and the wire 46 extends substantially linearly. Therefore, the wire is shortened, the resistance is reduced, and the high-frequency characteristics are improved. For example, the output gain increases.
[0080]
(6) A thermal via 16 is provided at a desired portion of the multilayer wiring board 2 so as to extend from a desired dielectric layer to a lowermost dielectric layer. Therefore, heat dissipation is enhanced, and stable electric characteristics can be obtained.
[0081]
(7) The semiconductor chips 44 and 45 are located on the thermal via 16. Therefore, the heat generated by the semiconductor chips 44 and 45 is quickly dissipated to the outside, and the field effect transistor operates stably.
[0082]
(8) In the electrode terminals 5 on the back surface of the multilayer wiring board 2, the ground wiring 15 is partially covered with a resist film 14 that does not wet the mounting bonding material, and a plurality of mutually independent ground terminals 7, 8,. 11 and 12. Therefore, since the mounting bonding material is uniformly wetted on each electrode terminal 5, each electrode terminal 5 is securely fixed to the mounting board via the mounting bonding material.
[0083]
(9) The arrangement intervals of the electrode terminals 5 on the back surface of the multilayer wiring board 2 are the same. Therefore, each electrode terminal 5 does not have a bias of the bonding material for mounting, and a defect such as a bridge of the bonding material for mounting does not occur. In addition, self-alignment of mounting becomes possible.
[0084]
(10) Of the electrode terminals 5 on the rear surface of the multilayer wiring board 2, at least the electrode terminals other than the ground terminals 7, 8, 11, and 12 are provided through end face through holes 20 extending vertically on the side surface of the multilayer wiring board 2. To the wiring of each layer. That is, the high-frequency power module has an LCC (leadless chip carrier) structure, and can be reduced in size.
[0085]
(11) Since the multilayer wiring board 2 is a multilayer ceramic substrate fired at a low temperature, the wiring can be formed of a highly conductive metal made of a silver-based metal (Ag-Pt) having a low melting point. It becomes. That is, the output gain can be improved.
[0086]
Although the invention made by the inventor has been specifically described based on the embodiment, the present invention is not limited to the above embodiment, and various changes can be made without departing from the gist of the invention. For example, as shown in FIG. 10, if the cap 4 is configured to be detachably attached to the edge of the recess 60 provided in the multilayer wiring board 2 via the hook 61, the cap 4 Can be easily attached and detached.
[0087]
In the above embodiment, since the multilayer wiring board 2 has a multilayer wiring structure, the thickness of the dielectric layer can be further reduced, and the capacitance can be increased. In addition, since the multilayer wiring board 2 is used, the length of the signal wiring can be further increased, so that the characteristic impedance can be increased. In this case, if a material having a high dielectric constant, such as titanium oxide or barium titanate, is used as the dielectric layer (dielectric plate), the increase in capacitance is further increased.
[0088]
Further, the multilayer wiring board 2 can be formed using a wiring board material other than glass ceramic.
[0089]
In the case of a low-temperature fired multilayer wiring board, gold or copper can be used as the wiring made of a highly conductive metal.
[0090]
In the above description, the case where the invention made by the inventor is mainly applied to the high frequency power module which is the application field as the background has been described, but the invention is not limited to this. The present invention is applicable to at least a hybrid integrated circuit device.
[0091]
【The invention's effect】
The effects obtained by the typical inventions among the inventions disclosed in the present application will be briefly described as follows.
[0092]
(1) Since the high-frequency power module has an LCC structure, the size is small. Further, since the wiring board is a multilayer wiring board, the signal wiring can be formed in each stage, so that a predetermined length can be obtained, the size of the wiring board can be reduced, and the size of the package can be reduced. With these, the miniaturization and mounting area of the high-frequency power module can be reduced.
[0093]
(2) Since the high-frequency power module uses a low-temperature fired multilayer wiring board, it can be formed of a highly conductive metal, and the signal wiring in the inner layer has a stripline structure, so that it is electrically and electromagnetically shielded. The heat generated in the chip is quickly radiated to the outside of the package by the thermal via, thereby improving the high frequency characteristics.
[0094]
(3) By providing electrode terminals on the back surface of the multilayer wiring board and covering the multilayer wiring board with a cap, What Since the high-frequency power module is formed, the number of parts is reduced, the number of assembly steps is reduced, and the material cost is reduced, so that the manufacturing cost can be reduced.
[Brief description of the drawings]
FIG. 1 is a perspective view showing an appearance of a high-frequency power module according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of the high-frequency power module according to the embodiment.
FIG. 3 is a plan view showing the high-frequency power module with the cap of the embodiment removed.
FIG. 4 is a partial perspective view illustrating a structure of a multilayer wiring board in the high-frequency power module according to the embodiment.
FIG. 5 is a plan view showing a wiring pattern (first-layer wiring) formed on the surface of the multilayer wiring board in the high-frequency power module of the present embodiment, that is, on the exposed surface of the upper dielectric layer.
FIG. 6 is a plan view showing a wiring pattern (second-layer wiring) formed between the upper dielectric layer and the middle dielectric layer of the multilayer wiring board in the high-frequency power module of the present embodiment.
FIG. 7 is a plan view showing a wiring pattern (third-layer wiring) formed between the middle dielectric layer and the lower dielectric layer of the multilayer wiring board in the high-frequency power module of the present embodiment.
FIG. 8 is a bottom view showing a wiring pattern (fourth layer wiring) formed on the back surface of the multilayer wiring board in the high-frequency power module of the present embodiment, that is, on the exposed surface of the lower dielectric layer.
FIG. 9 is a plan view showing a part of a second-layer wiring and a fourth-layer wiring serving as ground wiring in the high-frequency power module of the present embodiment.
FIG. 10 is a sectional view showing a high-frequency power module according to another embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Hybrid integrated circuit device (high frequency power module), 2 ... Multilayer wiring board, 3 ... Solder, 4 ... Cap, 5 ... Electrode terminal (external terminal), 6 ... Input terminal (P in ), 7: ground terminal (GND), 8: ground terminal (GND), 9: gain control terminal (V apc ), 10 ... output terminal (P out ), 11, 12: ground terminal (GND), 13: power supply terminal (V dd ), 14 ... resist film, 15 ... ground wiring, 16 ... thermal via, 20 ... end face through hole, 21 ... end face wall, 22 ... side wall, 23 ... connection piece, 25 ... upper dielectric layer, 26 ... middle dielectric layer 27 lower layer dielectric layer 30 first layer wiring 31 second layer wiring 32 third layer wiring 33 fourth layer wiring 35 signal wiring 36 power wiring 40 blind type Vias, 41: through-type vias, 42, 43: recess, 44, 45: semiconductor chip, 46: wire, 47: bonding material, 50: zener diode, 51: resistor, 52: capacitor, 53: capacitor, 54: resin .

Claims (8)

サーマルビィアが形成された多層配線基板と、
前記多層配線基板の上に配置された半導体チップとを有する混成集積回路装置であって、
前記半導体チップにはトランジスタが形成され、
前記半導体チップはレジンにより被覆され、
前記サーマルビィアは前記半導体チップの下に配置され、
前記多層配線基板の裏面のグランド電極端子は、該グランド電極端子の表面が実装用接合材に濡れないレジスト膜で部分的に覆われて相互に独立した複数の該グランド電極端子となっており、
前記多層配線基板の裏面の電極端子のうち前記グランド電極以外の電極端子は、該多層配線基板の側面の上下に延在する端面スルーホール端子を介して各層の配線に接続されていることを特徴とする混成集積回路装置。A multilayer wiring board on which thermal vias are formed,
A hybrid integrated circuit device having a semiconductor chip disposed on the multilayer wiring board,
A transistor is formed on the semiconductor chip,
The semiconductor chip is covered with a resin,
The thermal via is disposed below the semiconductor chip ;
The ground electrode terminals on the back surface of the multilayer wiring board are a plurality of mutually independent ground electrode terminals that are partially covered with a resist film that does not wet the surface of the ground electrode terminals with the bonding material for mounting,
Electrode terminals other than the ground electrode among the electrode terminals on the back surface of the multilayer wiring board are connected to the wiring of each layer via end surface through-hole terminals extending vertically on the side surface of the multilayer wiring board. A hybrid integrated circuit device. 多層配線基板と、
前記多層配線基板の主面に搭載された能動部品および受動部品と、
前記能動部品の電極と前記多層配線基板の配線とを接続した導電性のワイヤと、
前記多層配線基板の裏面に設けられた前記多層配線の複数の電極端子とを有し、
前記多層配線基板の裏面のグランド電極端子は、該グランド電極端子の表面が実装用接合材に濡れないレジスト膜で部分的に覆われて相互に独立した複数の該グランド電極端子となっており、
前記多層配線基板の裏面の電極端子のうち前記グランド電極以外の電極端子は、該多層配線基板の側面の上下に延在する端面スルーホール端子を介して各層の配線に接続されていることを特徴とする混成集積回路装置。A multilayer wiring board;
Active components and passive components mounted on the main surface of the multilayer wiring board,
A conductive wire connecting the electrode of the active component and the wiring of the multilayer wiring board,
The have a plurality of electrode terminals of the multilayered wiring the multilayer wiring provided on the back surface of the substrate,
The ground electrode terminals on the back surface of the multilayer wiring board are a plurality of mutually independent ground electrode terminals that are partially covered with a resist film that does not wet the surface of the ground electrode terminals with the bonding material for mounting,
The multilayer wiring electrode terminals other than the ground electrode of the back surface of the electrode terminals of the substrate, characterized in that it is connected to the respective layers of the wiring through the end face through hole pins which extend above and below the side surfaces of the multilayer wiring board A hybrid integrated circuit device. 多層配線基板と、
前記多層配線基板の主面に搭載された少なくとも一つ以上の能動部品および受動部品と、
前記能動部品の電極と前記多層配線基板の配線とを接続した導電性のワイヤと、
前記多層配線基板の主面を覆うように多層配線基板に固定されたキャップと、
前記多層配線基板の裏面に設けられた前記多層配線の複数の電極端子とを有し、
前記多層配線基板の裏面のグランド電極端子は、該グランド電極端子の表面が実装用接合材に濡れないレジスト膜で部分的に覆われて相互に独立した複数の該グランド電極端子となっており、
前記多層配線基板の裏面の電極端子のうち前記グランド電極以外の電極端子は、該多層配線基板の側面の上下に延在する端面スルーホール端子を介して各層の配線に接続されていることを特徴とする混成集積回路装置。A multilayer wiring board;
At least one or more active components and passive components mounted on the main surface of the multilayer wiring board,
A conductive wire connecting the electrode of the active component and the wiring of the multilayer wiring board,
A cap fixed to the multilayer wiring board so as to cover a main surface of the multilayer wiring board,
The have a plurality of electrode terminals of the multilayered wiring the multilayer wiring provided on the back surface of the substrate,
The ground electrode terminals on the back surface of the multilayer wiring board are a plurality of mutually independent ground electrode terminals that are partially covered with a resist film that does not wet the surface of the ground electrode terminals with the bonding material for mounting,
The multilayer wiring electrode terminals other than the ground electrode of the back surface of the electrode terminals of the substrate, characterized in that it is connected to the respective layers of the wiring through the end face through hole pins which extend above and below the side surfaces of the multilayer wiring board A hybrid integrated circuit device. 請求項３記載の混成集積回路装置において、
前記キャップは多層配線基板に設けた窪み部分によって形成された引っ掛かり部分にフックを介して着脱自在に取り付けられていることを特徴とする混成集積回路装置。The hybrid integrated circuit device according to claim 3,
The hybrid integrated circuit device according to claim 1, wherein the cap is detachably attached via a hook to a hook formed by a recess provided in the multilayer wiring board. 請求項２乃至４のいずれか一に記載の混成集積回路装置において、
前記能動部品はレジンにより被覆されていることを特徴とする混成集積回路装置。The hybrid integrated circuit device according to any one of claims 2 to 4,
A hybrid integrated circuit device, wherein the active component is covered with a resin. 請求項１乃至５のいずれか一に記載の混成集積回路装置において、
前記多層配線基板は配線を介して誘電体層を多段に積み重ねた構造をしており、
前記誘電体層の間に設けられた信号配線はその上下を前記誘電体層を介してグランド配線で挟まれるストリップライン構造となっていることを特徴とする混成集積回路装置。The hybrid integrated circuit device according to any one of claims 1 to 5,
The multilayer wiring board has a structure in which dielectric layers are stacked in multiple stages via wiring,
A hybrid integrated circuit device, wherein a signal line provided between the dielectric layers has a strip line structure in which upper and lower portions of the signal line are sandwiched by ground lines via the dielectric layer. 請求項６に記載の混成集積回路装置において、
前記グランド配線は編み目構造であることを特徴とする混成集積回路装置。The hybrid integrated circuit device according to claim 6,
A hybrid integrated circuit device, wherein the ground wiring has a stitch structure. 請求項１乃至７のいずれか一に記載の混成集積回路装置において、
前記半導体チップは前記多層配線基板の主面に設けられた窪みに固定され、
前記半導体チップの電極面と前記多層配線基板の配線面の高さは略同一であり、
前記半導体チップの電極と前記配線を接続する前記ワイヤはほぼ直線状に延在していることを特徴とする混成集積回路装置。The hybrid integrated circuit device according to any one of claims 1 to 7,
The semiconductor chip is fixed to a depression provided on a main surface of the multilayer wiring board,
The height of the electrode surface of the semiconductor chip and the wiring surface of the multilayer wiring board are substantially the same,
The hybrid integrated circuit device, wherein the wire connecting the electrode of the semiconductor chip and the wiring extends substantially linearly.
JP26835495A 1995-10-17 1995-10-17 Hybrid integrated circuit device Expired - Fee Related JP3578366B2 (en)

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