JPH09199823A - Chip-on-board printed wiring board - Google Patents
Chip-on-board printed wiring boardInfo
- Publication number
- JPH09199823A JPH09199823A JP8026032A JP2603296A JPH09199823A JP H09199823 A JPH09199823 A JP H09199823A JP 8026032 A JP8026032 A JP 8026032A JP 2603296 A JP2603296 A JP 2603296A JP H09199823 A JPH09199823 A JP H09199823A
- Authority
- JP
- Japan
- Prior art keywords
- printed wiring
- wiring board
- board
- via hole
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、プリント配線板に
関し、特に放熱性を向上させたチップオンボードプリン
ト配線板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board, and more particularly to a chip on board printed wiring board having improved heat dissipation.
【０００２】[0002]
【従来の技術】従来、電子部品をプリント配線基板に搭
載する際に、搭載した電子部品を保護し、また持ち運び
の時の電子部品の脱落を防止するために、電子部品の表
面を樹脂で封止することがあった。近年、電子部品の小
型化による高密度実装が行われ、半導体素子のマイクロ
アセンブリ技術の進歩に伴い、半導体素子をまずパッケ
ージに収納した後に基板に実装する方法ではなく、ベア
チップを直接基板に実装するＣＯＢ（Chip on Board ）
技術が用いられるようになった。このＣＯＢ技術による
チップオンボードプリント配線板においては、保護のた
めに、搭載したベアチップの表面を樹脂で封止すること
が多い。2. Description of the Related Art Conventionally, when mounting an electronic component on a printed wiring board, the surface of the electronic component is sealed with a resin in order to protect the mounted electronic component and to prevent the electronic component from falling off during transportation. I had to stop. In recent years, high-density mounting has been performed by miniaturization of electronic components, and with the progress of microassembly technology of semiconductor elements, a bare chip is directly mounted on a substrate instead of mounting the semiconductor element in a package first and then mounting it on the substrate. COB (Chip on Board)
Technology has come into use. In the chip-on-board printed wiring board based on this COB technology, the surface of the mounted bare chip is often sealed with resin for protection.
【０００３】通常のパッケージ品をベアチップで置き換
えると、パッケージ部分の容積が省けるため、電装品の
小型化および薄型化が要求される電卓や腕時計、携帯電
話にＣＯＢ技術は多用されている。また、年々エレクト
ロニクス化の進む自動車用の電装品においても、相反す
る信頼性とコストの問題を両立させながら、小型化およ
び高密度化を図る必要があり、ＣＯＢ技術が取り入れら
れるようになった。When the usual package product is replaced with a bare chip, the volume of the package portion can be saved, so that the COB technology is widely used in calculators, wrist watches, and mobile phones that require miniaturization and thinning of electrical components. In addition, even in electrical components for automobiles, which are becoming more and more electronics year by year, it is necessary to reduce the size and increase the density while satisfying the conflicting reliability and cost problems, and COB technology has come to be adopted.
【０００４】図５は、従来用いられているプリント配線
基板にベアチップを搭載したチップオンボードプリント
配線板の一例の断面図である。プリント配線基板３１に
は、ガラスエポキシなどの複合材料やＢＴレジンなどの
高ガラス転移温度を有する高機能樹脂が使われている。
プリント配線基板３１上には、電気的接続のための銅箔
配線２と、ベアチップを載せるための銅箔のアイランド
３が形成されている。銅箔配線２には、バリアメタルと
してニッケルがメッキされ、さらにその上に金メッキが
施されている。FIG. 5 is a sectional view of an example of a chip-on-board printed wiring board in which a bare chip is mounted on a conventionally used printed wiring board. For the printed wiring board 31, a composite material such as glass epoxy or a high-performance resin having a high glass transition temperature such as BT resin is used.
On the printed wiring board 31, a copper foil wiring 2 for electrical connection and a copper foil island 3 for mounting a bare chip are formed. The copper foil wiring 2 is plated with nickel as a barrier metal, and gold is further plated thereon.
【０００５】アイランド３の上側にはベアチップ４が置
かれ、アイランド３とベアチップ４はエポキシをバイン
ダとして、導電性特性を持たせるために銀が混入された
導電性接着剤５で接着されている。ベアチップ４上の端
子と銅箔配線２は、扱いやすく耐腐蝕性のよい、線径２
５μｍの金ワイヤ６で電気的に接続されている。金ワイ
ヤ６と銅箔配線２の金メッキとは同金属接合となり、高
い信頼性が得られる。電流容量が不足するために太いワ
イヤが必要な場合には、金ワイヤをコストの点から使用
できないので、アルミワイヤを用いることが多い。ベア
チップの端子がアルミで生成されているので、アルミワ
イヤとベアチップの端子は同金属接合となる。エポキシ
系の封止樹脂７がベアチップ４と金ワイヤ６をプリント
配線基板３１上に封止する。エポキシ系樹脂は硬化後か
なり硬質となるため、熱衝撃などが発生するような用途
では、応力緩和を考慮してシリコン系樹脂を用いること
もある。A bare chip 4 is placed on the upper side of the island 3, and the island 3 and the bare chip 4 are bonded with a conductive adhesive 5 mixed with silver for imparting a conductive characteristic with epoxy as a binder. The terminals on the bare chip 4 and the copper foil wiring 2 are easy to handle and have good corrosion resistance.
It is electrically connected by a 5 μm gold wire 6. The gold wire 6 and the gold plating of the copper foil wiring 2 form the same metal joint, and high reliability is obtained. When a thick wire is required due to insufficient current capacity, an aluminum wire is often used because a gold wire cannot be used in terms of cost. Since the terminals of the bare chip are made of aluminum, the aluminum wire and the terminals of the bare chip have the same metal bonding. The epoxy type sealing resin 7 seals the bare chip 4 and the gold wire 6 on the printed wiring board 31. Since the epoxy resin becomes considerably hard after curing, a silicone resin may be used in consideration of stress relaxation in applications where thermal shock or the like occurs.
【０００６】アイランド３の下側には、放熱のためのビ
アホール８がプリント配線基板３１を貫通して設けられ
ている。ビアホール８は、電気的に接続され配線の一部
として使用されることを目的とせず、放熱のために設け
られたビアホールで、サーマルビアとも呼ばれる。ベア
チップ４から発生する熱の放熱経路は、アイランド３と
アイランドの下側に設けられたビアホール８を介してプ
リント配線基板３１内部と基板裏面に放熱する経路と、
封止樹脂７を介して赤外線放射として放熱する経路と、
封止樹脂を介して雰囲気中へ空気伝導する経路とがあ
る。赤外線放射や空気伝導による放熱は、空間や気体を
介して熱伝達が行われるため、固体を介して放熱する場
合に比べて、数倍から数十倍放熱効率が悪く、固体を介
するビアホールは有効な放熱手段である。A via hole 8 for heat dissipation is provided below the island 3 so as to penetrate the printed wiring board 31. The via hole 8 is not intended to be electrically connected and used as a part of wiring, but is a via hole provided for heat dissipation and is also called a thermal via. A heat radiation path for heat generated from the bare chip 4 is a path for radiating heat to the inside of the printed wiring board 31 and the back surface of the board via the island 3 and the via hole 8 provided on the lower side of the island.
A path for radiating infrared radiation through the sealing resin 7,
There is a path for conducting air into the atmosphere through the sealing resin. In the heat radiation by infrared radiation or air conduction, heat transfer is performed through space or gas, so the heat radiation efficiency is several to several tens of times lower than when radiating through solids, and via holes through solids are effective It is a good heat dissipation means.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、このよ
うな従来のチップオンボードプリント配線板では、放熱
用のビアホールをアイランドの下に形成するために、ビ
アホール間のピッチやビア径の制約から、配置可能なビ
アホール数が制限される。また、多層構造のプリント配
線基板を用いたとき、アイランド下に設けられたビアホ
ールは導電性接着剤を介して、ベアチップ裏面に電気的
に接続されることが多いため、アイランド下に設けられ
たビアホールをプリント配線基板の内層に接続する場合
には、回路設計上の制約が多く、内層を放熱板として用
いることが難しい。However, in such a conventional chip-on-board printed wiring board, since the via holes for heat dissipation are formed below the island, the layout is restricted due to the pitch between the via holes and the via diameter. The number of possible via holes is limited. In addition, when a printed wiring board having a multilayer structure is used, the via hole provided under the island is often electrically connected to the back surface of the bare chip via a conductive adhesive, so the via hole provided under the island is often used. When connecting to the inner layer of the printed wiring board, there are many restrictions in circuit design, and it is difficult to use the inner layer as a heat sink.
【０００８】近年、高度化が進む自動車用の電子制御装
置の最終段では、アクチュエータ駆動用のパワー素子な
どの発熱量の多い素子が使用されることが多い。このよ
うな素子のベアチップをプリント配線基板に搭載した場
合、そのベアチップの発熱量が、放熱量を上回ることが
あり、その場合には、熱の影響が生じるおそれがある。
したがって本発明は、上記従来の問題点に鑑み、搭載し
たベアチップが発生する熱の放熱効率を向上させ、ベア
チップの熱破壊を防止したチップオンボードプリント配
線板を提供することを目的とする。In recent years, in the final stage of electronic control devices for automobiles, which are becoming more sophisticated, elements that generate a large amount of heat, such as power elements for driving actuators, are often used. When a bare chip of such an element is mounted on a printed wiring board, the amount of heat generated by the bare chip may exceed the amount of heat radiation, and in that case, the influence of heat may occur.
Therefore, in view of the above-mentioned conventional problems, it is an object of the present invention to provide a chip-on-board printed wiring board that improves heat dissipation efficiency of heat generated by a mounted bare chip and prevents thermal destruction of the bare chip.
【０００９】[0009]
【課題を解決するための手段】上記目的を達するため
に、請求項１に記載の本発明は、プリント配線基板上に
搭載した電子部品を封止材で封止したチップオンボード
プリント配線板であって、前記プリント配線基板が前記
封止材と接する領域に、電気的に接続されないビアホー
ルを設けたものとした。また、請求項２に記載の発明
は、プリント配線基板が多層構造であって、プリント配
線基板が封止材と接する領域に設けるビアホールが当該
プリント配線基板の内層の１つだけに電気的に接続され
たものとした。To achieve the above object, the present invention according to claim 1 is a chip-on-board printed wiring board in which electronic components mounted on a printed wiring board are sealed with a sealing material. Therefore, a via hole that is not electrically connected is provided in a region where the printed wiring board is in contact with the sealing material. In the invention according to claim 2, the printed wiring board has a multi-layer structure, and the via hole provided in a region where the printed wiring board contacts the sealing material is electrically connected to only one of the inner layers of the printed wiring board. It was assumed that it was done.
【００１０】請求項３に記載の発明は、プリント配線基
板に上記電子部品がはめ込まれる座繰り部分が形成さ
れ、当該プリント配線基板が封止材と接する領域に前記
座繰り部分の側壁により一部を削り取られた電気的に接
続されないビアホールを設けたものとした。上記の座繰
り部分の側壁により一部を削り取られたビアホールの周
囲にはさらに電気的に接続されないビアホールを設ける
のが好ましい。請求項５に記載の発明は、プリント配線
基板が多層構造でかつ電子部品がはめ込まれる座繰り部
分が形成され、当該プリント配線基板が封止材と接する
領域に、前記座繰り部分の側壁により一部を削り取られ
たビアホールをプリント配線基板の内層の１つだけに電
気的に接続されたものとした。According to a third aspect of the present invention, a countersunk part into which the electronic component is fitted is formed on the printed wiring board, and a part of the side wall of the countersunk part is provided in a region where the printed wiring board contacts the sealing material. A via hole which was scraped off and was not electrically connected was provided. It is preferable to provide a via hole which is not electrically connected to the periphery of the via hole which is partially removed by the side wall of the counterbore. According to a fifth aspect of the present invention, the printed wiring board has a multi-layered structure, and a counterbored portion into which an electronic component is fitted is formed, and a side wall of the counterbored portion is provided in a region where the printed wiring board contacts the sealing material. The via hole whose part was cut off was electrically connected to only one of the inner layers of the printed wiring board.
【００１１】[0011]
【作用】請求項１記載の発明においては、プリント配線
基板が封止材と接する部分に設けられたビアホールを介
して、プリント配線基板と基板裏面に放熱する経路が形
成される。すなわち固体を介して放熱するので高い放熱
効率が得られる。また、請求項２記載のものでは、プリ
ント配線基板が封止材と接する部分に設けられたビアホ
ールは、ベアチップなど電子部品と電気的に接続されて
いないため、グランド層又は電源層などの内層と接続す
ることができ、内層を放熱板として使用することができ
る。According to the first aspect of the present invention, a path for radiating heat to the printed wiring board and the back surface of the printed wiring board is formed through the via hole provided in the portion where the printed wiring board contacts the sealing material. That is, since heat is radiated through the solid, high heat dissipation efficiency can be obtained. Further, according to the second aspect, the via hole provided in the portion where the printed wiring board is in contact with the encapsulant is not electrically connected to an electronic component such as a bare chip. It can be connected and the inner layer can be used as a heat sink.
【００１２】さらに、請求項３記載のものでは、座繰り
部分に電子部品がはめ込まれ、座繰り部分の側壁で一部
を削られたビアホールが電子部品の側面と封止材を介し
て対面するので、封止材とビアホールの接触面積を増大
させ、電子部品の側面や上面からの発熱をビアホールへ
逃がしやすい。また、上記一部を削られたビアホールの
周囲にさらにビアホールを配置することにより、放熱が
より良好に行なわれる。請求項５記載のものでは、座繰
り部分の側壁で一部を削られたビアホールが電子部品の
側面と封止材を介して対面することにより電子部品の側
面や上面からの発熱をビアホールへ逃がしやすいととも
に、ビヤホールがプリント配線基板の内層と接続してこ
れを放熱板とし、一層放熱性能が向上する。Further, according to a third aspect of the present invention, the electronic component is fitted in the countersunk portion, and the via hole partially cut by the side wall of the countersink portion faces the side surface of the electronic component via the sealing material. Therefore, the contact area between the sealing material and the via hole is increased, and heat generated from the side surface or the upper surface of the electronic component can be easily released to the via hole. Further, by disposing a via hole further around the above-mentioned partly shaved via hole, heat dissipation can be performed better. According to another aspect of the present invention, the via hole partially cut by the side wall of the counterbore portion faces the side surface of the electronic component via the sealing material, so that heat generated from the side surface or the upper surface of the electronic component is released to the via hole. In addition to being easy, the via hole is connected to the inner layer of the printed wiring board to serve as a heat dissipation plate, and the heat dissipation performance is further improved.
【００１３】[0013]
【発明の実施の形態】本発明の実施の形態を実施例によ
り説明する。図１は第１の実施例の断面図である。ガラ
スエポキシ系樹脂で形成されたプリント配線基板１上
に、銅箔配線２と、銅箔のアイランド３が形成されてい
る。アイランド３の上側にはベアチップ４が置かれ、ア
イランド３とベアチップ４は導電性接着剤５で接着され
ている。ベアチップ４上の端子と銅箔配線２は金ワイヤ
６で電気的に接続されている。そして、エポキシ系の封
止樹脂７がベアチップ４と金ワイヤ６をプリント配線基
板１上に封止する。以上の構成は、プリント配線基板３
１のかわりにプリント配線基板１となっている点を除き
図５に示す従来例と同じである。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to examples. FIG. 1 is a sectional view of the first embodiment. Copper foil wirings 2 and copper foil islands 3 are formed on a printed wiring board 1 made of glass epoxy resin. A bare chip 4 is placed on the upper side of the island 3, and the island 3 and the bare chip 4 are bonded with a conductive adhesive 5. The terminal on the bare chip 4 and the copper foil wiring 2 are electrically connected by the gold wire 6. Then, the epoxy type sealing resin 7 seals the bare chip 4 and the gold wire 6 on the printed wiring board 1. The above configuration is the printed wiring board 3
5 is the same as the conventional example shown in FIG. 5 except that a printed wiring board 1 is used instead of 1.
【００１４】プリント配線基板１には、アイランド３の
下側になる領域に放熱のためのビアホール８が貫通して
設けられている。そしてさらに、封止樹脂７に覆われか
つアイランド３と銅箔配線２に覆われていない部分に、
同じくプリント配線基板１を貫通するビアホール９が設
けられている。プリント配線基板にビアホール９用の穴
を開ける工程では、制御盤にドリルを一括して複数個取
り付け、ビアホール８の形成と同時に形成する。ビアホ
ール９は高発熱部分であるベアチップの近傍に、できる
だけ数多く形成することが望ましい。The printed wiring board 1 is provided with a via hole 8 for radiating heat in a region below the island 3. Further, in a portion covered with the sealing resin 7 and not covered with the island 3 and the copper foil wiring 2,
Similarly, a via hole 9 penetrating the printed wiring board 1 is provided. In the step of forming a hole for the via hole 9 in the printed wiring board, a plurality of drills are collectively attached to the control board and formed simultaneously with the formation of the via hole 8. It is desirable to form as many via holes 9 as possible in the vicinity of the bare chip, which is a high heat generating portion.
【００１５】この実施例は以上のように構成されている
ので、ビアホール８による固体経路に加えて、ビアホー
ル９を介してプリント配線基板１内部と基板裏面に放熱
する新たな固体を介する放熱経路が得られた。これによ
り、ベアチップが発生する熱の放熱効率が向上し、ベア
チップの熱破壊を防止することができる。このビアホー
ル９はアイランド３と銅箔配線２に覆われていない部分
に設けられているから、電気的な接続から遮断されプリ
ント配線基板１上の回路に影響を与えることがない。ま
た、ビアホール８と新たなビアホール９の形成は一括し
て同時に行なうことができるので、必要なコストの増加
はほとんどない。なお、放熱効率を向上させるために、
設計上許される範囲内で、封止樹脂７に熱伝導度の大き
い材料を選定すると、封止樹脂を介する放熱効率もさら
に効果的に高めることができる。Since this embodiment is constructed as described above, in addition to the solid-state path by the via hole 8, a new solid-state heat-dissipating path for radiating heat to the inside of the printed wiring board 1 and the rear surface of the board via the via-hole 9 is provided. Was obtained. Thereby, the heat dissipation efficiency of the heat generated by the bare chip is improved, and the thermal destruction of the bare chip can be prevented. Since the via hole 9 is provided in the portion not covered with the island 3 and the copper foil wiring 2, it is cut off from the electrical connection and does not affect the circuit on the printed wiring board 1. Further, the formation of the via hole 8 and the new via hole 9 can be simultaneously performed in a batch, so that the required cost hardly increases. In order to improve heat dissipation efficiency,
If a material having a high thermal conductivity is selected for the sealing resin 7 within the range allowed by the design, the heat radiation efficiency through the sealing resin can be further effectively increased.
【００１６】次に図２は本発明の第２の実施例の断面図
を示す。プリント配線基板１１には、ガラスエポキシ系
樹脂が使われ、内部に電源層１２とグランド層１３とし
て使用される銅箔で作られた内層が設けられている。ア
イランド３の下側には、プリント配線基板１１を貫通す
る放熱のためのビアホール８が設けられている。プリン
ト配線基板１１の、封止樹脂７に覆われかつアイランド
３と銅箔配線２に覆われていない部分に、プリント配線
基板１１を貫通し、電源層１２のみに接続されているビ
アホール１９が設けられている。その他の構成は図１に
示す第１の実施例と同じである。Next, FIG. 2 shows a sectional view of a second embodiment of the present invention. A glass epoxy resin is used for the printed wiring board 11, and an inner layer made of copper foil used as a power supply layer 12 and a ground layer 13 is provided inside. Below the island 3, a via hole 8 for radiating heat that penetrates the printed wiring board 11 is provided. A via hole 19 penetrating the printed wiring board 11 and connected to only the power supply layer 12 is provided in a portion of the printed wiring board 11 which is covered with the sealing resin 7 and is not covered with the island 3 and the copper foil wiring 2. Has been. The other structure is the same as that of the first embodiment shown in FIG.
【００１７】これにより、第１の実施例と同様の効果が
得られるとともに、エレクトロマイグレーションやイオ
ンマイグレーションなどの問題の無い範囲であれば、内
層である銅箔で作られたグランド層を放熱板として使用
できるので、さらに放熱効率を向上させることができ
る。ここでは、ビアホール１９は内層の１つとのみ接続
されるので、プリント配線基板１１上の回路に電気的影
響を与えない。As a result, the same effect as that of the first embodiment can be obtained, and the ground layer made of the copper foil, which is the inner layer, is used as the heat sink as long as there is no problem such as electromigration and ion migration. Since it can be used, the heat dissipation efficiency can be further improved. Here, since the via hole 19 is connected to only one of the inner layers, it does not electrically affect the circuit on the printed wiring board 11.
【００１８】次に図３および図４に本発明の第３の実施
例を示す。図３は本実施例の断面図、図４はワイヤおよ
び封止樹脂を省いた上面図である。プリント配線基板２
１には、ガラスエポキシ系樹脂が使われ、内部に銅箔で
作られた電源層２２とグランド層２３が設けられてい
る。。プリント配線基板２１上には、電気的接続のため
の銅箔配線２と、ベアチップをはめ込むための座繰り部
分２４が設けられている。座繰り部分２４は、ミルまた
はドリルでＮＣ加工される。ベアチップを載せる部分は
放熱効率を考慮して、内層の銅箔部分をアイランド２５
として残し、アイランド２５の周囲は銅箔を削り、周囲
の電源層２２から絶縁させてある。Next, FIGS. 3 and 4 show a third embodiment of the present invention. FIG. 3 is a cross-sectional view of this embodiment, and FIG. 4 is a top view in which wires and sealing resin are omitted. Printed wiring board 2
1, a glass epoxy resin is used, and a power supply layer 22 and a ground layer 23 made of copper foil are provided inside. . On the printed wiring board 21, a copper foil wiring 2 for electrical connection and a countersunk portion 24 for fitting a bare chip are provided. The counterbore portion 24 is NC processed by a mill or a drill. Considering the heat dissipation efficiency, the part where the bare chip is placed is the island 25
The copper foil is scraped off around the island 25 and insulated from the surrounding power supply layer 22.
【００１９】アイランド２５の上側にはベアチップ４が
置かれ、アイランド２５とベアチップ４は導電性接着剤
５で接着されている。ベアチップ４上の端子と銅箔配線
２は、金ワイヤ６で電気的に接続されている。エポキシ
系の封止樹脂２７がベアチップ４と金ワイヤ６をプリン
ト配線基板２１上に封止し、座繰り部分２４を充填して
いる。ベアチップ４の下側には、放熱のためのビアホー
ル２８がプリント配線基板２１とアイランド２５を貫通
して設けられている。プリント配線基板２１の、封止樹
脂２７に覆われかつアイランド２５と銅箔配線２に覆わ
れていない部分に、プリント配線基板２１を貫通し、グ
ランド層２３のみに接続されているビアホール２９、３
０が設けられている。ビアホール３０は座繰り部分２４
の側壁により一部を削りとられている。図４に示すよう
に、座繰り部分２４の側壁にそってビアホール３０が設
けられ、これらビアホール３０の周囲にビアホール２９
が配置されている。The bare chip 4 is placed on the upper side of the island 25, and the island 25 and the bare chip 4 are bonded with a conductive adhesive 5. The terminal on the bare chip 4 and the copper foil wiring 2 are electrically connected by the gold wire 6. The epoxy type sealing resin 27 seals the bare chip 4 and the gold wire 6 on the printed wiring board 21 and fills the countersunk portion 24. A via hole 28 for heat dissipation is provided below the bare chip 4 so as to penetrate the printed wiring board 21 and the island 25. Via holes 29, 3 penetrating the printed wiring board 21 and connected to only the ground layer 23 are formed in a portion of the printed wiring board 21 which is covered with the sealing resin 27 and is not covered with the island 25 and the copper foil wiring 2.
0 is provided. The beer hole 30 is a countersunk portion 24.
Part of it has been scraped off by the side wall. As shown in FIG. 4, via holes 30 are provided along the side wall of the counterbore portion 24, and the via holes 29 are provided around these via holes 30.
Is arranged.
【００２０】本実施例においても、第２の実施例と同様
に、プリント配線基板の内層である銅箔のグランド層２
３を放熱板として使用するので放熱効率を向上させるこ
とができる。また、ビアホール３０の一部が座繰り部分
２４で削られているので、ビアホール３０の内壁とベア
チップ４の側壁が封止樹脂２７を介して対面する。これ
により、ベアチップ４の側面や上面からの熱もビアホー
ル３０、２９を介して効率良く放熱される。Also in this embodiment, as in the second embodiment, the ground layer 2 of copper foil, which is the inner layer of the printed wiring board, is used.
Since 3 is used as a heat dissipation plate, heat dissipation efficiency can be improved. Further, since a part of the via hole 30 is cut by the counterbore portion 24, the inner wall of the via hole 30 and the side wall of the bare chip 4 face each other via the sealing resin 27. As a result, heat from the side surface and the upper surface of the bare chip 4 is also efficiently radiated through the via holes 30 and 29.
【００２１】[0021]
【発明の効果】以上のとおり、本発明は、プリント配線
基板上に搭載した電子部品を封止材で封止したチップオ
ンボードプリント配線板において、プリント配線基板が
封止材と接する領域にビアホールを設けたので、プリン
ト配線基板と基板裏面に放熱する経路、すなわち固体を
介して放熱する新たな経路が設けられ、搭載した電子部
品が発生する熱の放熱効率を向上させ、電子部品の熱破
壊が防止される。As described above, according to the present invention, in a chip-on-board printed wiring board in which electronic components mounted on a printed wiring board are sealed with a sealing material, a via hole is provided in a region where the printed wiring board contacts the sealing material. Since it is provided, a route for radiating heat to the printed wiring board and the back surface of the substrate, that is, a new route for radiating heat via solids, is provided to improve the efficiency of radiating the heat generated by the mounted electronic components and to destroy the heat of the electronic components. Is prevented.
【００２２】また、プリント配線基板に座繰り部分を形
成し、この座繰り部分に電子部品をはめ込むとともに、
封止材と接する領域に設けたビアホールの一部を上記座
繰り部分の側壁で削り取られたものとすることにより、
封止材とビアホールの接触面積を増大させ、電子部品の
側面や上面からの発熱をビアホールへ逃がしやすいた
め、さらに放熱効率が向上する。さらに、プリント配線
基板が内部に電源層やグランド層など内層を有する多層
構造の場合、上記封止材と接する領域に設けたビアホー
ルをプリント配線基板の内層の１つに接続することによ
り、内層を放熱板として使用することができ、より一層
放熱効率が向上する。Further, a countersunk part is formed on the printed wiring board, and electronic parts are fitted into the countersunk part, and
By making a part of the via hole provided in the region in contact with the encapsulant cut by the side wall of the counterbore part,
Since the contact area between the encapsulant and the via hole is increased and heat generated from the side surface or the upper surface of the electronic component can be easily released to the via hole, the heat dissipation efficiency is further improved. Furthermore, in the case where the printed wiring board has a multi-layer structure having an inner layer such as a power supply layer or a ground layer inside, by connecting a via hole provided in a region in contact with the encapsulant to one of the inner layers of the printed wiring board, the inner layer is formed. It can be used as a heat dissipation plate, and the heat dissipation efficiency is further improved.
【図１】本発明の第１の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the present invention.
【図２】第２の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment.
【図３】第３の実施例の断面図である。FIG. 3 is a sectional view of a third embodiment.
【図４】第３の実施例の上面図である。FIG. 4 is a top view of the third embodiment.
【図５】従来例を示す図である。FIG. 5 is a diagram showing a conventional example.
１、１１、２１、３１ プリント配線基板 ２ 銅箔配線 ３、２５ アイランド ４ ベアチップ ５ 導伝性接着剤 ６ 金ワイヤ ７、２７ 封止樹脂 ８、９、１９、２８、２９、３０ ビアホール １２、２２ 電源層 １３、２３ グランド層 1, 11, 21, 31 Printed wiring board 2 Copper foil wiring 3, 25 Island 4 Bare chip 5 Conductive adhesive 6 Gold wire 7, 27 Encapsulating resin 8, 9, 19, 28, 29, 30 Via hole 12, 22 Power layer 13, 23 Ground layer
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０５Ｋ 3/46 Ｈ０１Ｌ 23/12 Ｌ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location H05K 3/46 H01L 23/12 L
Claims (5)
を封止材で封止したチップオンボードプリント配線板で
あって、前記プリント配線基板が前記封止材と接する領
域に、電気的に接続されないビアホールを設けたことを
特徴とするチップオンボードプリント配線板。1. A chip-on-board printed wiring board in which an electronic component mounted on a printed wiring board is sealed with a sealing material, the printed wiring board being electrically connected to a region in contact with the sealing material. A chip-on-board printed wiring board characterized by having a via hole that is not formed.
た電子部品を封止材で封止したチップオンボードプリン
ト配線板であって、前記プリント配線基板が前記封止材
と接する領域に、当該プリント配線基板の内層の１つだ
けに電気的に接続されたビアホールを設けたことを特徴
とするチップオンボードプリント配線板。2. A chip-on-board printed wiring board in which electronic components mounted on a multilayer printed wiring board are sealed with a sealing material, wherein the printed wiring board is provided in a region in contact with the sealing material. A chip-on-board printed wiring board, wherein a via hole electrically connected to only one of the inner layers of the printed wiring board is provided.
を封止材で封止したチップオンボードプリント配線板で
あって、前記プリント配線基板に前記電子部品がはめ込
まれる座繰り部分が形成され、当該プリント配線基板が
前記封止材と接する領域に前記座繰り部分の側壁により
一部を削り取られた電気的に接続されないビアホールを
設けたことを特徴とするチップオンボードプリント配線
板。3. A chip-on-board printed wiring board in which an electronic component mounted on a printed wiring board is sealed with a sealing material, and a counterbore portion into which the electronic component is fitted is formed on the printed wiring board. A chip-on-board printed wiring board, characterized in that a via hole, which is partially removed by a side wall of the countersunk portion, is provided in a region where the printed wiring board is in contact with the sealing material and which is not electrically connected.
領域において、前記座繰り部分の側壁により一部を削り
取られたビアホールの周囲にさらに電気的に接続されな
いビアホールが設けられていることを特徴とする請求項
３記載のチップオンボードプリント配線板。4. A via hole, which is not electrically connected, is provided around the via hole that is partially removed by the side wall of the counterbore portion in a region where the printed wiring board contacts the sealing material. The chip-on-board printed wiring board according to claim 3.
た電子部品を封止材で封止したチップオンボードプリン
ト配線板であって、前記プリント配線基板に前記電子部
品がはめ込まれる座繰り部分が形成され、当該プリント
配線基板が前記封止材と接する領域に、前記座繰り部分
の側壁により一部を削り取られ当該プリント配線基板の
内層の１つだけに電気的に接続されたビアホールを設け
たことを特徴とするチップオンボードプリント配線板。5. A chip-on-board printed wiring board in which an electronic component mounted on a printed wiring board having a multilayer structure is sealed with a sealing material, and a counterbore portion in which the electronic component is fitted to the printed wiring board. A via hole is formed in a region where the printed wiring board is in contact with the encapsulant, and a part of which is removed by the side wall of the counterbore portion and electrically connected to only one inner layer of the printed wiring board. A chip-on-board printed wiring board characterized in that
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8026032A JPH09199823A (en) | 1996-01-19 | 1996-01-19 | Chip-on-board printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8026032A JPH09199823A (en) | 1996-01-19 | 1996-01-19 | Chip-on-board printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09199823A true JPH09199823A (en) | 1997-07-31 |
Family
ID=12182373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8026032A Withdrawn JPH09199823A (en) | 1996-01-19 | 1996-01-19 | Chip-on-board printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09199823A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001189534A (en) * | 1999-12-27 | 2001-07-10 | Kyocera Corp | Ceramic wiring board |
| JP2004095586A (en) * | 2002-08-29 | 2004-03-25 | Denso Corp | Electric apparatus and wiring board |
| KR100462785B1 (en) * | 2002-11-12 | 2004-12-23 | 삼성에스디아이 주식회사 | Hybrid IC |
| KR100548013B1 (en) * | 1999-05-17 | 2006-02-01 | 삼성테크윈 주식회사 | Chip module for IC card and manufacturing method of the same |
| JP2007096009A (en) * | 2005-09-29 | 2007-04-12 | Sanyo Electric Co Ltd | Laminated circuit substrate and portable electronic equipment with the same |
| JP2009010671A (en) * | 2007-06-28 | 2009-01-15 | Daishinku Corp | Piezoelectric vibrating device |
| CN104302096A (en) * | 2014-08-27 | 2015-01-21 | 无锡长辉机电科技有限公司 | Pcb |
| CN104349597A (en) * | 2013-07-26 | 2015-02-11 | 集邦联合制造股份有限公司 | High heat dissipation circuit board set |
| JP2017117824A (en) * | 2015-12-21 | 2017-06-29 | 日立オートモティブシステムズ株式会社 | Electronic control device |
| CN111199928A (en) * | 2018-11-20 | 2020-05-26 | 日月光半导体制造股份有限公司 | Semiconductor package structure and semiconductor manufacturing method |
-
1996
- 1996-01-19 JP JP8026032A patent/JPH09199823A/en not_active Withdrawn
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100548013B1 (en) * | 1999-05-17 | 2006-02-01 | 삼성테크윈 주식회사 | Chip module for IC card and manufacturing method of the same |
| JP2001189534A (en) * | 1999-12-27 | 2001-07-10 | Kyocera Corp | Ceramic wiring board |
| JP2004095586A (en) * | 2002-08-29 | 2004-03-25 | Denso Corp | Electric apparatus and wiring board |
| KR100462785B1 (en) * | 2002-11-12 | 2004-12-23 | 삼성에스디아이 주식회사 | Hybrid IC |
| JP2007096009A (en) * | 2005-09-29 | 2007-04-12 | Sanyo Electric Co Ltd | Laminated circuit substrate and portable electronic equipment with the same |
| JP2009010671A (en) * | 2007-06-28 | 2009-01-15 | Daishinku Corp | Piezoelectric vibrating device |
| CN104349597A (en) * | 2013-07-26 | 2015-02-11 | 集邦联合制造股份有限公司 | High heat dissipation circuit board set |
| CN104302096A (en) * | 2014-08-27 | 2015-01-21 | 无锡长辉机电科技有限公司 | Pcb |
| JP2017117824A (en) * | 2015-12-21 | 2017-06-29 | 日立オートモティブシステムズ株式会社 | Electronic control device |
| CN111199928A (en) * | 2018-11-20 | 2020-05-26 | 日月光半导体制造股份有限公司 | Semiconductor package structure and semiconductor manufacturing method |
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Legal Events
| Date | Code | Title | Description |
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| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20030401 |