JP2008186957A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP2008186957A
JP2008186957A JP2007018465A JP2007018465A JP2008186957A JP 2008186957 A JP2008186957 A JP 2008186957A JP 2007018465 A JP2007018465 A JP 2007018465A JP 2007018465 A JP2007018465 A JP 2007018465A JP 2008186957 A JP2008186957 A JP 2008186957A
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chip
semiconductor device
chip surface
wires
semiconductor
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JP4881752B2 (en
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Shinichi Tanitaka
真一 谷高
Hiroshi Ishikawa
寛 石川
Kenji Kitamura
謙二 北村
Koichiro Sato
浩一郎 佐藤
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Honda Motor Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof wherein a temperature distribution due to heat generation in the chip surface is made uniform and the improvement of the power cycle life is intended in a power semiconductor device such as an IGBT, etc. <P>SOLUTION: This semiconductor device 10 comprises electrodes on the front and rear chip surfaces of a semiconductor chip (IGBT device 11, etc.), and a current flows between an electrode on one chip surface and an electrode on the other chip surface upon ON-operation. A plurality of wires 15 are connected to the electrodes (emitter electrodes 22-1 to 22-6) on one chip surface in uneven arrangement distribution, and the number of wires connected to the periphery of one chip surface is larger than that of wires connected to the central portion thereof. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は半導体装置およびその製造方法に関し、特に、半導体チップの表裏のチップ面に備えられた電極の一方の電極に複数のワイヤを接続し両チップ面の電極間に電流を流すパワー半導体装置であってチップ面での温度分布を中央部と周辺部で均一化した半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a power semiconductor device in which a plurality of wires are connected to one electrode of electrodes provided on the front and back chip surfaces of a semiconductor chip and current flows between the electrodes on both chip surfaces. The present invention also relates to a semiconductor device in which the temperature distribution on the chip surface is made uniform in the central portion and the peripheral portion, and a manufacturing method thereof.

例えば自動車では、搭載された多数の電気機器に必要な電力を供給するために電力系電気回路が設けられている。この電力系電気回路では、多くのパワー半導体装置が使用されている。パワー半導体装置の一例としてＩＧＢＴがある。ＩＧＢＴはスイッチング素子として使用される半導体装置であり、その等価回路はバイポーラトランジスタとＭＯＳＦＥＴを並列接合した電気回路で表現される。ＩＧＢＴの半導体素子（以下「半導体チップ」または「チップ」とも記す）は表裏のチップ面を有し、ＩＧＢＴがオンしたとき表裏の方向（縦方向）に電流が流れる。ＩＧＢＴは、例えば表面から見ると、同一の構造を半導体構造を有する複数のチップ要素に分離されており、ＩＧＢＴはこれらの複数のチップ要素の集合体として構成されている。ＩＧＢＴでは、複数のチップ要素のそれぞれがスイッチング素子として機能し、全体としてオン・オフする。   For example, in an automobile, a power system electric circuit is provided in order to supply necessary electric power to a large number of mounted electric devices. Many power semiconductor devices are used in this electric power circuit. An example of a power semiconductor device is an IGBT. An IGBT is a semiconductor device used as a switching element, and its equivalent circuit is expressed by an electric circuit in which a bipolar transistor and a MOSFET are joined in parallel. An IGBT semiconductor element (hereinafter also referred to as “semiconductor chip” or “chip”) has front and back chip surfaces, and when the IGBT is turned on, a current flows in the front and back direction (vertical direction). When viewed from the surface, for example, the IGBT is separated into a plurality of chip elements having the same structure as the semiconductor structure, and the IGBT is configured as an aggregate of the plurality of chip elements. In the IGBT, each of a plurality of chip elements functions as a switching element and is turned on / off as a whole.

上記のＩＧＢＴでは、複数のチップ要素のそれぞれに対応して、その表裏の両チップ面のいずれか一方のチップ面に複数本の通電用ワイヤが接続されている。   In the above-described IGBT, a plurality of energization wires are connected to either one of the front and back chip surfaces corresponding to each of the plurality of chip elements.

上記ＩＧＢＴ等のパワー半導体装置では、半導体装置がオン動作して半導体装置で通電状態が生じた時に、通電による発熱が偏在し、チップ面上での温度分布の不均一化の問題が提起される。   In the power semiconductor device such as the IGBT described above, when the semiconductor device is turned on and an energized state is generated in the semiconductor device, heat generation due to energization is unevenly distributed, which raises a problem of uneven temperature distribution on the chip surface. .

パワー半導体装置での温度分布の不均一を解決する従来技術として特許文献１に記載されたパワー半導体モジュールが存する。このパワー半導体モジュールでは、熱拡散部材を付設することにより、パワー半導体チップの温度分布を均一化している。また一般的な半導体装置に関してその放熱性を高めるための従来技術として特許文献２，３に記載された半導体装置が存する。
特開２０００−３０７０５８号公報 特開２００３−２２４２３４号公報 特開２００３−１６３３１４号公報 There is a power semiconductor module described in Patent Document 1 as a prior art for solving non-uniform temperature distribution in a power semiconductor device. In this power semiconductor module, the temperature distribution of the power semiconductor chip is made uniform by providing a heat diffusion member. Further, there are semiconductor devices described in Patent Documents 2 and 3 as conventional techniques for improving heat dissipation of general semiconductor devices.
JP 2000-307058 A JP 2003-224234 A JP 2003-163314 A

従来のＩＧＢＴでの複数本のワイヤの配線およびチップ面への接続（ワイヤボンド）に関する実装レイアウトでは、当該チップ面上において均一な位置関係に基づく配置となるように設計されていた。そのため、ＩＧＢＴがオン動作し、ＩＧＢＴに電流が流れると、チップから熱を逃がす放熱性、ワイヤ配列のバランスから、ＩＧＢＴのチップ面の中央部での発熱が高熱化して温度が高くなり、周辺部で温度が低くなるという温度分布の不均一化が生じていた。この問題は、前述した特許文献１〜３のいずれの発明によって解決することはできない。このようなＩＧＢＴ等のパワー半導体装置でのチップ中央部での高熱化は、当該パワー半導体装置のパワーサイクル寿命を短くしていた。   The mounting layout related to wiring of a plurality of wires and connection to a chip surface (wire bonding) in a conventional IGBT has been designed to be arranged based on a uniform positional relationship on the chip surface. Therefore, when the IGBT is turned on and a current flows through the IGBT, the heat generation at the center of the chip surface of the IGBT becomes high due to the heat dissipation that releases heat from the chip and the balance of the wire arrangement, and the temperature increases. As a result, the temperature distribution became non-uniform. This problem cannot be solved by any of the inventions of Patent Documents 1 to 3 described above. The increase in heat at the center of the chip in such a power semiconductor device such as an IGBT shortens the power cycle life of the power semiconductor device.

本発明の目的は、上記の課題を解決することにあり、ＩＧＢＴ等のパワー半導体装置においてチップ面内の発熱による温度分布を均一化し、パワーサイクル寿命の向上を企図した半導体装置およびその製造方法を提供することにある。   SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and a semiconductor device and a method for manufacturing the semiconductor device intended to improve the power cycle life by uniformizing the temperature distribution due to heat generation in the chip surface in a power semiconductor device such as an IGBT. It is to provide.

本発明に係る半導体装置およびその製造方法は、上記目的を達成するために、次のように構成される。   In order to achieve the above object, a semiconductor device and a manufacturing method thereof according to the present invention are configured as follows.

第１の半導体装置（請求項１に対応）は、半導体チップの表裏のチップ面に電極を備え、オン動作時に一方のチップ面の電極と他方のチップ面の電極の間で電流が流れる半導体装置であり、半導体チップの一方のチップ面の電極には複数のワイヤが不均一な配置分布で接続され、かつ、所定の基準に基づいて、一方のチップ面の周辺部に接続されるワイヤの本数は一方のチップ面の中央部に接続されるワイヤの本数よりも多くされるように構成される。   A first semiconductor device (corresponding to claim 1) is provided with electrodes on the front and back chip surfaces of a semiconductor chip, and a current flows between an electrode on one chip surface and an electrode on the other chip surface during an ON operation. The number of wires connected to the peripheral part of one chip surface based on a predetermined standard, with a plurality of wires connected to the electrode on one chip surface of the semiconductor chip in a non-uniform arrangement distribution Is configured to be larger than the number of wires connected to the central portion of one chip surface.

上記の構成では、半導体装置に含まれる半導体チップのチップ面に接続される複数の通電用ワイヤの実装について、チップ面の中央部と周辺部の抵抗バランスを配慮して不均一な配置分布とし、かつ周辺部に接続されるワイヤの本数を中央部に接続されるワイヤの本数よりも多くする。これによって、半導体チップのチップ面の温度分布を均一化し、通電による発熱バランスを良好なものとする。   In the above configuration, with respect to the mounting of a plurality of energizing wires connected to the chip surface of the semiconductor chip included in the semiconductor device, the distribution of the non-uniform arrangement is considered in consideration of the resistance balance between the central portion and the peripheral portion of the chip surface, In addition, the number of wires connected to the peripheral portion is made larger than the number of wires connected to the central portion. Thereby, the temperature distribution on the chip surface of the semiconductor chip is made uniform, and the heat generation balance by energization is made good.

第２の半導体装置（請求項２に対応）は、半導体チップの表裏のチップ面に電極を備え、オン動作時に一方のチップ面の電極と他方のチップ面の電極の間で電流が流れる半導体装置であり、半導体チップの一方のチップ面の電極には複数のワイヤが均一な配置分布で接続され、かつ、所定の基準に基づいて、一方のチップ面の周辺部に接続されるワイヤの断面積は一方のチップ面の中央部に接続されるワイヤの断面積よりも大きくされるように構成される。   A second semiconductor device (corresponding to claim 2) is provided with electrodes on the front and back chip surfaces of a semiconductor chip, and a current flows between an electrode on one chip surface and an electrode on the other chip surface during an ON operation. A plurality of wires are connected to the electrode on one chip surface of the semiconductor chip in a uniform arrangement distribution, and the cross-sectional area of the wire connected to the peripheral portion of one chip surface based on a predetermined standard Is configured to be larger than the cross-sectional area of the wire connected to the central portion of one chip surface.

上記の構成では、半導体装置に含まれる半導体チップのチップ面に接続される複数の通電用ワイヤの実装について、チップ面の中央部と周辺部の抵抗バランスを配慮し、均一な配置分布を前提としつつ、周辺部に接続されるワイヤの断面積を中央部に接続されるワイヤの断面積よりも大きくする。これによって、半導体チップのチップ面の温度分布を均一化し、通電による発熱バランスを良好なものとしている。   In the above configuration, regarding the mounting of a plurality of energizing wires connected to the chip surface of the semiconductor chip included in the semiconductor device, the resistance balance between the central portion and the peripheral portion of the chip surface is considered, and a uniform distribution is assumed. Meanwhile, the cross-sectional area of the wire connected to the peripheral part is made larger than the cross-sectional area of the wire connected to the central part. Thereby, the temperature distribution on the chip surface of the semiconductor chip is made uniform, and the heat generation balance by energization is made good.

第３の半導体装置（請求項３に対応）は、上記の第１および第２の構成において、上記の所定の基準は、半導体チップのチップ面における通電発熱に基づく温度分布が均一になる条件を満たすための基準であることを特徴とする。従って、周辺部におけるワイヤの本数の決定、あるいは、ワイヤの大きな断面積の決定は、当該所定の基準に基づき最適に決定される。   In the third semiconductor device (corresponding to claim 3), in the first and second configurations, the predetermined reference is that a temperature distribution based on current generation heat generation on the chip surface of the semiconductor chip is uniform. It is a criterion for satisfying. Therefore, the determination of the number of wires in the peripheral portion or the determination of the large cross-sectional area of the wire is optimally determined based on the predetermined criterion.

第４の半導体装置（請求項４に対応）は、半導体チップの表裏のチップ面に電極を備え、オン動作時に一方のチップ面の電極と他方のチップ面の電極の間で電流が流れる半導体装置であり、半導体チップの一方のチップ面の電極には複数のワイヤが均一な配置分布で接続され、かつ、チップ面の熱抵抗分布および半導体チップの順方向特性に基づいて、半導体チップのチップ面の全面の温度分布が均一となるように、一方のチップ面の電極に接続される複数のワイヤの熱抵抗の分布を異ならせて配置することを特徴とする。   A fourth semiconductor device (corresponding to claim 4) is provided with electrodes on the front and back chip surfaces of a semiconductor chip, and a current flows between an electrode on one chip surface and an electrode on the other chip surface during an ON operation. A plurality of wires are connected to the electrode on one chip surface of the semiconductor chip in a uniform arrangement distribution, and the chip surface of the semiconductor chip is based on the thermal resistance distribution on the chip surface and the forward characteristics of the semiconductor chip. The plurality of wires connected to the electrodes on one chip surface are arranged with different thermal resistance distributions so that the temperature distribution on the entire surface of the chip is uniform.

第１の半導体装置の製造方法（請求項５に対応）は、半導体チップの一方のチップ面の電極に均一な配置で接続された複数のワイヤと、半導体チップの他方のチップ面の電極との間に、所定の電力条件で通電を行ったときの半導体チップのチップ面の温度分布を計測する第１のステップと、半導体チップのチップ面を少なくとも２つの区画に分ける第２のステップと、温度分布と所定の電力条件の値に基づいて区画ごとの熱抵抗分布を求める第３のステップと、熱抵抗分布と半導体チップの順方向特性に基づいて、半導体チップの温度分布が均一になるように区画単位のワイヤ抵抗値を求める第４のステップと、ワイヤ抵抗値と一致するように区画に接続されるワイヤの実装条件を決定する第５のステップと、を有する方法である。   According to a first method of manufacturing a semiconductor device (corresponding to claim 5), a plurality of wires connected in a uniform arrangement to an electrode on one chip surface of a semiconductor chip and an electrode on the other chip surface of the semiconductor chip In between, a first step of measuring the temperature distribution of the chip surface of the semiconductor chip when energized under a predetermined power condition, a second step of dividing the chip surface of the semiconductor chip into at least two sections, and a temperature Third step of obtaining a thermal resistance distribution for each section based on the distribution and a value of a predetermined power condition, and based on the thermal resistance distribution and the forward characteristics of the semiconductor chip, so that the temperature distribution of the semiconductor chip becomes uniform This is a method including a fourth step of obtaining a wire resistance value for each section and a fifth step of determining a mounting condition of a wire connected to the section so as to coincide with the wire resistance value.

第２の半導体装置の製造方法（請求項６に対応）は、上記の方法において、好ましくは、ワイヤの実装条件はワイヤの本数または断面積であること特徴づけられる。   The second method for manufacturing a semiconductor device (corresponding to claim 6) is characterized in that, in the above method, the wire mounting condition is preferably the number of wires or a cross-sectional area.

第３の半導体装置の製造方法（請求項７に対応）は、上記の方法において、区画に接続されるワイヤの実装条件を決定する第５のステップの代わりに、ワイヤ抵抗値と一致するように電子線照射によって区画のいずれかに対応する半導体チップの順方向特性を変更するステップを設けたことで特徴づけられる。   A third method for manufacturing a semiconductor device (corresponding to claim 7) is the above-described method, wherein, instead of the fifth step of determining the mounting condition of the wire connected to the section, the wire resistance value is matched. It is characterized by providing a step of changing the forward characteristic of the semiconductor chip corresponding to one of the sections by electron beam irradiation.

第４の半導体装置の製造方法（請求項８に対応）は、上記の方法において、好ましくは、少なくとも２つの区画は、チップ面の中央部と周辺部であることで特徴づけられる。   A fourth method for manufacturing a semiconductor device (corresponding to claim 8) is characterized in that, in the above method, preferably, at least two sections are a central portion and a peripheral portion of a chip surface.

第５の半導体装置の製造方法（請求項９に対応）は、上記の方法において、好ましくは、周辺部のワイヤ本数を中央部のワイヤ本数よりも多くしたことで特徴づけられる。   The fifth method for manufacturing a semiconductor device (corresponding to claim 9) is preferably characterized in that, in the above method, the number of wires in the peripheral portion is larger than the number of wires in the central portion.

第６の半導体装置の製造方法（請求項１０に対応）は、上記の方法において、好ましくは、辺部のワイヤの断面積を中央部のワイヤの断面積よりも大きくしたことで特徴づけられる。   The sixth method for manufacturing a semiconductor device (corresponding to claim 10) is preferably characterized in that, in the above method, the cross-sectional area of the wire in the side portion is made larger than the cross-sectional area of the wire in the central portion.

第７の半導体装置の製造方法（請求項１１に対応）は、上記の方法において、好ましくは、電子線照射によって前記半導体チップにおける前記中央部の順方向特性を前記周辺部の順方向特性よりも高くしたことで特徴づけられる。   According to a seventh method for manufacturing a semiconductor device (corresponding to claim 11), in the above method, preferably, the forward characteristic of the central portion of the semiconductor chip is made to be higher than the forward characteristic of the peripheral portion by electron beam irradiation. Characterized by the increase.

本発明によれば、次の効果を奏する。
本発明に係る半導体装置によれば、半導体装置に含まれる半導体チップのチップに接続される複数のワイヤの実装を、事前に得た温度分布情報に基づいてチップ面での最適な抵抗バランスを求め、チップ面の中央部と周辺部とでワイヤの条件を変えてチップ面における最適な抵抗バランスを実現するようにしたため、半導体チップの温度分布をチップ面内で均一にすることができ、通常では高温となる傾向のあるチップ中央部でのワイヤの剥離や劣化を低減することができ、半導体装置の寿命を長くし、半導体装置の性能を向上することができる。
本発明に係る半導体装置の製造方法によれば、パワー半導体装置の半導体チップへの通電用ワイヤの実装でチップ面の温度分布を最適にすることができ、ワイヤの剥離・劣化が少なく、寿命の長いパワー半導体装置を製造することができる。 The present invention has the following effects.
According to the semiconductor device of the present invention, the mounting of the plurality of wires connected to the chip of the semiconductor chip included in the semiconductor device is obtained based on the temperature distribution information obtained in advance and the optimum resistance balance on the chip surface is obtained. Because the optimal resistance balance on the chip surface is realized by changing the wire conditions at the center and the peripheral part of the chip surface, the temperature distribution of the semiconductor chip can be made uniform in the chip surface. Wire peeling and deterioration at the center of the chip, which tends to be high, can be reduced, the life of the semiconductor device can be extended, and the performance of the semiconductor device can be improved.
According to the method for manufacturing a semiconductor device according to the present invention, the temperature distribution on the chip surface can be optimized by mounting the current-carrying wire on the semiconductor chip of the power semiconductor device, the wire peeling / deterioration is small, and the lifetime is reduced. A long power semiconductor device can be manufactured.

以下に、本発明の好適な実施形態（実施例）を添付図面に基づいて説明する。   DESCRIPTION OF EMBODIMENTS Preferred embodiments (examples) of the present invention will be described below with reference to the accompanying drawings.

図１〜図３を参照して本発明に係る半導体装置の実施形態について説明する。この半導体装置はパワー半導体装置である。図１は本実施形態に係る半導体装置の簡略的な斜視図を示し、図２はＩＧＢＴ素子の平面図を示し、図３はＩＧＢＴ素子の実装部分の縦断面図を示す。図３において、厚み方向の寸法は説明の便宜上誇張して拡大して描いており、実際のものとは異なっている。   An embodiment of a semiconductor device according to the present invention will be described with reference to FIGS. This semiconductor device is a power semiconductor device. FIG. 1 is a simplified perspective view of a semiconductor device according to the present embodiment, FIG. 2 is a plan view of an IGBT element, and FIG. 3 is a longitudinal sectional view of a mounting portion of the IGBT element. In FIG. 3, the dimension in the thickness direction is exaggerated and drawn for convenience of explanation, and is different from the actual one.

例えば自動車に搭載されるパワー半導体装置はモジュール化されて構成されている。自動車に搭載されたモータを駆動するためのインバータ装置に用いられるブリッジ回路は、１つの例えばＩＧＢＴ素子と１つのダイオード素子から成る電気回路を単位回路として構成される。この単位回路は、ブリッジ回路のハイサイド（高圧側）とローサイド（低圧側）のそれぞれに設けられる。ハイサイドおよびローサイドの上記単位回路によってパワー半導体モジュールが形成される。   For example, a power semiconductor device mounted on an automobile is configured as a module. A bridge circuit used in an inverter device for driving a motor mounted on an automobile includes an electric circuit including, for example, one IGBT element and one diode element as a unit circuit. This unit circuit is provided on each of the high side (high voltage side) and the low side (low voltage side) of the bridge circuit. A power semiconductor module is formed by the unit circuits on the high side and the low side.

図１は、モジュール化された半導体装置１０を示している。半導体装置１０は２つの構成部分１０Ａ，１０Ｂを備えている。２つの構成部分１０Ａ，１０Ｂの各々は、単位回路として構成されており、ＩＧＢＴ素子１１とダイオード素子１２が基板部１３上に配置されている。２つの構成部分１０Ａ，１０Ｂの各々も実質的には１つの半導体装置として構成されている。半導体装置１０の全体のイメージは二点鎖線で示されている。半導体装置１０のケースや樹脂モールド部分の図示は省略している。基板部１３は、後述するようにさらに複数の各種の基板から形成されている。基板部１３上には少なくとも１つの電極１４が設けられ、これらの電極１４とＩＧＢＴ素子１１とダイオード素子１２とその他の図示しない電極との間は、多数のワイヤ１５により接続されている。図１に示されたワイヤ接続のレイアウトは図示のための便宜上の一例であり、簡素化して示されている。上記のＩＧＢＴ素子１１とダイオード素子１２はそれぞれ半導体チップを成している。   FIG. 1 shows a modularized semiconductor device 10. The semiconductor device 10 includes two components 10A and 10B. Each of the two components 10A and 10B is configured as a unit circuit, and the IGBT element 11 and the diode element 12 are arranged on the substrate portion 13. Each of the two components 10A and 10B is also substantially configured as one semiconductor device. An overall image of the semiconductor device 10 is indicated by a two-dot chain line. Illustration of the case and the resin mold part of the semiconductor device 10 is omitted. As will be described later, the substrate section 13 is further formed of a plurality of various substrates. At least one electrode 14 is provided on the substrate portion 13, and these electrodes 14, the IGBT element 11, the diode element 12, and other electrodes (not shown) are connected by a number of wires 15. The wire connection layout shown in FIG. 1 is an example for convenience of illustration, and is shown in a simplified manner. Each of the IGBT element 11 and the diode element 12 constitutes a semiconductor chip.

上記ＩＧＢＴ素子１１は、図１において上側（表側）と下側（裏側）と間でチップの厚み方向に通電が行われる構造となっている。本実施形態に係るＩＧＢＴ素子１１は縦型ＤＭＯＳ構造を有し、ＩＧＢＴ素子１１のチップ全体は横方向にて複数のチップ要素に分割されている。そのためＩＧＢＴ素子１１の表裏のチップ面では、複数のチップ要素に基づいて分割された面が形成されている。   The IGBT element 11 has a structure in which energization is performed in the thickness direction of the chip between the upper side (front side) and the lower side (back side) in FIG. The IGBT element 11 according to this embodiment has a vertical DMOS structure, and the whole chip of the IGBT element 11 is divided into a plurality of chip elements in the horizontal direction. Therefore, the front and back chip surfaces of the IGBT element 11 are formed with surfaces divided based on a plurality of chip elements.

ＩＧＢＴ素子１１は、エミッタ、コレクタ、ゲートの３つの電極を備えている。ＩＧＢＴ素子１１では、ゲートに印加される電圧に応じてエミッタ・コレクタの間に電流が流れる。図１に示されたＩＧＢＴ素子１１において、上側のチップ面（表面）にはエミッタ電極が設けられ、下側のチップ面（裏面）にはコレクタ電極が設けられている。また上側のチップ面には、上記のエミッタ電極と共に、ゲート電極も設けられている。   The IGBT element 11 includes three electrodes: an emitter, a collector, and a gate. In the IGBT element 11, a current flows between the emitter and the collector in accordance with the voltage applied to the gate. In the IGBT element 11 shown in FIG. 1, an emitter electrode is provided on the upper chip surface (front surface), and a collector electrode is provided on the lower chip surface (back surface). In addition to the emitter electrode, a gate electrode is provided on the upper chip surface.

図２にＩＧＢＴ素子１１の平面図を示す。ＩＧＢＴ素子１１はほぼ正方形の矩形チップ面を有している。ＩＧＢＴ素子１１の上側のチップ面上には、例えば１つのゲート電極２１と、例えば６つのエミッタ電極２２−１〜２２−６とが、形成されている。ＩＧＢＴ素子におけるエミッタ電極は本来的に１つの概念であるが、この実施形態に係る半導体装置１０のＩＧＢＴ素子１１のエミッタ電極では、ＩＧＢＴ素子１１のエミッタ電極を設けるべき箇所を６つの箇所の区画し、６つの領域のそれぞれにエミッタ電極２２−１〜２２−６を設けている。   FIG. 2 shows a plan view of the IGBT element 11. The IGBT element 11 has a substantially square rectangular chip surface. On the chip surface on the upper side of the IGBT element 11, for example, one gate electrode 21 and, for example, six emitter electrodes 22-1 to 22-6 are formed. The emitter electrode in the IGBT element is originally one concept, but in the emitter electrode of the IGBT element 11 of the semiconductor device 10 according to this embodiment, the place where the emitter electrode of the IGBT element 11 is to be provided is divided into six parts. , Emitter electrodes 22-1 to 22-6 are provided in each of the six regions.

前述のごとく縦型ＤＭＯＳ構造を有しかつチップ全体が複数のチップ要素に分割されたＩＧＢＴ素子１１では、矩形のチップ面のほぼ全体にわたって均一に分布して形成されたチップ要素のうち適宜な数のチップ要素を、６つのエミッタ電極２２−１〜２２−６のそれぞれに対応させて接続するようにしている。   As described above, in the IGBT element 11 having the vertical DMOS structure and the entire chip divided into a plurality of chip elements, an appropriate number of chip elements formed uniformly distributed over substantially the entire rectangular chip surface. These chip elements are connected to correspond to each of the six emitter electrodes 22-1 to 22-6.

ＩＧＢＴ素子１１の上側のチップ面に接続される前述した複数のワイヤ１５は、ゲート電極２１に接続されるワイヤと、６つのエミッタ電極２２−１〜２２−６に接続されるワイヤを含む。これらのワイヤ１５はワイヤボンディングによって対応する各電極に接続されている。この中で６つのエミッタ電極２２−１〜２２−６のそれぞれに接続されるワイヤ１５は、ＩＧＢＴ素子１１に通電用の電流を流すための電流路を形成している。本実施形態に係る半導体装置１０によれば、６つのエミッタ電極２２−１〜２２−６のそれぞれに接続される複数のワイヤ１５の実装のレイアウトに関して、後述するごとき所定の不均一配置の配線の仕方を採用したり、あるいはワイヤの断面積を接続場所に応じて相違させる等している。すなわち、チップ面上のエミッタ電極が占める面積領域における複数のワイヤ１５の接続レイアウトに関して、後述する条件を満たす基準に基づいて、所要の不均一性を与える構造を採用するようにした。   The plurality of wires 15 described above connected to the chip surface on the upper side of the IGBT element 11 include wires connected to the gate electrode 21 and wires connected to the six emitter electrodes 22-1 to 22-6. These wires 15 are connected to corresponding electrodes by wire bonding. Among these, the wire 15 connected to each of the six emitter electrodes 22-1 to 22-6 forms a current path for flowing a current for energization to the IGBT element 11. According to the semiconductor device 10 according to the present embodiment, with respect to the mounting layout of the plurality of wires 15 connected to each of the six emitter electrodes 22-1 to 22-6, the wiring of a predetermined non-uniformly arranged wiring as will be described later. The method is adopted, or the cross-sectional area of the wire is made different depending on the connection location. In other words, the connection layout of the plurality of wires 15 in the area occupied by the emitter electrode on the chip surface is configured to give a required non-uniformity based on criteria that satisfy the conditions described later.

図３に従って半導体装置１０のＩＧＢＴ素子１１の実装部分の縦断面構造を説明する。ＩＧＢＴ素子１１のチップは、ＡｌＮ（窒化アルミニウム）基板３１の上のＡｌ（アルミニウム）パターン３２上に実装されている。ＩＧＢＴ素子１１はダイボンディングによりＡｌパターン３２の上面に接合されている。符号３３で示された層は基板部１３上に形成された前述した電極１４の１つであり、この電極３３もＡｌパターンとして形成される。上記のＡｌＮ基板３１はハンダ３４によってベース部材３５に接合されている。ベース部材３５は銅で作られている。この銅ベース部材３５はサーマルコンパウンド３６を介してヒートシンク３７に接合されている。ヒートシンク３７はアルミニウムで作られており、その外側下面にはフィンが形成されている。サーマルコンパウンド３６は、ベース部材３５とヒートシンク３７との間の熱結合を均一化しかつ当該熱結合を高めるための熱伝導剤である。   A vertical cross-sectional structure of the mounting portion of the IGBT element 11 of the semiconductor device 10 will be described with reference to FIG. The chip of the IGBT element 11 is mounted on an Al (aluminum) pattern 32 on an AlN (aluminum nitride) substrate 31. The IGBT element 11 is bonded to the upper surface of the Al pattern 32 by die bonding. A layer indicated by reference numeral 33 is one of the electrodes 14 formed on the substrate portion 13, and this electrode 33 is also formed as an Al pattern. The AlN substrate 31 is joined to the base member 35 by solder 34. The base member 35 is made of copper. The copper base member 35 is joined to a heat sink 37 via a thermal compound 36. The heat sink 37 is made of aluminum, and fins are formed on the outer lower surface thereof. The thermal compound 36 is a thermal conductive agent for making the thermal coupling between the base member 35 and the heat sink 37 uniform and enhancing the thermal coupling.

上記の構造において、ＩＧＢＴ素子１１の上面（エミッタ電極等）と電極３３との間には複数のワイヤ１５が配線されている。ＩＧＢＴ素子１１のエミッタ電極２２−１〜２２−６には、通電時には電極３３およびワイヤ１５を経由して通電用の電流が供給されことになる。   In the above structure, a plurality of wires 15 are wired between the upper surface (emitter electrode or the like) of the IGBT element 11 and the electrode 33. A current for energization is supplied to the emitter electrodes 22-1 to 22-6 of the IGBT element 11 via the electrode 33 and the wire 15 when energized.

次に、本実施形態に係る半導体装置１０の特徴的構成を説明する。半導体装置１０の特徴的構成は、ＩＧＢＴ素子１１のエミッタ電極２２−１〜２２−６に接続される複数のワイヤ１５の通電時の発熱に起因する温度分布をチップ面の全体にわたって均一にするため、反対に、エミッタ電極２２−１〜２２−６に接続される複数のワイヤ１５の接続の仕方に関して所要の不均一性を与えるようにした点にある。   Next, a characteristic configuration of the semiconductor device 10 according to the present embodiment will be described. The characteristic configuration of the semiconductor device 10 is to make the temperature distribution due to heat generated when energizing the plurality of wires 15 connected to the emitter electrodes 22-1 to 22-6 of the IGBT element 11 uniform over the entire chip surface. On the contrary, a required non-uniformity is provided with respect to the connection method of the plurality of wires 15 connected to the emitter electrodes 22-1 to 22-6.

まず、ワイヤ１５の上記不均一性を説明する前に、半導体装置１０のＩＧＢＴ素子１１における複数のワイヤ１５を実装するための手順を説明する。図４にワイヤ実装のための手順をフローチャート形式にて示す。   First, a procedure for mounting the plurality of wires 15 in the IGBT element 11 of the semiconductor device 10 will be described before describing the non-uniformity of the wires 15. FIG. 4 shows a procedure for wire mounting in the form of a flowchart.

このワイヤ実装では、ＩＧＢＴ素子１１のチップ面におけるワイヤの接続レイアウトについて所要の不均一性を与える。そのために、最初のステップＳ１（温度分布の観察）で、ＩＧＢＴ素子１１においてそのエミッタ電極（２２−１〜２２−６）の全占有面積上で複数のワイヤを均一配置で接続して実装した場合の通電時の温度分布（発熱分布）の情報を計測によって取得する。「ワイヤの均一配置での実装」とは、同一のワイヤを均等な間隔でエミッタ電極２２−１〜２２−６の全体の占有面積上に配置することを意味している。ＩＧＢＴ素子１１のチップ面における温度分布情報を得るための計測では、計測装置としてサーモビュアが使用される。取得された温度分布の情報は、ＩＧＢＴ素子１１のチップ面における温度分布の状態である。ＩＧＢＴ素子１１のエミッタ電極２２−１〜２２−６におけるワイヤの均一配置実装においてワイヤへの通電条件は例えば２２５［Ａ］および２．２２［Ｖ］である。ＩＧＢＴ素子１１のチップ面における温度分布（発熱分布）は計測装置の表示画面に表示される。表示画面に示されたチップ面上の温度分布は色彩で表現される。   In this wire mounting, the required non-uniformity is given to the connection layout of the wires on the chip surface of the IGBT element 11. Therefore, in the first step S1 (observation of temperature distribution), a plurality of wires are mounted in a uniform arrangement on the entire occupied area of the emitter electrodes (22-1 to 22-6) in the IGBT element 11 and mounted. Information of temperature distribution (heat generation distribution) during energization of is acquired by measurement. “Mounting with uniform wire arrangement” means that the same wires are arranged on the entire occupied area of the emitter electrodes 22-1 to 22-6 at equal intervals. In the measurement for obtaining temperature distribution information on the chip surface of the IGBT element 11, a thermoviewer is used as a measurement device. The acquired temperature distribution information is the state of the temperature distribution on the chip surface of the IGBT element 11. In the uniform arrangement mounting of the wires in the emitter electrodes 22-1 to 22-6 of the IGBT element 11, the energization conditions to the wires are, for example, 225 [A] and 2.22 [V]. The temperature distribution (heat generation distribution) on the chip surface of the IGBT element 11 is displayed on the display screen of the measuring device. The temperature distribution on the chip surface shown on the display screen is expressed in color.

次のステップＳ２（熱抵抗の算出）では、ステップＳ１で得られたＩＧＢＴ素子１１のチップ面についての温度分布に基づいて、チップ面内のミクロな熱抵抗を例えば中央部と周辺部（または外周部）の各々で算出する。チップ面内のミクロな熱抵抗の計算は、チップ面の場所ごとのジャンクション温度（接合温度）に基づいて熱抵抗を算出するようにしている。チップ面における場所は適宜に選択することができる。この実施形態では、ＩＧＢＴ素子１１のチップ面の中央部の熱抵抗値と周辺部の熱抵抗値を算出する。   In the next step S2 (calculation of thermal resistance), based on the temperature distribution on the chip surface of the IGBT element 11 obtained in step S1, the micro thermal resistance in the chip surface is determined, for example, at the central portion and the peripheral portion (or the outer periphery). Part). In the calculation of the micro thermal resistance in the chip surface, the thermal resistance is calculated based on the junction temperature (bonding temperature) for each location on the chip surface. The location on the chip surface can be selected as appropriate. In this embodiment, the thermal resistance value of the center part of the chip surface of the IGBT element 11 and the thermal resistance value of the peripheral part are calculated.

熱抵抗の値の一例を述べる。中央部の温度を１４５℃かつ室温を２５℃とすると、中央部の熱抵抗の値は（１４５−２５）［℃］／（２２５×２．２２）［Ｗ］＝０．２４［℃／Ｗ］となる。また同様にして、周辺部の熱抵抗の値は、周辺部の温度を１１５℃とするとき、（１１５−２５）［℃］／（２２５×２．２２）［Ｗ］＝０．１９［℃／Ｗ］となる。   An example of the value of thermal resistance will be described. Assuming that the temperature at the center is 145 ° C. and the room temperature is 25 ° C., the value of the thermal resistance at the center is (145-25) [° C.] / (225 × 2.22) [W] = 0.24 [° C./W ]. Similarly, the value of the thermal resistance of the peripheral portion is (115-25) [° C.] / (225 × 2.22) [W] = 0.19 [° C. when the temperature of the peripheral portion is 115 ° C. / W].

なお、上記において、チップ面で設定される区画は中央部と周辺部に限定されず、２より多い複数の区画とすることもできる。   In the above, the sections set on the chip surface are not limited to the central part and the peripheral part, and may be a plurality of more than two sections.

次のステップＳ３（ジャンクション温度の一致化条件の算出）では、ステップＳ２で得られた異なる中央部の熱抵抗値と周辺部の熱抵抗値とに基づいて、両者の熱抵抗値が実質的に一致するような中央部が負担すべき電力と周辺部が負担すべき電力とを算出する。中央部の電力と周辺部の電力は、それぞれ、ＩＧＢＴ素子１１のチップ実装状態を含めた当該ＩＧＢＴ素子１１の順方向特性から求められる。この計算を、図５のグラフを参照して説明する。   In the next step S3 (calculation of the matching condition of the junction temperature), based on the different thermal resistance values in the central part and the peripheral thermal resistance values obtained in step S2, the thermal resistance values of both are substantially equal. The power that should be borne by the central part and the power that should be borne by the peripheral part are calculated. The electric power in the central part and the electric power in the peripheral part are respectively obtained from the forward characteristics of the IGBT element 11 including the chip mounting state of the IGBT element 11. This calculation will be described with reference to the graph of FIG.

図５の座標系について、横軸はコレクタ・エミッタ電圧（Ｖｃｅ）を示し、縦軸はコレクタ・エミッタ電流（Ｉｃｅ）を示す。従って図５に示した特性グラフ４１は、ＩＧＢＴ素子１１のコレクタ・エミッタ間のＶ−Ｉ特性を示している。この特性グラフ４１は前述したＩＧＢＴ素子１１の順方向特性を表している。当該特性グラフ４１において、仮に中央部の状態を示す点がＰ１であるとき、その電力は１００［Ａ］×１．７［Ｖ］＝１７０［Ｗ］となる。そこで、次には、中央部と周辺部の熱抵抗値の比（０．２４／０．１９）を利用して、中央部の電力１７０［Ｗ］に対応する電力を、１７０×（０．２４／０．１９）の式に従って求めると、２１５［Ｗ］になる。この電力２１５［Ｗ］に対応する点を特性グラフ４１の上で探す。その結果、１２０［Ａ］×１．８［Ｖ］＝２１６［Ｗ］により、特性グラフ４１上で点Ｐ２が求められる。結果的に、ＩＧＢＴ素子１１のチップ面で温度分布（発熱分布）で均一性を生じさせるようにするためには、中央部での電流が１００Ａである場合には、周辺部の電流は１２０Ａであることが望ましいということが判明する。その結果、ＩＧＢＴ素子１１のエミッタ電極２２−１〜２２−６の面上に複数の通電用ワイヤ１５を実装する場合において、当該ワイヤに関する実装の抵抗バランスを、中央部の抵抗値をＲｃ、周辺部の抵抗値をＲｐとするとき、Ｒｃ：Ｒｐ＝１００：１２０という関係式による条件を満たすように設定する。これにより、ＩＧＢＴ素子１１のチップ面において中央部に流れる電流を少なくし、かつ周辺部に流れる電流を多くするように、複数のワイヤ１５の実装に関する抵抗バランスを設定する。この抵抗バランスによって、ワイヤ１５によるジャンクション温度が中央部と周辺部でほぼ同一となり、チップ面におけるワイヤ１５による温度分布を均一にすることが可能となる。   In the coordinate system of FIG. 5, the horizontal axis indicates the collector-emitter voltage (Vce), and the vertical axis indicates the collector-emitter current (Ice). Therefore, the characteristic graph 41 shown in FIG. 5 shows the VI characteristic between the collector and the emitter of the IGBT element 11. This characteristic graph 41 represents the forward characteristic of the IGBT element 11 described above. In the characteristic graph 41, if the point indicating the state of the central part is P1, the power is 100 [A] × 1.7 [V] = 170 [W]. Therefore, next, the power corresponding to the power 170 [W] in the central portion is set to 170 × (0. 24 / 0.19), it is 215 [W]. A point corresponding to the power 215 [W] is searched on the characteristic graph 41. As a result, the point P2 is obtained on the characteristic graph 41 by 120 [A] × 1.8 [V] = 216 [W]. As a result, in order to produce uniformity in the temperature distribution (heat generation distribution) on the chip surface of the IGBT element 11, when the current at the center is 100A, the current at the periphery is 120A. It turns out to be desirable. As a result, when a plurality of energizing wires 15 are mounted on the surfaces of the emitter electrodes 22-1 to 22-6 of the IGBT element 11, the resistance balance of the mounting related to the wires is expressed as Rc, When the resistance value of the part is Rp, the condition is set so as to satisfy the relational expression Rc: Rp = 100: 120. As a result, the resistance balance related to the mounting of the plurality of wires 15 is set so that the current flowing in the central portion on the chip surface of the IGBT element 11 is reduced and the current flowing in the peripheral portion is increased. By this resistance balance, the junction temperature due to the wire 15 becomes substantially the same at the central portion and the peripheral portion, and the temperature distribution due to the wire 15 on the chip surface can be made uniform.

最後のステップＳ４（抵抗バランスに基づくワイヤの実装）では、半導体装置１０におけるＩＧＢＴ素子１１のエミッタ電極２２−１〜２２−６上に複数のワイヤ１５を実装するにあたり、前述した実装条件（ジャンクション温度が同一になる条件）を満たすように実装を行う。このワイヤ１５の実装は、好ましくは、エミッタ電極２２−１〜２２−６において中央部と周辺部の間で、接続するワイヤ本数を変えたり、ワイヤ断面積を変えたりする。またワイヤの実装の代わりに、抵抗バランスに従って、ＩＧＢＴ素子１１のエミッタ電極側のチップ面の順方向特性を電子線照射によって変更させることもできる。この場合、ＩＧＢＴ素子１１の順方向特性について、チップ面の中央部の順方向特性を周辺部の順方向特性に比較して高くするようにする。すなわち、同一の印加電圧に対して中央部の通電量が周辺部の通電量に比して少なくなるように順方向特性を適切に調整する。なお「電子線照射」は、電離作用で生じた放射線を処理・加工対象物に対して照射するもので、電離作用等に基づき対象物の物性的特質を改変することができる処理技術である。   In the final step S4 (wire mounting based on the resistance balance), the mounting conditions (junction temperature) described above are required for mounting the plurality of wires 15 on the emitter electrodes 22-1 to 22-6 of the IGBT element 11 in the semiconductor device 10. Implementation is performed so as to satisfy the same condition). The wire 15 is preferably mounted by changing the number of wires to be connected or changing the wire cross-sectional area between the central portion and the peripheral portion in the emitter electrodes 22-1 to 22-6. Further, instead of mounting wires, the forward characteristics of the chip surface on the emitter electrode side of the IGBT element 11 can be changed by electron beam irradiation in accordance with the resistance balance. In this case, with respect to the forward characteristic of the IGBT element 11, the forward characteristic at the center of the chip surface is made higher than the forward characteristic at the peripheral part. In other words, the forward characteristics are appropriately adjusted so that the energization amount at the central portion is smaller than the energization amount at the peripheral portion with respect to the same applied voltage. Note that “electron beam irradiation” is a processing technique that irradiates the object to be processed / processed with radiation generated by the ionization action, and can modify the physical properties of the object based on the ionization action or the like.

図６と図７を参照して具体的なワイヤ実装等の例を示す。   Specific examples of wire mounting and the like will be described with reference to FIGS.

図６はＩＧＢＴ素子に関して３つの平面図（Ａ），（Ｂ），（Ｃ）を示している。図６の（Ａ）は従来方式のワイヤ実装の例を示し、（Ｂ）と（Ｃ）は本実施形態によるワイヤ実装の例を示している。図６の（Ａ）は、本実施形態に係る実装例である（Ｂ）および（Ｃ）と対比させるために図示されたものである。   FIG. 6 shows three plan views (A), (B), and (C) regarding the IGBT element. 6A shows an example of conventional wire mounting, and FIGS. 6B and 6C show an example of wire mounting according to the present embodiment. FIG. 6A is shown for comparison with FIGS. 6B and 7C which are mounting examples according to the present embodiment.

図６の（Ａ）によれば、ＩＧＢＴ素子１１の上側のチップ面におけるエミッタ電極２２−１〜２２−６の全面積部分に対して均一のレイアウト（配置または配列）で同一の複数のワイヤ１５が接続されている。すなわち、６つのエミッタ電極２２−１〜２２−６から成るエミッタ電極のチップ面上の占有面積領域において均等な間隔で偏りのない状態で配置されている。   According to FIG. 6A, the same wires 15 are arranged in a uniform layout (arrangement or arrangement) over the entire area of the emitter electrodes 22-1 to 22-6 on the upper chip surface of the IGBT element 11. Is connected. That is, the emitter electrode composed of the six emitter electrodes 22-1 to 22-6 is arranged at an even interval in the occupied area region on the chip surface without any deviation.

上記のワイヤ実装に対して、図６の（Ｂ）に示した本実施形態に係るワイヤ実装の第１の例によれば、同一の複数のワイヤ１５の接続で、中央部５１のワイヤ本数に対して周辺部５２のワイヤ本数を増した状態でワイヤが接続されている。すなわち、ＩＧＢＴ素子１１の周辺部５２に接続されるワイヤの本数が中央部５１に接続されるワイヤの本数よりも多くなるように実装されている。この図示例では、一例として、中央部５１のワイヤ１５の本数が１２であるのに対して、周辺部５２のワイヤ１５の本数は３２となっている。実際上、ワイヤ実装による不均一なレイアウトは、前述のごとく、ステップＳ３で得られた条件に基づいて決定される。このワイヤ実装に基づいて、ＩＧＢＴ素子１１のチップ面の温度分布を、中央部５１と周辺部５２とでほぼ等しくすることができ、チップ面全体で均一にすることができる。   In contrast to the wire mounting described above, according to the first example of wire mounting according to the present embodiment shown in FIG. 6B, the number of wires in the central portion 51 can be increased by connecting the same plurality of wires 15. On the other hand, the wires are connected in a state where the number of wires in the peripheral portion 52 is increased. That is, it is mounted so that the number of wires connected to the peripheral portion 52 of the IGBT element 11 is larger than the number of wires connected to the central portion 51. In the illustrated example, as an example, the number of wires 15 in the central portion 51 is 12, whereas the number of wires 15 in the peripheral portion 52 is 32. In practice, the non-uniform layout due to the wire mounting is determined based on the condition obtained in step S3 as described above. Based on this wire mounting, the temperature distribution on the chip surface of the IGBT element 11 can be made substantially equal between the central portion 51 and the peripheral portion 52, and can be made uniform over the entire chip surface.

また図６の（Ｃ）に示した実施形態に係るワイヤ実装の第２の例によれば、エミッタ電極の面全体でのワイヤ（１５，５３）の接続は均一に配置すると共に、周辺部５２に接続されたワイヤ５３の断面積（または径）を、中央部５１に接続されたワイヤ１５の断面積（または径）よりも大きくしている。中央部５１に接続されたワイヤ１５は、図６の（Ａ）に示した従来方式のワイヤと同じである。周辺部５２に接続されたワイヤ５３は、配置位置および本数は従来方式のワイヤの例と同じであり、断面積が例えばほぼ２倍程度になっている。このワイヤ実装の場合にも、実際上、ワイヤ実装による不均一なレイアウトは、前述のごとく、ステップＳ３で得られた条件に基づいて決定される。このワイヤ実装に基づいて、ＩＧＢＴ素子１１のチップ面の温度分布を、中央部５１と周辺部５２とでほぼ等しくすることができ、チップ面全体で均一にすることができる。   Further, according to the second example of wire mounting according to the embodiment shown in FIG. 6C, the wires (15, 53) are connected uniformly over the entire surface of the emitter electrode and the peripheral portion 52 is arranged. The cross-sectional area (or diameter) of the wire 53 connected to is larger than the cross-sectional area (or diameter) of the wire 15 connected to the central portion 51. The wire 15 connected to the central portion 51 is the same as the conventional wire shown in FIG. The wires 53 connected to the peripheral portion 52 are the same in arrangement position and number as in the conventional wire example, and have a cross-sectional area of about double, for example. Also in the case of this wire mounting, the non-uniform layout due to the wire mounting is actually determined based on the condition obtained in step S3 as described above. Based on this wire mounting, the temperature distribution on the chip surface of the IGBT element 11 can be made substantially equal between the central portion 51 and the peripheral portion 52, and can be made uniform over the entire chip surface.

図７は、ＩＧＢＴ素子１１の平面図を示し、ＩＧＢＴ素子１１のエミッタ電極側のチップ面の順方向特性を電子線照射によって変更させる例を示している。この図示例では、ＩＧＢＴ素子１１の順方向特性について、チップ面の中央部５１の順方向特性を周辺部５２の順方向特性に比較して高くするようにしている。ワイヤ１５の配列は均一な配列となっており、従来方式のワイヤ実装と同じである。   FIG. 7 shows a plan view of the IGBT element 11 and shows an example in which the forward characteristic of the chip surface on the emitter electrode side of the IGBT element 11 is changed by electron beam irradiation. In this illustrated example, the forward characteristics of the IGBT element 11 are set so that the forward characteristics of the center portion 51 of the chip surface are higher than the forward characteristics of the peripheral portion 52. The arrangement of the wires 15 is a uniform arrangement, which is the same as the conventional wire mounting.

なお上記では、半導体装置１０においてＩＧＢＴ素子１１のワイヤ実装の例のみを説明したが、パワー半導体素子としてのダイオード素子１２についても必要に応じて同様なワイヤ実装を行うことができる。さらに、その他のパワー半導体装置に含まれる半導体チップ一般に本実施形態に係るワイヤ実装を適用することができる。   In the above description, only the example of the wire mounting of the IGBT element 11 in the semiconductor device 10 has been described. However, the same wire mounting can be performed on the diode element 12 as the power semiconductor element as necessary. Furthermore, the semiconductor chip included in other power semiconductor devices generally can be applied to the wire mounting according to the present embodiment.

前述した半導体装置１０の製造方法を概説する。この製造方法は、工程順の述べると、（１）ダイボンディング工程、（２）ケーシング工程、（３）ワイヤボンド工程、（４）シリコンゲル・ポッティング工程、（５）ゲートドライバ／絶縁フィルムコネクタ取付け工程、（６）検査工程、（７）ヒートシンク取付け工程、（８）エージング工程から構成されている。   A method for manufacturing the semiconductor device 10 described above will be outlined. This manufacturing method is described in the order of processes: (1) die bonding process, (2) casing process, (3) wire bonding process, (4) silicon gel potting process, (5) gate driver / insulating film connector attachment The process includes (6) an inspection process, (7) a heat sink attachment process, and (8) an aging process.

ダイボンディング工程は、半導体チップ（ＩＧＢＴ素子１１およびダイオード素子１２）を、予め用意された基板部にハンダ付けする工程である。これにより単位装置の半導体装置１０が作られる。   The die bonding step is a step of soldering the semiconductor chip (IGBT element 11 and diode element 12) to a substrate portion prepared in advance. Thereby, the semiconductor device 10 of the unit device is manufactured.

ケーシング工程は、上記の半導体装置１０を例えば２つ用意し、さらに別途に適宜形状のケースを用意し、２つの半導体装置１０を所定の配置関係によってケースに収納し、接着剤で接着し、かつ接着剤を硬化させる工程である。   In the casing process, for example, two semiconductor devices 10 are prepared, and a case having an appropriate shape is prepared separately. The two semiconductor devices 10 are accommodated in a case according to a predetermined arrangement relationship, and bonded with an adhesive. This is a step of curing the adhesive.

ワイヤボンド工程では、半導体装置１０に含まれるＩＧＢＴ素子のエミッタ電極およびゲート電極と、ダイオード素子の電極と、その他の電極部分との間を、複数のワイヤで接続する。このとき、ＩＧＢＴ素子等のエミッタ電極に複数のワイヤを接続するワイヤ実装では、前述した通りの特徴的な実装が行われる。   In the wire bonding step, the emitter electrode and gate electrode of the IGBT element, the electrode of the diode element, and other electrode portions included in the semiconductor device 10 are connected by a plurality of wires. At this time, characteristic mounting as described above is performed in wire mounting in which a plurality of wires are connected to an emitter electrode such as an IGBT element.

シリコンゲル・ポッティング工程では、ワイヤが配置される空間部に対してシリコンゲルが充填され、当該シリコンゲルは硬化される。   In the silicon gel potting process, the silicon gel is filled in the space where the wire is placed, and the silicon gel is cured.

ゲートドライバ／絶縁フィルムコネクタ取付け工程では、硬化したシリコンゲル部分の露出面に対してゲートドライバが取り付けられ、さらにその上に絶縁フィルムコネクタが取り付けられる。   In the gate driver / insulating film connector attaching step, the gate driver is attached to the exposed surface of the cured silicon gel portion, and the insulating film connector is further attached thereon.

検査工程は、組み立てられた半導体装置の電気的特性を検査する工程である。   The inspection step is a step of inspecting the electrical characteristics of the assembled semiconductor device.

ヒートシンク取付け工程は、熱伝導剤を介在させて、半導体装置を含むケースの全体をヒートシンクに取り付ける工程である。   The heat sink attachment step is a step of attaching the entire case including the semiconductor device to the heat sink with a thermal conductive agent interposed.

エージング工程は、製造された半導体装置の全体を高温または低温で連続して運転する工程である。   The aging process is a process in which the entire manufactured semiconductor device is continuously operated at a high temperature or a low temperature.

以上の実施形態で説明された構成、形状、大きさおよび配置関係については本発明が理解・実施できる程度に概略的に示したものにすぎず、また数値および各構成の組成（材質）については例示にすぎない。従って本発明は、説明された実施形態に限定されるものではなく、特許請求の範囲に示される技術的思想の範囲を逸脱しない限り様々な形態に変更することができる。   The configurations, shapes, sizes, and arrangement relationships described in the above embodiments are merely shown to the extent that the present invention can be understood and implemented, and the numerical values and the compositions (materials) of the respective configurations are as follows. It is only an example. Therefore, the present invention is not limited to the described embodiments, and can be variously modified without departing from the scope of the technical idea shown in the claims.

本発明は、各種の電気機器および電子機器に利用されるパワー半導体装置に含まれる半導体チップのワイヤ実装に利用される。   The present invention is used for wire mounting of a semiconductor chip included in a power semiconductor device used for various electric devices and electronic devices.

本発明の本実施形態に係る半導体装置の構成の外観例を簡略的に示す斜視図である。It is a perspective view which shows simply the example of the external appearance of the structure of the semiconductor device which concerns on this embodiment of this invention. 本実施形態に係る半導体装置に搭載されたＩＧＢＴ素子の平面図である。It is a top view of the IGBT element mounted in the semiconductor device which concerns on this embodiment. ＩＧＢＴ素子の実装構造を示す縦断面図である。It is a longitudinal cross-sectional view which shows the mounting structure of an IGBT element. 本実施形態に係る半導体装置のＩＧＢＴ素子における複数のワイヤを実装するための手順を説明するためのフローチャートである。It is a flowchart for demonstrating the procedure for mounting the some wire in the IGBT element of the semiconductor device which concerns on this embodiment. ＩＧＢＴ素子のコレクタ・エミッタ間のＶ−Ｉ特性（順方向特性）を示すグラフである。It is a graph which shows the VI characteristic (forward characteristic) between collector-emitters of an IGBT element. ＩＧＢＴ素子に関して従来方式のワイヤ実装の例（Ａ）と本実施形態によるワイヤ実装の例（Ｂ），（Ｃ）とを示す平面図である。It is a top view which shows the example (A) of the wire mounting of a conventional system regarding the IGBT element, and the example (B) and (C) of the wire mounting by this embodiment. ＩＧＢＴ素子のエミッタ電極側のチップ面の順方向特性を電子線照射によって変更させる例を示す平面図である。It is a top view which shows the example which changes the forward direction characteristic of the chip surface by the side of the emitter electrode of an IGBT element by electron beam irradiation.

符号の説明Explanation of symbols

１０ 半導体装置
１１ ＩＧＢＴ素子
１２ ダイオード素子
１３ 基板部
１４ 電極
１５ ワイヤ
２１ ゲート電極
２２−１〜２２−６ エミッタ電極
３１ ＡｌＮ基板
３２ Ａｌパターン
３３ 電極
３４ ベース部材
３５ サーマルコンパウンド
３６ ヒートシンク
５１ 中央部
５２ 周辺部
５３ ワイヤ DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 IGBT element 12 Diode element 13 Substrate part 14 Electrode 15 Wire 21 Gate electrode 22-1 to 22-6 Emitter electrode 31 AlN substrate 32 Al pattern 33 Electrode 34 Base member 35 Thermal compound 36 Heat sink 51 Central part 52 Peripheral part 53 wires

Claims (11)

半導体チップの表裏のチップ面に電極を備え、オン動作時に一方の前記チップ面の前記電極と他方の前記チップ面の前記電極の間で電流が流れる半導体装置において、
前記半導体チップの前記一方のチップ面の前記電極には複数のワイヤが不均一な配置分布で接続され、かつ、所定の基準に基づいて、前記一方のチップ面の周辺部に接続される前記ワイヤの本数は前記一方のチップ面の中央部に接続される前記ワイヤの本数よりも多くされることを特徴とする半導体装置。 In the semiconductor device comprising electrodes on the front and back chip surfaces of the semiconductor chip, and a current flows between the electrode on one of the chip surfaces and the electrode on the other chip surface during an on operation,
A plurality of wires are connected to the electrodes on the one chip surface of the semiconductor chip in a non-uniform arrangement distribution, and the wires are connected to a peripheral portion of the one chip surface based on a predetermined reference The number of wires is larger than the number of wires connected to the central portion of the one chip surface. 半導体チップの表裏のチップ面に電極を備え、オン動作時に一方の前記チップ面の前記電極と他方の前記チップ面の前記電極の間で電流が流れる半導体装置において、
前記半導体チップの前記一方のチップ面の前記電極には複数のワイヤが均一な配置分布で接続され、かつ、所定の基準に基づいて、前記一方のチップ面の周辺部に接続される前記ワイヤの断面積は前記一方のチップ面の中央部に接続される前記ワイヤの断面積よりも大きくされることを特徴とする半導体装置。 In the semiconductor device comprising electrodes on the front and back chip surfaces of the semiconductor chip, and a current flows between the electrode on one of the chip surfaces and the electrode on the other chip surface during an on operation,
A plurality of wires are connected to the electrodes on the one chip surface of the semiconductor chip in a uniform arrangement distribution, and the wires connected to the peripheral portion of the one chip surface based on a predetermined reference A semiconductor device characterized in that a cross-sectional area is made larger than a cross-sectional area of the wire connected to a central portion of the one chip surface. 前記所定の基準は、前記半導体チップの前記チップ面における通電発熱に基づく温度分布が均一になる条件を満たすための基準であることを特徴とする請求項１または２記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the predetermined reference is a reference for satisfying a condition that a temperature distribution based on energization heat generation on the chip surface of the semiconductor chip is uniform. 半導体チップの表裏のチップ面に電極を備え、オン動作時に一方の前記チップ面の前記電極と他方の前記チップ面の前記電極の間で電流が流れる半導体装置において、
前記半導体チップの前記一方のチップ面の前記電極には複数のワイヤが均一な配置分布で接続され、かつ、前記チップ面の熱抵抗分布および前記半導体チップの順方向特性に基づいて、前記半導体チップの前記チップ面の全面の温度分布が均一となるように、前記一方のチップ面の前記電極に接続される複数のワイヤの熱抵抗の分布を異ならせて配置することを特徴とする半導体装置。 In the semiconductor device comprising electrodes on the front and back chip surfaces of the semiconductor chip, and a current flows between the electrode on one of the chip surfaces and the electrode on the other chip surface during an on operation,
A plurality of wires are connected to the electrode on the one chip surface of the semiconductor chip in a uniform arrangement distribution, and the semiconductor chip is based on a thermal resistance distribution on the chip surface and a forward characteristic of the semiconductor chip. A semiconductor device, wherein the plurality of wires connected to the electrodes on the one chip surface are arranged with different thermal resistance distributions so that the temperature distribution on the entire chip surface is uniform. 半導体チップの一方のチップ面の電極に均一な配置で接続された複数のワイヤと、前記半導体チップの他方のチップ面の電極との間に、所定の電力条件で通電を行ったときの前記半導体チップの前記チップ面の温度分布を計測するステップと、
前記半導体チップの前記チップ面を少なくとも２つの区画に分けるステップと、
前記温度分布と前記所定の電力条件の値に基づいて前記区画ごとの熱抵抗分布を求めるステップと、
前記熱抵抗分布と前記半導体チップの順方向特性に基づいて、前記半導体チップの温度分布が均一になるように前記区画単位のワイヤ抵抗値を求めるステップと、
前記ワイヤ抵抗値と一致するように前記区画に接続されるワイヤの実装条件を決定するステップと、
を有することを特徴とする半導体装置の製造方法。 The semiconductor when energized under a predetermined power condition between a plurality of wires connected in a uniform arrangement to electrodes on one chip surface of the semiconductor chip and an electrode on the other chip surface of the semiconductor chip Measuring the temperature distribution of the chip surface of the chip;
Dividing the chip surface of the semiconductor chip into at least two sections;
Obtaining a thermal resistance distribution for each section based on the temperature distribution and the value of the predetermined power condition;
Based on the thermal resistance distribution and the forward characteristics of the semiconductor chip, obtaining the wire resistance value of the partition unit so that the temperature distribution of the semiconductor chip is uniform;
Determining a mounting condition of a wire connected to the section so as to match the wire resistance value;
A method for manufacturing a semiconductor device, comprising: 前記ワイヤの前記実装条件は前記ワイヤの本数または断面積であること特徴とする請求項５記載の半導体装置の製造方法。   6. The method of manufacturing a semiconductor device according to claim 5, wherein the mounting condition of the wires is the number or cross-sectional area of the wires. 前記区画に接続されるワイヤの実装条件を決定する前記ステップの代わりに、前記ワイヤ抵抗値と一致するように電子線照射によって前記区画のいずれかに対応する前記半導体チップの順方向特性を変更するステップを設けたことを特徴とする請求項５記載の半導体装置の製造方法。   Instead of the step of determining the mounting condition of the wire connected to the section, the forward characteristic of the semiconductor chip corresponding to one of the sections is changed by electron beam irradiation so as to match the wire resistance value. 6. The method of manufacturing a semiconductor device according to claim 5, further comprising a step. 前記少なくとも２つの区画は、前記チップ面の中央部と周辺部であることを特徴とする請求項５〜７のいずれか１項に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 5, wherein the at least two sections are a central portion and a peripheral portion of the chip surface. 前記周辺部のワイヤ本数を前記中央部のワイヤ本数よりも多くしたことを特徴とする請求項８記載の半導体装置の製造方法。   9. The method of manufacturing a semiconductor device according to claim 8, wherein the number of wires in the peripheral portion is larger than the number of wires in the central portion. 前記周辺部のワイヤの断面積を前記中央部のワイヤの断面積よりも大きくしたことを特徴とする請求項８記載の半導体装置の製造方法。   9. The method of manufacturing a semiconductor device according to claim 8, wherein a cross-sectional area of the peripheral wire is larger than a cross-sectional area of the central wire. 電子線照射によって前記半導体チップにおける前記中央部の順方向特性を前記周辺部の順方向特性よりも高くしたことを特徴とする請求項８記載の半導体装置の製造方法。   9. The method of manufacturing a semiconductor device according to claim 8, wherein the forward characteristic of the central portion of the semiconductor chip is made higher than the forward characteristic of the peripheral portion by electron beam irradiation.
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