JPH05315467A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH05315467A JPH05315467A JP4113468A JP11346892A JPH05315467A JP H05315467 A JPH05315467 A JP H05315467A JP 4113468 A JP4113468 A JP 4113468A JP 11346892 A JP11346892 A JP 11346892A JP H05315467 A JPH05315467 A JP H05315467A
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- substrate
- hole
- substrates
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、特に高周波電力増幅
用の厚膜混成集積回路装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thick film hybrid integrated circuit device especially for high frequency power amplification.
【０００２】[0002]
【従来の技術】近年、無線通信装置の電力増幅部をハイ
ブリッド型の集積回路としたものが多く提供され、より
小型化する傾向がある。従来の装置としては、例えば、
図３、図４に示すようなものや、図５、図６に示すよう
なものがある。図３、図４に示すものは、アルミナ等か
らなる第１絶縁基板１の表面に、メタライズされた導体
膜である入力用導体５ａ、出力用導体５ｂおよび接地用
導体５ｃが形成されている。７は半導体素子（トランジ
スタ）を示し、その半導体素子７のボンディングパッド
に金属細線８ａ、８ｂを介してそれぞれ入力用導体５
ａ、接地用導体５ｃ上に接続されている。また基板１上
には回路上必要な導体、回路素子が形成されている。2. Description of the Related Art In recent years, a large number of hybrid type integrated circuits have been provided for the power amplification section of a wireless communication device, and there is a tendency for further miniaturization. As a conventional device, for example,
There are those shown in FIGS. 3 and 4 and those shown in FIGS. 5 and 6. As shown in FIGS. 3 and 4, the input conductor 5a, the output conductor 5b, and the grounding conductor 5c, which are metallized conductor films, are formed on the surface of the first insulating substrate 1 made of alumina or the like. Reference numeral 7 denotes a semiconductor element (transistor), and the input conductor 5 is connected to the bonding pad of the semiconductor element 7 via the thin metal wires 8a and 8b.
a, connected to the grounding conductor 5c. In addition, conductors and circuit elements necessary for the circuit are formed on the substrate 1.
【０００３】半導体素子７は、高周波領域での大電力増
幅に使用するため発熱量が大きく、そのため半導体素子
７の放熱をよくするために、導体５ｂ上に放熱プレート
１１が設けられている。この放熱プレート１１上に半導
体素子７が半田材により接合されている。また、回路装
置全体の放熱性をよくするために放熱板９が半田材１０
を介して第１絶縁基板１の裏面に設けられている。絶縁
基板１の上下面を導通させるためにスルーホール１２を
穿設してある。１３は外部接続用の電源端子、及び入力
端子であり、１４はキャップである。Since the semiconductor element 7 is used for high power amplification in a high frequency region, it generates a large amount of heat, and therefore, in order to improve heat dissipation of the semiconductor element 7, a heat dissipation plate 11 is provided on the conductor 5b. The semiconductor element 7 is bonded onto the heat dissipation plate 11 with a solder material. Further, in order to improve the heat dissipation of the entire circuit device, the heat dissipation plate 9 is provided with the solder material 10.
It is provided on the back surface of the first insulating substrate 1 via. Through holes 12 are formed in order to electrically connect the upper and lower surfaces of the insulating substrate 1. Reference numeral 13 is a power supply terminal and an input terminal for external connection, and 14 is a cap.
【０００４】図５、図６に示すものは、半導体素子の発
熱量が非常に大きくなった場合の半導体装置の構造であ
り、上述した放熱プレート１１の代わりに、第２絶縁基
板１５として熱伝導性の非常によいベリリア等を使用す
る。第２絶縁基板１５上の半導体組み立ては別の工程で
行い、半田付け工程で放熱板９上への搭載が行われ、第
２絶縁基板１５にロウ付けされているリード１６、１７
が第１絶縁基板１の導体膜５ａ、５ｂと半田１８により
接続される。このように第２絶縁基板１５上の半導体組
み立てを別の工程で行ってから半田付け工程で放熱板９
上へ搭載する理由は、第１絶縁基板１と第２絶縁基板１
５との材質の違いによる熱膨張係数の相違から、例えば
後述する図７に示すように埋設したのではこれらの基板
が割れる危険が極めて大きいので、基板間に隙間をもた
せて放熱板９に固定するようにしたのである。FIGS. 5 and 6 show the structure of a semiconductor device when the amount of heat generated by a semiconductor element is extremely large. Instead of the above-mentioned heat dissipation plate 11, a second insulating substrate 15 is used for heat conduction. It uses beryllia, etc., which has very good properties. Assembling the semiconductor on the second insulating substrate 15 is performed in another process, is mounted on the heat dissipation plate 9 in the soldering process, and the leads 16 and 17 brazed to the second insulating substrate 15 are mounted.
Are connected to the conductor films 5 a and 5 b of the first insulating substrate 1 by the solder 18. As described above, the semiconductor assembly on the second insulating substrate 15 is performed in another process, and then the heat dissipation plate 9 is performed in the soldering process.
The reason for mounting on top is the first insulating substrate 1 and the second insulating substrate 1.
From the difference in the thermal expansion coefficient due to the difference in the material from 5, the risk of cracking these substrates is extremely great if they are buried as shown in FIG. 7, which will be described later. I decided to do it.
【０００５】実開昭６２−１０７４４５号には、絶縁基
板上にペレットを実装したヒートシンクを搭載した構成
のものでは、ワイヤボンディングの際にヒートシンクの
角部がワイヤに接触しやすい欠点と、絶縁基板上面から
ヒートシンクとペレットがとび出しているために装置の
厚みを厚くしている欠点とを有するから、この欠点を改
良するために、図７に示すような構造の混成集積回路装
置が提案されている。すなわち、絶縁基板２０に貫通孔
２１を設け、その孔２１にヒートシンク２２が埋め込ま
れペレット２３がヒートシンク２２上にあり、ペレット
２３の上面が絶縁基板２０の上面よりも低くなってい
る、というものである。Japanese Utility Model Laid-Open No. 62-107445 discloses a structure in which a heat sink in which pellets are mounted on an insulating substrate is mounted, and a corner of the heat sink is apt to come into contact with a wire during wire bonding, and the insulating substrate. Since the heat sink and the pellets are projected from the upper surface, the device has a thickness that is increased. Therefore, in order to improve this defect, a hybrid integrated circuit device having a structure as shown in FIG. 7 has been proposed. There is. That is, the through hole 21 is provided in the insulating substrate 20, the heat sink 22 is embedded in the hole 21, the pellet 23 is on the heat sink 22, and the upper surface of the pellet 23 is lower than the upper surface of the insulating substrate 20. is there.
【０００６】[0006]
【発明が解決しようとする課題】図３、図４に示したも
のでは、半導体素子７の放熱をよくするために放熱プレ
ート１１を第１絶縁基板１上に搭載した構成であるか
ら、小型化するためには、上側に突出して高さが高くな
る点や第１絶縁基板１における占有面積が大きくなる点
に問題がある。図５、図６に示したものでは、第２絶縁
基板１５上の半導体組み立ては別の工程で行い、半田付
け工程で組み入れるようになっているから、工程数が多
い点、また第１絶縁基板１における占有面積が大きくな
る点で問題がある。図７に示したものでは、絶縁基板２
０の孔２１にヒートシンク２２を埋め込んだものである
から、双方の材質の違いによる熱膨張係数の相違によ
り、絶縁基板２０が割れる問題がある。In the structure shown in FIGS. 3 and 4, the heat dissipation plate 11 is mounted on the first insulating substrate 1 to improve the heat dissipation of the semiconductor element 7. In order to do so, there is a problem in that it protrudes to the upper side and the height becomes high, and the occupied area in the first insulating substrate 1 becomes large. In FIGS. 5 and 6, the semiconductor assembly on the second insulating substrate 15 is performed in a separate process and is incorporated in the soldering process. There is a problem in that the occupied area in 1 becomes large. In the case shown in FIG. 7, the insulating substrate 2
Since the heat sink 22 is embedded in the hole 21 of 0, there is a problem that the insulating substrate 20 is cracked due to the difference in the coefficient of thermal expansion due to the difference between the two materials.
【０００７】この発明は上記のような問題点を解決する
ためになされたもので、半導体素子および放熱板の間の
熱抵抗を改善し、小型化かつ製造が容易な高周波半導体
装置を提供することを目的とする。The present invention has been made to solve the above problems, and an object of the present invention is to provide a high frequency semiconductor device which is improved in thermal resistance between a semiconductor element and a heat sink and which can be miniaturized and easily manufactured. And
【０００８】[0008]
【課題を解決するための手段】この発明の混成集積回路
装置は、放熱板上に搭載される第１絶縁基板にこれを貫
通した穴部または切り欠き部を設け、半導体素子が搭載
される絶縁体もしくは金属からなる第２基板を上記穴部
または上記切り欠き部の内周面に対し余裕をもって収容
し、上記穴部または切り欠き部に収容した第２基板と穴
部または上記切り欠き部の内周面とを接合剤により一部
で接合して一体化してあることを特徴とする。According to the hybrid integrated circuit device of the present invention, a first insulating substrate mounted on a heat dissipation plate is provided with a hole or a cutout penetrating the first insulating substrate so that a semiconductor element is mounted. A second substrate made of a body or metal is accommodated in the inner peripheral surface of the hole or the notch with a margin, and the second substrate accommodated in the hole or notch and the hole or the notch It is characterized in that the inner peripheral surface and the inner peripheral surface are partially joined by a joining agent to be integrated.
【０００９】上記接合剤により一部で接合して一体化す
る場合、第２基板が四角形であるときはその一辺で接合
するのがよい。また、第２基板は熱伝導性のよいものと
するが、その材質は、絶縁基板の場合にはベリリアもし
くは窒化アルミ、金属の場合は銅とするのがよい。When part of the second substrate is joined and integrated by the above-mentioned joining agent, when the second substrate is a quadrangle, it is preferable to join on one side thereof. The second substrate has good thermal conductivity, and its material is preferably beryllia or aluminum nitride in the case of an insulating substrate and copper in the case of a metal.
【００１０】[0010]
【作用】第１絶縁基板の穴部または切り欠き部に第２基
板を余裕をもって収容してその全周でなく一部で接合し
てあるため、第１絶縁基板と第２基板との材質の相違に
より熱膨張に差異があっても、熱応力の発生部分が接合
部周辺に限られ、第１絶縁基板や第２基板の割れる危険
が大幅に減少する。Since the second substrate is accommodated in the hole or the cutout portion of the first insulating substrate with a margin and is joined not at the entire circumference but at a part thereof, the material of the first insulating substrate and the second substrate is Even if there is a difference in thermal expansion due to the difference, the portion where the thermal stress is generated is limited to the periphery of the joint portion, and the risk of cracking of the first insulating substrate and the second substrate is greatly reduced.
【００１１】上記第１絶縁基板と第２基板との一体化は
製造工程の比較的早い時期に行うことができるから、従
来のように第２基板に対するサブアセンブリの必要がな
くなる。このことは第２基板を従来のサブアセンブリし
て半田付け工程で組み入れる場合に比べて小さく形成で
きる。また、第２基板は第１絶縁基板とは別個に形成し
て接合するので、第１絶縁基板より熱伝導性のよいもの
を使用でき、これによって図３、図４に示した放熱プレ
ート１１を省略できる。Since the first insulating substrate and the second substrate can be integrated at a relatively early stage of the manufacturing process, the subassembly for the second substrate is not required unlike the conventional case. This can be made smaller than in the case where the second substrate is sub-assembled in the related art and incorporated in the soldering process. In addition, since the second substrate is formed separately from the first insulating substrate and bonded to the first insulating substrate, it is possible to use one having better thermal conductivity than the first insulating substrate, and thus the heat dissipation plate 11 shown in FIGS. 3 and 4 can be used. It can be omitted.
【００１２】[0012]
【実施例】実施例 図１は本発明の実施例を概略的に示す斜視図であり、図
２は図１のものに高周波半導体装置を実装した状態のＡ
−Ａ線に沿った断面図である。これらの図において図３
〜図６に示したものと同等部分は同一符号で示してあ
る。Embodiments FIG. 1 is a perspective view schematically showing an embodiment of the present invention, and FIG. 2 is a view showing a state in which a high frequency semiconductor device is mounted on that of FIG.
It is a sectional view taken along the line A. In these figures, FIG.
The same parts as those shown in FIG. 6 are designated by the same reference numerals.
【００１３】図１において、第１絶縁基板１は、四角形
の穴部２５、四角形の一辺で開放された切り欠き部２６
を設けられており、その穴部２５に第２基板２を、また
切り欠き部２６に第２基板３を、夫々周辺に小間隙を形
成する寸法に形成して余裕をもって収容し、上記四角形
の一辺に対応する部分で接合剤４ａ、４ｂにより接合さ
れている。この接合剤４ａ、４ｂは半導体素子７のダイ
ボンド時の温度（約４００°Ｃ）に十分耐えられる材
料、例えば５００°Ｃ付近で焼結させるガラス系のペー
スト材を用いる。そしてこの接合は、ダイボンディング
の前に行われ、第１絶縁基板１と第２基板２、３が一体
化されたものとする。図１の接地導体膜５ｃはスルーホ
ル１２を介して下面導体と接続している。この第１絶縁
基板１及び第２基板２、３に高周波半導体装置を実装す
ると図２のようになる。In FIG. 1, the first insulating substrate 1 has a square hole 25 and a notch 26 opened at one side of the square.
The second substrate 2 is provided in the hole portion 25 thereof, the second substrate 3 is formed in the notch portion 26, and the second substrate 3 is formed in such a size as to form a small gap in the periphery, and the second substrate 2 is accommodated with a margin. The portions corresponding to one side are joined by the joining agents 4a and 4b. As the bonding agents 4a and 4b, a material that can sufficiently withstand the temperature (about 400 ° C.) at the time of die-bonding the semiconductor element 7, for example, a glass-based paste material that is sintered at around 500 ° C. is used. This bonding is performed before die bonding, and the first insulating substrate 1 and the second substrates 2 and 3 are integrated. The ground conductor film 5c in FIG. 1 is connected to the lower surface conductor via the through hole 12. The high-frequency semiconductor device is mounted on the first insulating substrate 1 and the second substrates 2 and 3 as shown in FIG.
【００１４】図２において、半導体素子７の裏面電極が
放熱板９と電気的に絶縁の必要な場合は、第２基板２は
絶縁基板とするが、電界効果形トランジスタのような場
合には、その裏面電極は放熱板９と電気的に同電位とな
るので、第２基板２は金属板でよい。勿論第２基板３に
おいても同様である。これらの材質は具体的には、第１
絶縁基板１はアルミナ、第２基板２、３はこれらが絶縁
基板の場合にはベリリアもしくは窒化アルミ、第２基板
２、３はこれらが金属板の場合には銅で構成する。同図
において、６ａ、６ｂは第２基板２が絶縁基板であると
きメタライズドした導体膜、８ｃは導体膜６ａと出力導
体膜５ｂを接続する金属細線である。In FIG. 2, when the back electrode of the semiconductor element 7 needs to be electrically insulated from the heat sink 9, the second substrate 2 is an insulating substrate, but in the case of a field effect transistor, the second substrate 2 is an insulating substrate. The second electrode 2 may be a metal plate because its back electrode has the same electric potential as that of the heat dissipation plate 9. Of course, the same applies to the second substrate 3. These materials are specifically
The insulating substrate 1 is made of alumina, the second substrates 2 and 3 are made of beryllia or aluminum nitride when they are insulating substrates, and the second substrates 2 and 3 are made of copper when they are metal plates. In the figure, 6a and 6b are conductor films metallized when the second substrate 2 is an insulating substrate, and 8c is a fine metal wire connecting the conductor film 6a and the output conductor film 5b.
【００１５】このような構成の混成集積回路装置は、予
め第１絶縁基板１と第２基板２、３を一体化しておくこ
とが出でき、その一体化は四角形の一辺で接合され他の
辺が自由な状態であるから、熱膨張係数に違いがあって
も熱応力による破損の恐れがほとんどなくなり、第１絶
縁基板１および第２基板２、３に対するダイボンディン
グを同じ工程で行うことができ、第２基板２、３に対し
て半導体素子７等をサブアセンブリしておく必要がなく
なり、また、第２基板２、３は第１絶縁基板１とは別個
に形成して接合するものであるから、第１絶縁基板より
も熱伝導性のよいものを使用できて、図４に示したよう
な放熱プレート１１を設ける必要がなくなる。従って、
基板の割れを防止できてしかも組立工程の簡略化と小型
化を達成できる。In the hybrid integrated circuit device having such a structure, the first insulating substrate 1 and the second substrates 2 and 3 can be integrated in advance, and the integration is joined by one side of a quadrangle. Since it is in a free state, there is almost no risk of damage due to thermal stress even if there is a difference in thermal expansion coefficient, and die bonding to the first insulating substrate 1 and the second substrates 2 and 3 can be performed in the same step. , It is not necessary to sub-assemble the semiconductor element 7 and the like to the second substrates 2 and 3, and the second substrates 2 and 3 are formed and joined separately from the first insulating substrate 1. Therefore, a material having better thermal conductivity than the first insulating substrate can be used, and it is not necessary to provide the heat dissipation plate 11 as shown in FIG. Therefore,
It is possible to prevent the substrate from cracking and to achieve simplification and miniaturization of the assembly process.
【００１６】[0016]
【発明の効果】以上のようにこの発明によれば、複数の
絶縁基板もしくは金属板を部分的に接合して熱応力によ
る基板の割れの問題を解決するとともに組立工程の簡略
化と小型化を達成できる効果を奏する。As described above, according to the present invention, a plurality of insulating substrates or metal plates are partially joined to solve the problem of cracking of the substrate due to thermal stress and simplification and miniaturization of the assembly process. It has an effect that can be achieved.
【図１】この発明の一実施例の第１絶縁基板と第２基板
を一体化した状態を示す概略斜視図である。FIG. 1 is a schematic perspective view showing a state in which a first insulating substrate and a second substrate of one embodiment of the present invention are integrated.
【図２】図１に示す一体化した基板に高周波半導体を実
装した状態のＡ−Ａ線に沿った概略縦断面図である。FIG. 2 is a schematic vertical cross-sectional view taken along the line AA in the state where a high frequency semiconductor is mounted on the integrated substrate shown in FIG.
【図３】従来の高周波電力増幅用厚膜混成集積回路装置
の一例を示す概略斜視図である。FIG. 3 is a schematic perspective view showing an example of a conventional thick film hybrid integrated circuit device for high frequency power amplification.
【図４】図３のＢ−Ｂ線に沿った縦断面図である。4 is a vertical cross-sectional view taken along the line BB of FIG.
【図５】従来の高周波電力増幅用厚膜混成集積回路装置
の他の例を示す斜視図である。FIG. 5 is a perspective view showing another example of a conventional thick film hybrid integrated circuit device for high frequency power amplification.
【図６】図５のＣ−Ｃ線に沿った縦断面図である。6 is a vertical cross-sectional view taken along the line CC of FIG.
【図７】従来の混成集積回路装置のさらに他の例を示す
概略縦断面図である。FIG. 7 is a schematic vertical sectional view showing still another example of a conventional hybrid integrated circuit device.
１ 第１絶縁基板 ２ 第２基板 ３ 第２基板 ４ａ 接合剤 ７ 半導体素子 ９ 放熱板 ２５ 穴部 ２６ 切り欠き部 1 1st insulating substrate 2 2nd substrate 3 2nd substrate 4a bonding agent 7 semiconductor element 9 heat sink 25 hole 26 notch
Claims (1)
れを貫通した穴部または切り欠き部を設け、半導体素子
が搭載される絶縁体もしくは金属からなる第２基板を上
記穴部または上記切り欠き部の内周面に対し余裕をもっ
て収容し、上記穴部または切り欠き部に収容した第２基
板と穴部または上記切り欠き部の内周面とを接合剤によ
り一部で接合して一体化してあることを特徴とする混成
集積回路装置。1. A first insulating substrate mounted on a heat dissipation plate is provided with a hole portion or a notch portion penetrating the first insulating substrate, and a second substrate made of an insulator or a metal on which a semiconductor element is mounted is provided with the hole portion or The second substrate accommodated in the inner peripheral surface of the cutout portion with a margin, and the second substrate accommodated in the hole or cutout portion and the inner peripheral surface of the hole portion or the cutout portion are partially joined by a bonding agent. A hybrid integrated circuit device characterized by being integrated into one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4113468A JPH05315467A (en) | 1992-05-06 | 1992-05-06 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4113468A JPH05315467A (en) | 1992-05-06 | 1992-05-06 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05315467A true JPH05315467A (en) | 1993-11-26 |
Family
ID=14613018
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4113468A Pending JPH05315467A (en) | 1992-05-06 | 1992-05-06 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05315467A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0836227A3 (en) * | 1996-10-09 | 1999-03-10 | Hewlett-Packard Company | Heat conductive substrate mounted in PC board hole for transferring heat from IC to heat sink |
| US6320756B1 (en) | 1999-01-18 | 2001-11-20 | Alps Electric Co., Ltd. | Electronic device mounting structure using electronic device mounting member and cushioning |
| JP2007027227A (en) * | 2005-07-13 | 2007-02-01 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
| JP2010192496A (en) * | 2009-02-16 | 2010-09-02 | Kyocera Corp | Substrate for loading device |
| US9030005B2 (en) | 2010-08-27 | 2015-05-12 | Murata Manufacturing Co., Ltd. | Semiconductor device |
| JP2019041086A (en) * | 2017-08-29 | 2019-03-14 | 京セラ株式会社 | Semiconductor package and semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02210852A (en) * | 1989-02-10 | 1990-08-22 | Hitachi Ltd | High-frequency video amplifier |
-
1992
- 1992-05-06 JP JP4113468A patent/JPH05315467A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02210852A (en) * | 1989-02-10 | 1990-08-22 | Hitachi Ltd | High-frequency video amplifier |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0836227A3 (en) * | 1996-10-09 | 1999-03-10 | Hewlett-Packard Company | Heat conductive substrate mounted in PC board hole for transferring heat from IC to heat sink |
| US6320756B1 (en) | 1999-01-18 | 2001-11-20 | Alps Electric Co., Ltd. | Electronic device mounting structure using electronic device mounting member and cushioning |
| JP2007027227A (en) * | 2005-07-13 | 2007-02-01 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
| JP2010192496A (en) * | 2009-02-16 | 2010-09-02 | Kyocera Corp | Substrate for loading device |
| US9030005B2 (en) | 2010-08-27 | 2015-05-12 | Murata Manufacturing Co., Ltd. | Semiconductor device |
| JP2019041086A (en) * | 2017-08-29 | 2019-03-14 | 京セラ株式会社 | Semiconductor package and semiconductor device |
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