JPS6334962A - Structure for package - Google Patents

Structure for package

Info

Publication number
JPS6334962A
JPS6334962A JP61177525A JP17752586A JPS6334962A JP S6334962 A JPS6334962 A JP S6334962A JP 61177525 A JP61177525 A JP 61177525A JP 17752586 A JP17752586 A JP 17752586A JP S6334962 A JPS6334962 A JP S6334962A
Authority
JP
Japan
Prior art keywords
silicon chip
dielectric substrate
substrate
aluminum nitride
package structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61177525A
Other languages
Japanese (ja)
Inventor
Koichi Inoue
井上 広一
Yasutoshi Kurihara
保敏 栗原
Komei Yatsuno
八野 耕明
Masaaki Takahashi
正昭 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP61177525A priority Critical patent/JPS6334962A/en
Publication of JPS6334962A publication Critical patent/JPS6334962A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • HELECTRICITY
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
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    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
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    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To realize an airtight sealing structure of high reliability by a method wherein a conductive protrusion is formed on a wiring material or on an AlN material, or the AlN material is connected with the wiring material by using a conductive substance, or the AlN material is connected with the conduction path on the surface of the wiring material. CONSTITUTION:A wiring material 7 is prepared after, in addition to a first conduction layer 111 and a second conduction layer 112, a conduction path 113 to be used for the back of a silicon chip 1 in order to control the potential of the silicon chip 1 from the outside has been attached. Then, a ring-shaped adherence material whose outward form is square and which is to be used for the back of the silicon chip is inserted into a hole from above so that the material can be set on a connecting electrode 18 to be used for the back of the silicon chip. A square AlN material 301 whose ends are removed and which, after its both faces have been thick-metallized, is plated is inserted into the hole and is set on the adherence material 19 to be used for the back of the silicon chip. Onto this material a metallic material 302 is set via an adherence material 303. This assembly is brazed collectively in a forming glass atmosphere.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体基板を第一誘電体基板に固定し、−一誘
電体基板を、外周部に半導体基体を外部と電気的に結合
するための端子群を配置した第二誘電体基板と機械的に
結合した半導体パッケージ構造体に係り、特に、第一誘
電体基板が第二誘電体基板と異なる材質で構成されてお
り、しかも、第一誘電体基板が窒化アルミニラ11の焼
結体を含む二つ以上の材質からなる半導体パッケージ構
造体に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for fixing a semiconductor substrate to a first dielectric substrate, and electrically coupling the semiconductor substrate to the outside on the outer periphery of the first dielectric substrate. This relates to a semiconductor package structure that is mechanically coupled to a second dielectric substrate on which a group of terminals is arranged, and in particular, the first dielectric substrate is made of a different material from the second dielectric substrate, and The present invention relates to a semiconductor package structure in which a dielectric substrate is made of two or more materials including a sintered body of aluminum nitride 11.

〔従来の技術〕[Conventional technology]

Anwar Mohammsd、 ”THICK FI
LM METALLIZAT工0NSAND PERF
ORMANCIE OF A POVERHVBRID
 MODULE ONALUMINUM NITRID
E 5UBSTRATH3,” Proceeding
s ofthe  1985  Internatio
nal Sy+++posium  onMicroe
lectronics、pp、218−224 、No
vember。
Anwar Mohammsd, “THICK FI
LM METALLIZAT WORK 0NSAND PERF
ORMANCIE OF A POVERHVBRID
MODULE ONALUMINUM NITRID
E 5UBSTRATH3,”Proceeding
s of the 1985 International
nal Sy+++posium on Microe
electronics, pp, 218-224, No.
vember.

1985に開示されているように、半導体集積回路は、
近年、ますます高密度化、高集積化に拍車がかかり、L
SIチップは大型化の傾向が著しく、その発熱密度も増
大の一途をたどっている。このような状況に対応するた
め、LSIチップを外部回路に電気的に接続するための
半導体パッケージもその構造及び材質に大幅な改善が要
求されている。
As disclosed in 1985, semiconductor integrated circuits are
In recent years, the trend toward higher density and higher integration has accelerated, and L
There is a remarkable tendency for SI chips to become larger, and their heat generation density is also increasing. In order to cope with such a situation, significant improvements are required in the structure and materials of semiconductor packages for electrically connecting LSI chips to external circuits.

近年注目を集めている、いわゆる、ピン・グリッド・ア
レー型パッケージ(P、G、A、)は、この情勢に対応
して開発されたものである。
The so-called pin grid array type package (P, G, A,), which has been attracting attention in recent years, was developed in response to this situation.

一般的なP、G、A、の構成を第2図に示す。A typical configuration of P, G, and A is shown in FIG.

P、G、A、の主要部分は、第2図に示すように、大き
く分けて三つの部分から成り立っている。
The main parts of P, G, and A are roughly divided into three parts, as shown in FIG.

IC支持部材3はLSIチップを機械的に支え、LSI
チップで発生する熱を効貿よく逃がす働きをする。配線
用部材7はLSIチップへの電力の供給やLSIチップ
からの信号の取りだしを、その内部に形成した導電経路
11により行う。密閉用部材9はLSIチップを外界か
ら遮蔽するための蓋である。これらの三つの部分が一体
化したとき全体で気密の容器を形成する。この容器は外
界からLSIチップを遮蔽し、その性能を外界の状態に
関係なく、常に、維持する働きをする。
The IC support member 3 mechanically supports the LSI chip and
It works to efficiently dissipate the heat generated by the chip. The wiring member 7 supplies power to the LSI chip and takes out signals from the LSI chip through a conductive path 11 formed therein. The sealing member 9 is a lid for shielding the LSI chip from the outside world. When these three parts are put together, they form an airtight container. This container shields the LSI chip from the outside world and always maintains its performance regardless of the conditions of the outside world.

P、G、A、の構成材料に対する要求は上述の三つの部
分によりそれぞれ異なる。特に、IC支持部材3では熱
を効率よく逃がすために高熱伝導率が、LSIチップを
構成するシリコン(Si)との接着の信頼性確保のため
、Siに近い熱膨張係数が、また、システムの設計の自
由度を確保するためには、電気絶縁性が望まれる。近年
の半導体装置の高密度化に伴う高発熱密度化の趨勢によ
り、この部分には従来のアルミナ(A It 208)
から高熱伝導率のベリリア(Bed)が使用されるよう
になってきている。
Requirements for the constituent materials of P, G, and A are different depending on the above-mentioned three parts. In particular, the IC support member 3 has a high thermal conductivity to efficiently dissipate heat, and a thermal expansion coefficient close to that of silicon to ensure reliability of adhesion to the silicon (Si) that constitutes the LSI chip. Electrical insulation is desired to ensure freedom in design. Due to the recent trend toward higher heat generation density due to the higher density of semiconductor devices, conventional alumina (A It 208) is used in this part.
Since then, beryllia (Bed), which has high thermal conductivity, has come into use.

ベリリアの熱伝導率は260W/mKであり、アルミナ
(熱伝導率: 17W/mK)を使用したパッケージに
比べ、同一のパッケージサイズで■、STチップの発熱
量を大きく許すことができる。
The thermal conductivity of beryllia is 260 W/mK, and compared to a package using alumina (thermal conductivity: 17 W/mK), the ST chip can generate a larger amount of heat with the same package size.

しかし、ベリリアは高価であり、シリコン(熱膨張係数
: 3 X 10−8/’C)と熱膨張係数が合わない
(7,5X 10−8/’C) 、さらに有毒であると
いう大きな欠点を持っている。
However, beryllia is expensive, has a thermal expansion coefficient that does not match that of silicon (7.5 x 10-8/'C), and is toxic. have.

そこで、ベリリアの代替材料として、例えば、Anwa
r Mohammed、 ”THICK FII、M 
MRTALLTZATIONSAND  PERFOR
NANCE  OF  A  POすERHYBRID
  MODULE  ONALUMINUM NITR
IDE 5UnSTRATES、” Proceedi
ngs ofMicroelectronics、pp
+218−224 、November。
Therefore, as an alternative material to beryllia, for example, Anwa
r Mohammed, “THICK FII, M
MRTALLTZATIONSAND PERFOR
NANCE OF A POSUERHYBRID
MODULE ONALUMINUM NITR
IDE 5UnSTRATES,” Proceedi
ngs of Microelectronics, pp.
+218-224, November.

1985に開示されているように、窒化アルミニラ11
(A fl N)が開発された。Al2Nは熱伝導率が
140W/mKとBeOの半分位あり、しかも、熱膨張
係数がシリコンに近い3.4〜4.4X10−8/℃で
あり、さらに毒性がないというIC支持部材3に適した
性質を持っている。しかし、現状では多層配線が固型で
ある上にアルミナより高価であるために配線用部材7に
は使用されない、従って、IC支持部材3と配線用部材
7を一体化することができず、IC支持部材3と配線用
部材7とを何等かの方法で接着しなければならない。と
ころが、AQNは、配線用部材7に5通常、使われるア
ルミナ(熱膨張係数: 6.5 X 10−8/’C)
や、その他の材料と熱膨張係数が合わないために接着部
の残留応力が大きく、信頼性の高い接着方式が望まれる
Aluminum nitride 11 as disclosed in 1985
(A fl N) was developed. Al2N has a thermal conductivity of 140 W/mK, which is about half that of BeO, and a coefficient of thermal expansion of 3.4 to 4.4 x 10-8/°C, which is close to that of silicon, making it suitable for the IC support member 3 as it is non-toxic. It has certain characteristics. However, at present, multilayer wiring is not only solid but also more expensive than alumina, so it is not used as the wiring member 7. Therefore, the IC support member 3 and the wiring member 7 cannot be integrated, and the IC The support member 3 and the wiring member 7 must be bonded together by some method. However, AQN is made of alumina (coefficient of thermal expansion: 6.5 x 10-8/'C), which is usually used for the wiring member 7.
Because the coefficient of thermal expansion does not match that of other materials, the residual stress in the bonded area is large, and a highly reliable bonding method is desired.

AQNはアルミナ等、酸化物系のセラミックスに比べて
金属に対する接着力が弱いが、比較的低温(約350”
C以下)の温度条件ではチタン−白金−金膜をAQN表
面に形成し、はんだ付けする方法等、信頼性の高い方式
が既に開発されている。
AQN has weak adhesive strength to metals compared to oxide ceramics such as alumina, but it can be used at relatively low temperatures (approximately 350"
Highly reliable methods have already been developed, such as a method in which a titanium-platinum-gold film is formed on the AQN surface and soldered under a temperature condition of (C or lower).

P、G、A、ではシリコンチップのダイボンディング時
の加熱(約450℃)に耐えられる耐熱性が要求される
。しかし、450℃以上の高温に耐える接着方式では、
必然的に接着温度が高くなるため、接着温度からの冷却
過程でAQNと配線用部材7との熱膨張係数の差による
応力が大きくなり、信頼性の高い接着部が得られていな
い、特に、接着部の気密性を確保することが国電で、本
発明で扱うような、気密シールを必要とするパッケージ
に適用可能な接着部は未だに実現していない。
P, G, and A require heat resistance that can withstand heating (approximately 450° C.) during die bonding of silicon chips. However, with adhesive methods that can withstand high temperatures of over 450℃,
Since the bonding temperature inevitably becomes high, stress due to the difference in thermal expansion coefficient between the AQN and the wiring member 7 increases during the cooling process from the bonding temperature, making it impossible to obtain a highly reliable bonded part. Ensuring the airtightness of the bonded portion is a national priority, and a bonded portion that can be applied to packages that require an airtight seal, such as the one dealt with in the present invention, has not yet been realized.

一方、P 、 G 、 A 、の構造は、シリコン・チ
ップ1のワイヤボンディング性についての問題を抱えて
いる。第3図に第2図のシリコン・チップ1を含むP、
G、A、の中心部を拡大して示す。寸a、すなわち、シ
リコン・ウェハの厚さはシリコン・ウェハの直径が大き
くなるに伴って厚くなるが、現状では、はぼ0.5〜0
.6nl+である。これに対して1寸法す及び寸法Cは
グリーン・シート・プロセス及び配線容量上の制約から
、通常0.5〜0.7 ■である。その結果、図のよう
にワイヤボンディングを二列にわたって行うには二列目
142のボンディング段差が大きくなり、実用に耐えな
いという問題が生じ、勿論、ワイヤボンディングが一列
のみであれば問題は少ないが、ここでは工C支持部材3
にAl2Nを使用する特に発熱密度、実装密度の高い高
性能なピン・グリッド・フレーを扱うので当然ワイヤボ
ンディングが二列の構造に対応できなければならない6 以上の要求、すなわち、(1)450℃以上の耐熱性を
もつ高信頼性の気密接着構造と、(2)ワイヤボンディ
ング時の段差問題を解決する構造を、同時に満たす構造
として第4図に示すうに、IC支持部材3を二つの部材
で構成する手段が考えられる。すなわち、気密シールを
必要とする部分には配線用部材7に使用される材料(通
常はアルミナ)に近い熱膨張係数でしかも熱伝導率が大
きく、アルミナとの接着性の良好な金属部材302(例
えば、銅とタングステンの合金)を配し、シリコン・チ
ップ1の高さ調節と電気絶縁性と高熱伝導性の条件を満
たすためにAQN部材301を金属部材302に接着す
る。この構造では、AQN部材301と金属部材302
の間の接着部材303に気密性が要求されないため、従
来のメタライズ技術(例えばモリブデン−マンガン・ペ
ーストノ焼結)と通常のろう付技術とにより、容易に、
500℃の耐熱性をもつ接着部材303を形成できる利
点がある。
On the other hand, the structures of P, G, and A have problems regarding the wire bondability of the silicon chip 1. P including the silicon chip 1 of FIG. 2 in FIG.
The central parts of G and A are shown enlarged. The dimension a, that is, the thickness of the silicon wafer, increases as the diameter of the silicon wafer increases, but currently it is approximately 0.5 to 0.
.. It is 6nl+. On the other hand, the dimensions C and C are usually 0.5 to 0.7 mm due to constraints on the green sheet process and wiring capacity. As a result, when wire bonding is performed over two rows as shown in the figure, the bonding level difference in the second row 142 becomes large, causing the problem that it is not practical. , here, the work C support member 3
In particular, since we are dealing with high-performance pins, grids, and flakes with high heat generation density and mounting density, it is natural that wire bonding must be able to support a two-row structure.6 The above requirements, namely (1) 450℃ As shown in Fig. 4, the IC support member 3 is made up of two members, which simultaneously satisfies the above-mentioned heat-resistant and highly reliable airtight adhesion structure and (2) structure that solves the step problem during wire bonding. There are ways to configure it. In other words, the metal member 302 (which has a coefficient of thermal expansion close to that of the material used for the wiring member 7 (usually alumina), has high thermal conductivity, and has good adhesion to alumina) is used in the area that requires an airtight seal. For example, an alloy of copper and tungsten) is disposed, and the AQN member 301 is bonded to the metal member 302 in order to adjust the height of the silicon chip 1 and satisfy the requirements of electrical insulation and high thermal conductivity. In this structure, an AQN member 301 and a metal member 302
Since airtightness is not required for the adhesive member 303 between them, it can be easily bonded using conventional metallization techniques (for example, molybdenum-manganese paste sintering) and ordinary brazing techniques.
There is an advantage that the adhesive member 303 can be formed with heat resistance of 500°C.

しかし、この構造にはシリコン・チップ1の背面の電位
を外部から制御することが容易でないという大きな欠点
がある。本発明で扱うP、G、A。
However, this structure has a major drawback in that it is not easy to control the potential on the back surface of the silicon chip 1 from the outside. P, G, and A handled in the present invention.

のような絶縁型の半導体パッケージでは、一般的に(1
)シリコン・チップとパッケージ本体外周部(リードピ
ンを除く外周部分)が絶縁されていることはもちろん必
須であるが、同時に(2)シリコン・チップの背面の電
位を外部から制御することも要求される。すなわち、第
5図において、シリコン・チップの背面101(ダイボ
ンディング面)の電位を所望の値にするために、シリコ
ン・チップの背面101とリードピン10の少なくとも
一本とを接続しなければならない、ところが、第4図の
構造ではシリコン・チップの背面101とリードピン1
0とを容易に接続することができない。
Insulated semiconductor packages such as
) It is of course essential that the silicon chip and the outer periphery of the package body (the outer periphery excluding the lead pins) be insulated, but at the same time (2) it is also required to control the potential on the back side of the silicon chip from the outside. . That is, in FIG. 5, in order to set the potential of the back surface 101 (die bonding surface) of the silicon chip to a desired value, the back surface 101 of the silicon chip must be connected to at least one of the lead pins 10. However, in the structure shown in FIG. 4, the back surface 101 of the silicon chip and the lead pin 1
0 cannot be easily connected.

この問題に対しては、第6図に示すように。For this problem, as shown in Figure 6.

IC支持部材3をAQN部材301のみで構成するか(
同図(、、))、またはAflN部材301と金属部材
302の配置を第4図と逆にするか(同図(b))によ
って容易に解決することができる。
Is the IC support member 3 made up of only the AQN member 301?
This problem can be easily solved by reversing the arrangement of the AflN member 301 and the metal member 302 from that shown in FIG. 4 (FIG. 4(b)).

しかし、これらの構造では、すでに述べたように。But in these structures, as already mentioned.

気密シールが要求されるAQN部材301と配線用部材
7(アルミナ)の接着部分(接着部材6の部分)を高い
信頼性で形成できないという問題が残る。
The problem remains that the adhesive part (adhesive member 6 part) between the AQN member 301 and the wiring member 7 (alumina), which requires an airtight seal, cannot be formed with high reliability.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来技術は、450℃以上の高温に耐え、しかも、
気密シールを高信頼で実現できる手段と、外周部からシ
リコン・チップを電気的に絶縁しながらシリコン・チッ
プの背面の電位を外部から制御する手段とを同時に実現
できないという点で問題があった。
The above conventional technology can withstand high temperatures of 450°C or higher, and
There was a problem in that it was not possible to simultaneously realize a means to achieve a highly reliable airtight seal and a means to externally control the potential on the back surface of the silicon chip while electrically insulating the silicon chip from the outer periphery.

本発明の目的は、従来技術の欠点を解消した半導体パッ
ケージ構造体を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package structure that overcomes the drawbacks of the prior art.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、配線用部材7に導電性突起を設けるか、あ
るいは、AnN部材301に導電性突起を設けるか、あ
るいは、AQN部材301と配線用部材7とを導電性の
物質で接続するかにより、あるいは、AQN部材301
を配線用部材7の表面導電路に接続することにより達成
される。
The above purpose can be achieved by providing a conductive protrusion on the wiring member 7, providing a conductive protrusion on the AnN member 301, or connecting the AQN member 301 and the wiring member 7 with a conductive substance. , or AQN member 301
This is achieved by connecting to the surface conductive path of the wiring member 7.

〔作用〕[Effect]

本発明では、半導体基体を固定した第一誘電体基板を、
窒化アルミニウムを含む二つ以上の材料で構成し、第一
誘電体基板の、半導体基体に接続する部材を窒化アルミ
ニウムで構成し、第一誘電体基板の、外周部に半導体基
体を外部と電気的に結合するための端子群を配置した第
二誘電体基板と接着する部材を導電性材料で構成し、窒
化アルミニウム部材、或いは、第二誘電体基板に導電性
の突起を設けるか、或いは、窒化アルミニウム部材と第
二誘電体基板とを導電性の部材で接続するか、或いは、
窒化アルミニウム部材を第二誘電体基板の表面導電路に
接続することにより、窒化アルミニウム部材の半導体基
体に接する面と第二誘電体基板の端子群の少なくとも一
個とを電気的に接続し、半導体基体の背面と外部回路と
を電気的に接続することができるようにする。
In the present invention, the first dielectric substrate on which the semiconductor substrate is fixed is
The first dielectric substrate is made of two or more materials including aluminum nitride, and the member of the first dielectric substrate that connects to the semiconductor substrate is made of aluminum nitride. The member to be bonded to the second dielectric substrate on which the terminal group for coupling to is arranged is made of a conductive material, and the aluminum nitride member or the second dielectric substrate is provided with conductive protrusions, or the second dielectric substrate is made of aluminum nitride. Connect the aluminum member and the second dielectric substrate with a conductive member, or
By connecting the aluminum nitride member to the surface conductive path of the second dielectric substrate, the surface of the aluminum nitride member in contact with the semiconductor substrate and at least one terminal group of the second dielectric substrate are electrically connected, and the semiconductor substrate To enable electrical connection between the back surface of the device and an external circuit.

〔実施例〕〔Example〕

実施例1 本発明の実施例を第11図に従って説明する0本実施例
では、第2図に示したような一般的なピン・グリッド・
アレーに於けるIC支持部材3を。
Embodiment 1 An embodiment of the present invention will be explained according to FIG. 11. In this embodiment, a general pin grid as shown in FIG.
IC support member 3 in the array.

AQN部材301と金属部材302とで構成した。It is composed of an AQN member 301 and a metal member 302.

ここで、金属部材302としては熱膨張係数が配線用部
材7の材質であるアルミナにほぼ等しく、熱伝導率がベ
リリア並みの鋼−20重量%タングステン(Cu−20
wt%W)を用いた。また、AQN部材301と金属部
材302との接着部材303の形成方法は、気密シール
を必要としないので通常の方法とした。すなわち、AQ
N部材301にモリブデン−マンガンの混合物による厚
膜メタライズを施し、金属部材302 (Cu−20w
t%W)とを共晶銀ろう(銀71〜73重量%−銅27
〜29重量%)を用いて8F)0℃でフォーミングガス
?HIH気でろう付けをした。
Here, the metal member 302 has a coefficient of thermal expansion almost equal to that of alumina, which is the material of the wiring member 7, and a thermal conductivity of steel-20% tungsten (Cu-20
wt%W) was used. Further, the method of forming the adhesive member 303 between the AQN member 301 and the metal member 302 was a normal method since an airtight seal was not required. That is, AQ
The N member 301 is coated with a thick film metallization using a molybdenum-manganese mixture, and the metal member 302 (Cu-20w
t%W) and eutectic silver solder (71-73% by weight of silver - 27% by weight of copper)
~29% by weight) using forming gas at 8F) 0°C? I did the brazing with high energy.

本発明によるパッケージを得る手順について説明する。A procedure for obtaining a package according to the present invention will be explained.

(+)  第−m4電路111と第二層導電路1]2に
加えてシリコン・チップ1の背面の電位を外部から制御
するためのシリコン・チップ背面用導電路11;3を付
加した配線用部材7を用意する。配線用部材7の中心部
には一辺10mmの正方形の孔が開いているが、その全
周、あるいは、一部にシリコン・チップ背面用導電路1
13の終端には接続したシリコン・チップ背面用接続電
極(基板側)18を備える長さ]I+I11の配線用部
材個突起26が設けられる。
(+) In addition to the −m4th electrical path 111 and the second layer conductive path 1] 2, a conductive path 11 for the back surface of the silicon chip for externally controlling the potential on the back surface of the silicon chip 1 is used for wiring. Prepare member 7. A square hole with a side of 10 mm is opened in the center of the wiring member 7, and the conductive path 1 for the back surface of the silicon chip is formed around the whole or part of the hole.
At the terminal end of the wiring member 13, a wiring member protrusion 26 having a length of I+I11 and having a connecting electrode (substrate side) 18 for the back side of the silicon chip connected thereto is provided.

(ii )  外形が一辺9mの正方形のリング状のシ
リコン・チップ背面用接着部材19を図の上方から孔に
嵌挿し、シリコン・チップ背面用接続電極(基板側)1
8上に設置した後、端面を除き、両面にモリブデン−マ
ンガン厚膜メタライズを施した後ニッケルめっきを施し
た一辺9mの正方形のAQN部材301を孔に嵌挿し、
シリコン・チップ背面用接着部材19上に設置し、その
上に接着部材303を介して、金属部材302を設置す
る。同時に、金属部材302は、接着部材6を介して配
線用部材7にも接している6(iii )  シリコン
・チップテr面用接着部材19.接着部材303.接着
部材6は、上述のように、共晶ろうであり、最高温度8
50℃でフォーミングガス雰囲気中で、一括、ろう付を
行う。このとき、リードビン(図示せず)は配線用部材
7に同じ共晶ろうを用いてろう付けされる。
(ii) Insert the ring-shaped adhesive member 19 for the silicon chip back side into the hole from above in the figure, and connect the connecting electrode (substrate side) 1 for the silicon chip back side.
8, a square AQN member 301 with a side of 9 m, which has been subjected to molybdenum-manganese thick film metallization and nickel plating on both sides except for the end faces, is inserted into the hole.
It is installed on the adhesive member 19 for the back side of the silicon chip, and the metal member 302 is installed thereon via the adhesive member 303. At the same time, the metal member 302 is also in contact with the wiring member 7 via the adhesive member 6.6(iii) Adhesive member 19 for silicon chip surface. Adhesive member 303. As mentioned above, the adhesive member 6 is a eutectic solder and has a maximum temperature of 8
Bulk brazing is performed at 50°C in a forming gas atmosphere. At this time, the lead bin (not shown) is brazed to the wiring member 7 using the same eutectic solder.

(iv)  金の電解めっきを2〜3μm施し、シリコ
ン・チップ1のダイボンディング部(−辺7nn)及び
ワイヤボンディング電極(基板側)13を形成する。
(iv) Gold electrolytic plating is applied to a thickness of 2 to 3 μm to form a die bonding portion (−side 7 nn) of the silicon chip 1 and a wire bonding electrode (substrate side) 13.

(v)  パッケージの上・下を図と逆にし、裏面に金
膜を被着したシリコン・チップ1(−辺6nw++)を
A Q、 N部材301のほぼ中央部に配し、シリコン
・チップ1の裏面に被着された金膜を加熱(400℃、
窒素雰囲気)により金−シリコン共晶はんだに変化させ
、ダイボンド部材2としてシリコン・チップ1を接着す
る。
(v) With the top and bottom of the package reversed from the diagram, the silicon chip 1 (-side 6nw++) with a gold film coated on the back side is placed approximately in the center of the AQ,N member 301, and the silicon chip 1 Heating the gold film deposited on the back side (400℃,
The gold-silicon eutectic solder is changed into a gold-silicon eutectic solder (in a nitrogen atmosphere), and the silicon chip 1 is bonded as the die bonding member 2.

(vi )  シリコン・チップ1の表面側にはワイヤ
ボンディング電極!極(基板側)13と同じ数のワイヤ
ボンディング電極(チップ側)15が形成されており、
それらの間を金の細線であるワイヤ14で熱圧着する。
(vi) Wire bonding electrodes on the surface side of silicon chip 1! The same number of wire bonding electrodes (chip side) 15 as poles (substrate side) 13 are formed,
A wire 14, which is a thin gold wire, is used to bond them together by thermocompression.

(vii)  最後に密閉用部材9を金−錫の共晶はん
だであるキャップ接着部材8で配線用部材7に300’
C1窒素ガス雰囲気で接着し、本発明によるパッケージ
を完成する。
(vii) Finally, the sealing member 9 is attached to the wiring member 7 by 300' with the cap adhesive member 8 made of gold-tin eutectic solder.
The package according to the present invention is completed by bonding in a C1 nitrogen gas atmosphere.

本実施例によれば、AQN部材301.金属部材302
を配線用部材7に接着すると同時にシリコン・チップ背
面用接続電極(AQ、N部材側)20の電気的接続が完
了する点で有利である。
According to this embodiment, AQN member 301. Metal member 302
This is advantageous in that the electrical connection of the connection electrodes 20 for the back side of the silicon chip (AQ, N member side) is completed at the same time as the bonding to the wiring member 7.

実施例2 本発明の実施例を第7図に従って説明する。本実施例で
は、配線用部材側突起26を設ける点では第一の実施例
と同じであるが、シリコン・チップの背面101と第−
m4電路111とを接続する点が第一の実施例と異なる
。本実施例では付加導電路が不要であるため、配線用部
材7の製造時のグリーンシートの層数を増す必要がない
点で第一の実施例より有利である。
Example 2 An example of the present invention will be described with reference to FIG. This embodiment is the same as the first embodiment in that a protrusion 26 on the wiring member side is provided, but the rear surface 101 of the silicon chip and the -
This embodiment differs from the first embodiment in that it is connected to the m4 electric line 111. This embodiment is advantageous over the first embodiment in that there is no need to increase the number of green sheet layers when manufacturing the wiring member 7, since no additional conductive path is required.

実施例3 本発明の実施例を第8図に従って説明する。本実施例で
は、配線用部材7に突起を設ける代わりにAffN部材
301にシリコン・チップ背面用接続突起21を設ける
点が第一の実施例と異なる。
Example 3 An example of the present invention will be described with reference to FIG. This embodiment differs from the first embodiment in that instead of providing a protrusion on the wiring member 7, a connection protrusion 21 for the back side of the silicon chip is provided on the AffN member 301.

この突起は、導電性セラミックスであるジルコニウム・
ポライドによって形成されており、AQNと同時に焼成
される。本実施例で配線用部材7に付加導電路(シリコ
ン・チップ背面用導電路113)のみならず、配線用部
材側突起26も設ける必要がない点で第一の実施例より
有利である。
This protrusion is made of zirconium, which is a conductive ceramic.
It is made of poride and is fired at the same time as AQN. This embodiment is advantageous over the first embodiment in that it is not necessary to provide the wiring member 7 with not only the additional conductive path (the conductive path 113 for the back side of the silicon chip) but also the wiring member side protrusion 26.

実施例4 本発明の実施例を第9図に従って説明する。本実施例で
は、銅によるシリコン・チップ背面用接続部材22によ
って第−m4電路111とシリコン・チップ背面用接続
電極(AQN部材側)20とを接続する点が第一の実施
例と異なる。本実施例で配線用部材7及びAQN部材3
01に一切の加工、変形を必要としない点で第一から第
三の実施例より有利である。
Example 4 An example of the present invention will be described with reference to FIG. This embodiment differs from the first embodiment in that the -m4th electrical path 111 and the silicon chip back side connection electrode (AQN member side) 20 are connected by a silicon chip back side connection member 22 made of copper. In this embodiment, the wiring member 7 and the AQN member 3
This embodiment is more advantageous than the first to third embodiments in that it does not require any processing or modification.

実施例5 本発明の実施例を第10図に従って説明する。Example 5 An embodiment of the present invention will be described with reference to FIG.

本実施例では、シリコン・チップ背面用ワイヤ24によ
り第−m4電路111とシリコン・チップ背面用接続電
極(AQN部材側)20とを接続する点が第一の実施例
と異なる。本実施例では配線用部材7及びAQN部材3
01に一切の加工。
This embodiment differs from the first embodiment in that the -m4th electric path 111 and the connection electrode (AQN member side) 20 for the back surface of the silicon chip are connected by the wire 24 for the back surface of the silicon chip. In this embodiment, the wiring member 7 and the AQN member 3
No processing was done on 01.

変形を必要としない点では第四の実施例と同じであるが
、シリコン・チップ背面用接続部材22を特に用意しな
くてもよい点で第四の実施例よりさらに有利である。
This embodiment is the same as the fourth embodiment in that no modification is required, but is more advantageous than the fourth embodiment in that there is no need to prepare a connecting member 22 for the back side of the silicon chip.

実施例6 本発明の実施例を第11図に従って説明する。Example 6 An embodiment of the present invention will be described with reference to FIG.

本実施例ではシリコン・チップの背面の電位を外部から
制御する手段として配線用部材7の内部導電路を用いる
第一から第五の実施例と異なり、シリコン・チップ背面
用導電路113を配線用部材7の表面に配した。本実施
例によれば、A Q、 N部材301及び金属部材30
2に若干の加工を施すのみで本発明の目的を達すること
ができる。
In this embodiment, unlike the first to fifth embodiments in which the internal conductive path of the wiring member 7 is used as a means for externally controlling the potential on the back surface of the silicon chip, the conductive path 113 for the back surface of the silicon chip is used for wiring. It was placed on the surface of member 7. According to this embodiment, the AQ, N members 301 and the metal member 30
The object of the present invention can be achieved by only slight processing of 2.

ここで、シリコン・チップ背面用接着部材19゜接着部
材303.接着部材6は本実施例で用いた共晶ろうであ
る必要はない。後工程での熱処理温度に耐える耐熱性を
もつ接着部材であれば一般的なろう材から適宜選んでも
よい。もちろん、拡散接合等、ろう付以外の接着手段を
選んでもよい。
Here, the adhesive member 19 for the silicon chip back side and the adhesive member 303. The adhesive member 6 does not need to be the eutectic solder used in this embodiment. Any adhesive member may be appropriately selected from common brazing materials as long as it has heat resistance that can withstand the heat treatment temperature in the subsequent process. Of course, adhesive means other than brazing, such as diffusion bonding, may be selected.

また、金属部材302は本実施例で用いた銅−20重量
%タングステンである必要はない。熱伝導率は銅−20
重量%タングステン合金より劣るが、熱膨張係数がアル
ミナに近い鉄−ニッケル合金等も使用できる。この場合
、パッケージの熱抵抗を悪化させないためには金属部材
302を薄くすればよい。逆に、熱膨張係数がアルミナ
より大きいが、熱伝導率が優れている銅等を使用するこ
ともできる。この場合、熱膨張係数の差に基づく熱応力
は、金属部材302の板厚と曲率を適当に選ぶことによ
り信頼性を損なわないレベルにまで下げることができる
Further, the metal member 302 does not need to be the copper-20% by weight tungsten used in this embodiment. Thermal conductivity is copper -20
Iron-nickel alloys, etc., whose coefficient of thermal expansion is close to that of alumina, although inferior to tungsten alloys by weight, can also be used. In this case, the metal member 302 may be made thinner in order not to deteriorate the thermal resistance of the package. Conversely, it is also possible to use copper, which has a larger coefficient of thermal expansion than alumina but excellent thermal conductivity. In this case, the thermal stress due to the difference in thermal expansion coefficients can be reduced to a level that does not impair reliability by appropriately selecting the plate thickness and curvature of the metal member 302.

また、ダイボンド部材2及び密閉用部材9に接着部材8
は本実施例のものである必要はなく、一般的なはんだ材
から適宜選んでよい。ただし、ダイボンド部材2の融点
は、当然のことながら、後工程であるキャップ接着部材
8の作業温度(通常融点より約50℃高い)よりも高く
なければならない。
In addition, an adhesive member 8 is attached to the die bond member 2 and the sealing member 9.
The solder material does not have to be that of this embodiment, and may be appropriately selected from general solder materials. However, the melting point of the die bonding member 2 must naturally be higher than the working temperature (usually about 50° C. higher than the melting point) of the cap bonding member 8, which is a subsequent process.

実施例7 本発明によるパッケージ構造体では、第12図に示すよ
うに、金属部材302を金属容器3020とし、内部に
冷却水27を流すことにより、容易に水冷型パッケージ
構造体が得られる6本構造ではパッケージの外周部に直
接水を流すのと熱的に等価であり、LSIチップの発熱
量を最大限に許容できる。
Embodiment 7 In the package structure according to the present invention, as shown in FIG. 12, a water-cooled package structure can be easily obtained by using a metal member 302 as a metal container 3020 and flowing cooling water 27 inside. The structure is thermally equivalent to flowing water directly to the outer periphery of the package, and the amount of heat generated by the LSI chip can be tolerated to the maximum.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、半導体基体の電位を外部がら制御でき
、しかも、半導体基体をパッケージ外部から電気的に絶
縁した高信頼性の気密シール構造の窒化アルミニウムを
用いたパッケージ構造体が得られる。
According to the present invention, it is possible to obtain a package structure using aluminum nitride having a highly reliable airtight seal structure in which the potential of the semiconductor substrate can be controlled from the outside and the semiconductor substrate is electrically insulated from the outside of the package.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の拡大断面図、第2図は本発
明が扱うパッケージの一般的構造を示す一部断面斜視図
、第3図は第2図の一部拡大断面図、第4図ないし第6
図は従来例を示す一部拡大断面図、第7図ないし第12
図は本発明の他の実施例を示す一部拡大断面図である。 1・・・シリコン・チップ、111・・・第1層導電路
。 112・・・第2層導電路、113・・・シリコン・チ
ップ背面用導電路、13・・・ワイヤボンディング電極
(基板側)、14・・・ワイヤ、141・・・1列目の
ワイヤ、142・・・2列目のワイヤ、15・・・ワイ
ヤボンディング電極(チップ側)、16・・・仮想導電
路、17・・・AQN表面メタライズ層、18・・・シ
リコン・チップ背面用接続電極(基板側)、19・・・
シリコン・チップ背面用接着部材、20・・・シリコン
・チップ背面用接続電極(AlliN部材側)、21・
・・シリコン・チップ背面用接続突起、22・・・シリ
コン・チップ背面用接続部材、23・・・シリコン・チ
ップ背面用接着部材、24・・・シリコン・チップ背面
用ワイヤ、25・・・シリコン・チップ背面用ワイヤボ
ンディング電極、26・・・配線用部材側突起。
FIG. 1 is an enlarged sectional view of an embodiment of the present invention, FIG. 2 is a partially sectional perspective view showing the general structure of a package handled by the present invention, and FIG. 3 is a partially enlarged sectional view of FIG. Figures 4 to 6
The figures are partially enlarged cross-sectional views showing conventional examples, Figures 7 to 12.
The figure is a partially enlarged sectional view showing another embodiment of the present invention. 1... Silicon chip, 111... First layer conductive path. 112... Second layer conductive path, 113... Silicon chip back side conductive path, 13... Wire bonding electrode (substrate side), 14... Wire, 141... First row wire, 142... Second row wire, 15... Wire bonding electrode (chip side), 16... Virtual conductive path, 17... AQN surface metallized layer, 18... Connection electrode for silicon chip back side (board side), 19...
Adhesive member for silicon chip back surface, 20... Connection electrode for silicon chip back surface (AlliN member side), 21.
... Connection protrusion for the back side of the silicon chip, 22... Connection member for the back side of the silicon chip, 23... Adhesive member for the back side of the silicon chip, 24... Wire for the back side of the silicon chip, 25... Silicon - Wire bonding electrode for the back side of the chip, 26...Protrusion on the side of the wiring member.

Claims (1)

【特許請求の範囲】 1、半導体基体を第一誘電体基板に固定し、前記第一誘
電体基板を、外周部に前記半導体基体を外部と電気的に
結合するための端子群を配置した第二誘電体基板と機械
的に結合した半導体パッケージ構造体に於いて、 前記第一誘電体基板を複数の材料で構成し、前記第一誘
電体基板の、前記半導体基体に接続する部材を窒化アル
ミニウムで構成し、前記第一誘電体基板の、前記第二誘
電体基板と機械的に結合する部材を導電性材料で構成し
、前記窒化アルミニウム部材の前記半導体基体に接する
面と前記第二誘電体基板の前記端子群の少なくとも一個
を電気的に接続し、前記端子群を除く前記半導体パッケ
ージ構造体の外周部を前記半導体基体と電気的に絶縁す
ることを特徴とするパッケージ構造体。 2、特許請求の範囲第1項に於いて、 前記第二誘電体基板に、前記窒化アルミニウム部材の前
記半導体基体に接する面と接続するための突起及び内部
付加導電路を備えることを特徴とするパッケージ構造体
。 3、特許請求の範囲第1項に於いて、 前記第二誘電体基板に、前記窒化アルミニウム部材の前
記半導体基体に接する面とを接続するための突起を備え
たことを特徴とするパツケージ構造体。 4、特許請求の範囲第1項に於いて、 前記窒化アルミニウム部材の前記半導体基体に接する面
の周辺に導電性セラミックスの突起を備え、前記突起を
前記第二誘電体基板の既設内部導電路に電気的に接続す
ることを特徴とするパッケージ構造体。 5、特許請求の範囲第1項に於いて、 前記窒化アルミニウム部材の前記半導体基体に接する面
と前記第二誘電体基板の前記既設内部導電路との間に導
電部材を設けることを特徴とするパッケージ構造体。 6、特許請求の範囲第1項に於いて、 前記窒化アルミニウム部材の前記半導体基体に接する面
と前記第二誘電体基板の表面導電路とを電気的に接続す
ることを特徴とするパッケージ構造体。
[Claims] 1. A semiconductor substrate is fixed to a first dielectric substrate, and the first dielectric substrate is provided with a terminal group on the outer periphery for electrically connecting the semiconductor substrate to the outside. In a semiconductor package structure mechanically coupled to a second dielectric substrate, the first dielectric substrate is made of a plurality of materials, and the member of the first dielectric substrate connected to the semiconductor substrate is made of aluminum nitride. a member of the first dielectric substrate that is mechanically coupled to the second dielectric substrate is made of a conductive material, and a surface of the aluminum nitride member in contact with the semiconductor substrate and the second dielectric A package structure, wherein at least one of the terminal groups of the substrate is electrically connected, and an outer peripheral portion of the semiconductor package structure except for the terminal group is electrically insulated from the semiconductor base. 2. In claim 1, the second dielectric substrate is provided with a protrusion and an internal additional conductive path for connection to the surface of the aluminum nitride member that is in contact with the semiconductor substrate. package structure. 3. A package structure according to claim 1, characterized in that the second dielectric substrate is provided with a protrusion for connecting the surface of the aluminum nitride member that is in contact with the semiconductor substrate. . 4. In claim 1, a conductive ceramic protrusion is provided around the surface of the aluminum nitride member in contact with the semiconductor substrate, and the protrusion is connected to an existing internal conductive path of the second dielectric substrate. A package structure characterized by electrical connection. 5. In claim 1, a conductive member is provided between the surface of the aluminum nitride member that contacts the semiconductor substrate and the existing internal conductive path of the second dielectric substrate. package structure. 6. A package structure according to claim 1, characterized in that a surface of the aluminum nitride member in contact with the semiconductor substrate and a surface conductive path of the second dielectric substrate are electrically connected. .
JP61177525A 1986-07-30 1986-07-30 Structure for package Pending JPS6334962A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61177525A JPS6334962A (en) 1986-07-30 1986-07-30 Structure for package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61177525A JPS6334962A (en) 1986-07-30 1986-07-30 Structure for package

Publications (1)

Publication Number Publication Date
JPS6334962A true JPS6334962A (en) 1988-02-15

Family

ID=16032444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61177525A Pending JPS6334962A (en) 1986-07-30 1986-07-30 Structure for package

Country Status (1)

Country Link
JP (1) JPS6334962A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63173348A (en) * 1987-01-13 1988-07-16 Toshiba Corp Semiconductor device
JPS63164237U (en) * 1987-04-15 1988-10-26
US6185028B1 (en) 1996-03-08 2001-02-06 Nihon Shingo Kabushiki Kaisha Optical barrier apparatus

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63173348A (en) * 1987-01-13 1988-07-16 Toshiba Corp Semiconductor device
JPS63164237U (en) * 1987-04-15 1988-10-26
JPH0514514Y2 (en) * 1987-04-15 1993-04-19
US6185028B1 (en) 1996-03-08 2001-02-06 Nihon Shingo Kabushiki Kaisha Optical barrier apparatus
US6246503B1 (en) 1996-03-08 2001-06-12 Nihon Shingo Kabushiki Kaisha Optical barrier apparatus

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