JP2007027227A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2007027227A
JP2007027227A JP2005203883A JP2005203883A JP2007027227A JP 2007027227 A JP2007027227 A JP 2007027227A JP 2005203883 A JP2005203883 A JP 2005203883A JP 2005203883 A JP2005203883 A JP 2005203883A JP 2007027227 A JP2007027227 A JP 2007027227A
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substrate
solder
semiconductor device
support
back surface
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JP4842574B2 (en
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Shigemi Kageyama
茂己 影山
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Mitsubishi Electric Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having such a structure that can suppress the scattering of solder during manufacturing. <P>SOLUTION: The semiconductor device 10 has such a structure that a supporting body 18 is bonded to the rear face 20 of a substrate 16 formed with storage holes 22 for storing semiconductor components 12 by means of solder 30, and that the semiconductor components 12 are mounted on part of the supporting body 18 which can be seen through the storage holes 22. The substrate 16 has through-holes 26 for connecting the rear face 20 and the principal plane 24 opposite to the rear face at least in the periphery of the storage holes 22. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

本発明は、半導体装置と半導体装置の製造方法に関するものであり、特に、はんだによって半導体装置の構成要素が接合されるものに関する。   The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a method in which components of a semiconductor device are joined by solder.

1Wを越えるような比較的パワーの大きい、例えば業務用無線やLAN等の通信に使用される整合回路付きの高周波パワーアンプモジュールなどにおいて、発熱する半導体素子を、熱伝導率が低い基板上に搭載するのではなく、熱伝導率が高い支持体、例えば放熱板に搭載するものがある。例えば、放熱板と基板の裏面がはんだによって接着される構造の半導体装置であって、基板に半導体素子(または半導体素子を有する半導体部品)が収容可能な収容穴(キャビティ)が形成され、キャビティを介して見える放熱板の部分に半導体素子または半導体部品が直接搭載されるまたは台座を介して搭載されるものがある。半導体素子または半導体部品は、基板の主面のキャビティ縁部に設けられた端子と電気的に接続される。このような半導体装置は、キャビティダウン型半導体装置と呼ばれている。キャビティダウン型半導体装置の一例として、特許文献1のものがある。
特開平11−97567号公報
A semiconductor element that generates heat is mounted on a substrate with low thermal conductivity in a high-frequency power amplifier module with a matching circuit used for communications such as commercial radio and LAN, etc., which has a relatively large power exceeding 1 W. Instead, there are those mounted on a support having high thermal conductivity, for example, a heat sink. For example, in a semiconductor device having a structure in which a heat sink and a back surface of a substrate are bonded by solder, a housing hole (cavity) that can accommodate a semiconductor element (or a semiconductor component having a semiconductor element) is formed in the substrate, and the cavity is formed. Some semiconductor elements or semiconductor components are mounted directly on the heat sink plate that can be seen through, or mounted via a pedestal. The semiconductor element or the semiconductor component is electrically connected to a terminal provided on the cavity edge of the main surface of the substrate. Such a semiconductor device is called a cavity down type semiconductor device. As an example of the cavity down type semiconductor device, there is one of Patent Document 1.
JP-A-11-97567

しかしながら、はんだによって放熱板と接着される基板にキャビティが形成された半導体装置において、はんだの溶融中に、はんだに含まれるフラックスが液化するまたは気化することにより体積膨張してキャビティから噴出し、それによりキャビティからフラックスや溶融したはんだ粉末が飛散することがある。これにより、溶融したはんだ粉末やフラックスが基板の主面に付着することがあった。   However, in a semiconductor device in which a cavity is formed in a substrate that is bonded to a heat sink by solder, the volume of the solder contained in the solder is melted and liquefied or vaporized during the melting of the solder and ejected from the cavity. As a result, flux and molten solder powder may be scattered from the cavity. As a result, molten solder powder or flux may adhere to the main surface of the substrate.

そこで、本発明は、基板の裏面と支持体をはんだによって接合する際の加熱工程において、キャビティから飛散するはんだ(フラックスや溶融したはんだ粉末)の基板の主面の付着を抑制する構造を有する半導体装置と半導体装置の製造方法を提供することを目的とする。   Therefore, the present invention provides a semiconductor having a structure that suppresses the adhesion of the main surface of the substrate to the solder (flux or molten solder powder) that scatters from the cavity in the heating process when the back surface of the substrate and the support are joined by solder. An object is to provide a device and a method for manufacturing a semiconductor device.

上記目的を達成するために、本発明に係る半導体装置は、
半導体部品の収容穴が形成された基板の裏面と支持体がはんだによって接合され、収容穴を介して見える支持体の部分に半導体部品が搭載される半導体装置であって、
基板は、少なくとも収容穴の周縁に裏面と該裏面と対向する主面を連絡する貫通穴を有することを特徴とする。
In order to achieve the above object, a semiconductor device according to the present invention includes:
A semiconductor device in which a back surface of a substrate on which a housing hole for a semiconductor component is formed and a support are joined by solder, and the semiconductor component is mounted on a portion of the support that can be seen through the housing hole,
The substrate has a through hole that communicates at least the back surface and the main surface opposite to the back surface at the periphery of the accommodation hole.

本発明によれば、基板の収容穴周縁部に主面と裏面を連絡する複数の貫通穴が形成されているため、はんだの溶融中、基板と支持体の間で液化したまたは気化したはんだのフラックスの移動は、収容穴と複数の貫通穴に分散する。これにより、収容穴から噴出するフラックスの量は、複数の貫通穴が基板に形成されていない場合に比べて少なくなる。その結果、収容穴から噴出したはんだの基板の主面への付着が抑制される。   According to the present invention, since a plurality of through holes that connect the main surface and the back surface are formed at the peripheral portion of the accommodation hole of the substrate, during the melting of the solder, the liquefied or vaporized solder between the substrate and the support body The movement of the flux is dispersed in the accommodation hole and the plurality of through holes. As a result, the amount of flux ejected from the accommodation hole is reduced as compared with the case where a plurality of through holes are not formed in the substrate. As a result, the adhesion of the solder ejected from the accommodation hole to the main surface of the substrate is suppressed.

まず、本明細書において、「はんだ」は、はんだ粉末とフラックスが混合されたものを言う。はんだ粉末は、例えば錫や鉛などの粉末であって、被接合部材の間で溶融して固化することにより該被接合部材同士を接合するものを言う。一方、フラックスは、例えば樹脂などであって、被接合部材の表面酸化物を除去して溶融したはんだ粉末と被接合部材の濡れ性を向上させるものを言う。   First, in this specification, “solder” refers to a mixture of solder powder and flux. The solder powder is, for example, a powder of tin, lead or the like, which joins the members to be joined by melting and solidifying between the members to be joined. On the other hand, the flux refers to, for example, a resin, which improves the wettability of the bonded member and the solder powder melted by removing the surface oxide of the bonded member.

実施の形態1.
図1(a)に本発明の一実施の形態に係る半導体装置の上面図を示し、図1(b)に図1(a)においてA方向から見た半導体装置の断面図を示す。図1において符号10で示される半導体装置は、いわゆるキャビティダウン型の半導体装置であって、概略、半導体チップ12と、半導体チップ12が搭載される台座14と、半導体チップ12と電気的に接続される基板16と、基板16が接合される放熱板18とを有する。
Embodiment 1 FIG.
FIG. 1A shows a top view of a semiconductor device according to an embodiment of the present invention, and FIG. 1B shows a cross-sectional view of the semiconductor device viewed from the A direction in FIG. A semiconductor device denoted by reference numeral 10 in FIG. 1 is a so-called cavity down type semiconductor device, and is generally electrically connected to the semiconductor chip 12, a pedestal 14 on which the semiconductor chip 12 is mounted, and the semiconductor chip 12. And a heat sink 18 to which the substrate 16 is bonded.

半導体チップ12は、放熱板18に裏面20が接合された基板16に形成されている穴(キャビティ)22を介して見える放熱板18の部分に台座14を介して搭載される。台座14は、熱伝導性に優れつつ半導体チップ12と放熱板18の間の線膨張係数差を考慮した材料で作製されている。これにより、半導体装置10の駆動中に半導体チップ12から発生した熱は、効率よく放熱板18に伝達される。   The semiconductor chip 12 is mounted via a pedestal 14 on a portion of the heat dissipation plate 18 that can be seen through a hole (cavity) 22 formed in the substrate 16 in which the rear surface 20 is bonded to the heat dissipation plate 18. The pedestal 14 is made of a material that takes into account the difference in coefficient of linear expansion between the semiconductor chip 12 and the heat sink 18 while being excellent in thermal conductivity. Thereby, the heat generated from the semiconductor chip 12 during driving of the semiconductor device 10 is efficiently transmitted to the heat radiating plate 18.

キャビティ22は、半導体チップ12が搭載された台座14を十分に収容するような大きさ、すなわちキャビティ22の内周面と台座14の間に間隙が形成されるような大きさで基板16に形成されている。   The cavity 22 is formed on the substrate 16 in such a size as to sufficiently accommodate the pedestal 14 on which the semiconductor chip 12 is mounted, that is, such that a gap is formed between the inner peripheral surface of the cavity 22 and the pedestal 14. Has been.

基板16には、少なくともキャビティ22の周縁部に複数の貫通穴(基板16の主面24と裏面20を連絡する穴)26が形成されている。複数の貫通穴26は、半導体装置10の駆動には関与しておらず、半導体装置10の製造において機能するものである。半導体装置10の製造については後述する。   In the substrate 16, a plurality of through holes (holes connecting the main surface 24 and the back surface 20 of the substrate 16) 26 are formed at least at the peripheral edge of the cavity 22. The plurality of through holes 26 are not involved in driving the semiconductor device 10 and function in the manufacture of the semiconductor device 10. The manufacture of the semiconductor device 10 will be described later.

また、基板16の主面24のキャビティ22の周縁部には、半導体チップ12とボンディングワイヤ28によって電気的に接続される接続部(図示せず)を有する。   In addition, the peripheral portion of the cavity 22 of the main surface 24 of the substrate 16 has a connection portion (not shown) that is electrically connected to the semiconductor chip 12 by a bonding wire 28.

次に、半導体装置10の作製方法、具体的に言うと基板16と放熱板18の接合方法について説明する。   Next, a method for manufacturing the semiconductor device 10, specifically, a method for bonding the substrate 16 and the heat sink 18 will be described.

基板16と放熱板18の接合は、はんだ30によって行われる。まず、クリーム状のはんだ(いわゆるソルダペーストと呼ばれるもので、はんだ粉末とペースト状のフラックスからなるもの)30が、基板16の裏面20または放熱板18の基板16との接合面のいずれか一方にスキージによって均一な厚さで塗布される。次に、基板16と放熱板18をはんだ30を介して重ね合わせる。続いて、はんだ30を溶融するために、例えば、はんだ30を介して重ね合わせた状態の基板16と放熱板18を炉に入れて加熱する。   The substrate 16 and the heat radiating plate 18 are joined by solder 30. First, cream-like solder (so-called solder paste, which is composed of solder powder and paste-like flux) 30 is applied to either the back surface 20 of the substrate 16 or the bonding surface of the heat sink 18 to the substrate 16. A uniform thickness is applied by a squeegee. Next, the substrate 16 and the heat radiating plate 18 are overlapped via the solder 30. Subsequently, in order to melt the solder 30, for example, the substrate 16 and the heat radiating plate 18 that are superposed via the solder 30 are placed in a furnace and heated.

はんだ30の溶融工程において、はんだ30に含まれるペースト状のフラックスが液化または気化し、基板16と放熱板18の間から外に向かって移動(噴出)する。このとき、液化または気化したフラックスは基板16に設けられた複数の貫通穴26やキャビティ22を介して外に移動する。キャビティ22を介して外に移動する液化または気化したフラックスの量は、複数の貫通穴26が基板16に形成されていない場合に比べて少なくなり、それにより、キャビティ22からフラックスが噴出することによってキャビティから飛散する溶融したはんだ粉末やフラックスの量も少なくなる。その結果、基板16の主面に付着するはんだ(溶融したはんだ粉末やフラックス)の量が少なくなる。   In the melting process of the solder 30, the paste-like flux contained in the solder 30 is liquefied or vaporized, and moves (spouts) from between the substrate 16 and the radiator plate 18. At this time, the liquefied or vaporized flux moves to the outside through a plurality of through holes 26 and cavities 22 provided in the substrate 16. The amount of the liquefied or vaporized flux that moves outside through the cavity 22 is smaller than that in the case where the plurality of through holes 26 are not formed in the substrate 16, thereby causing the flux to be ejected from the cavity 22. The amount of molten solder powder and flux scattered from the cavity is also reduced. As a result, the amount of solder (molten solder powder or flux) adhering to the main surface of the substrate 16 is reduced.

はんだ30が十分に溶融した後、はんだ30を固化するために、はんだ30を介して重ね合わせた状態の基板16と放熱板18が除熱される。そして、基板16と放熱板18が接合される。なお、基板16と放熱板18のはんだ30による接合とともに、半導体チップ12が搭載された台座14と放熱板18の接合を同一工程でおこなってもよい。   After the solder 30 is sufficiently melted, in order to solidify the solder 30, the substrate 16 and the heat radiating plate 18 in a state of being overlapped with each other through the solder 30 are removed. And the board | substrate 16 and the heat sink 18 are joined. In addition to joining the substrate 16 and the heat sink 18 with the solder 30, the base 14 on which the semiconductor chip 12 is mounted and the heat sink 18 may be joined in the same process.

実施の形態2.
上述の実施の形態は、基板に複数の貫通穴を形成することによってキャビティから飛散するはんだの量を少なくした。本実施の形態は、放熱板に貫通穴を形成することによりキャビティから飛散するはんだの量を抑制する。
Embodiment 2. FIG.
In the above-described embodiment, the amount of solder scattered from the cavity is reduced by forming a plurality of through holes in the substrate. In the present embodiment, the amount of solder scattered from the cavity is suppressed by forming a through hole in the heat sink.

図2(a)に本実施の形態に係る半導体装置の上面図を示し、図2(b)に図2(a)においてB方向から見た半導体装置の断面図を示す。   FIG. 2A shows a top view of the semiconductor device according to this embodiment, and FIG. 2B shows a cross-sectional view of the semiconductor device viewed from the B direction in FIG.

図2において符号110で示される半導体装置において、実施の形態1の半導体装置10と異なる点は放熱板118である。したがって、放熱板118について説明する。   In the semiconductor device denoted by reference numeral 110 in FIG. 2, a different point from the semiconductor device 10 of the first embodiment is a heat radiating plate 118. Therefore, the heat sink 118 will be described.

放熱板118は、少なくとも基板116の裏面120のキャビティ122の周縁部と対向する部分に、はんだ130を介して基板116と接合する面(接合面)132から該接合面132と対向する面(裏面)134を連絡する複数の貫通穴136を有する。貫通穴136は、実施の形態1の半導体装置10の基板16に形成された複数の貫通穴26と同様に機能し、基板116と放熱板118のはんだ130による接合時にキャビティ122から飛散するはんだの量を抑制する。   The heat radiating plate 118 is a surface (back surface) facing the bonding surface 132 from a surface (bonding surface) 132 bonded to the substrate 116 via the solder 130 at least in a portion facing the peripheral portion of the cavity 122 of the back surface 120 of the substrate 116. ) 134 having a plurality of through holes 136 communicating with each other. The through holes 136 function in the same manner as the plurality of through holes 26 formed in the substrate 16 of the semiconductor device 10 of the first embodiment, and the solder that scatters from the cavity 122 when the substrate 116 and the heat sink 118 are joined by the solder 130. Reduce the amount.

実施の形態1において基板16に形成される複数の貫通穴26のレイアウトは、例えばボンディングワイヤ28の端子などによって制限されるが、本実施の形態の放熱板118に形成される貫通穴136のレイアウトは大きく制限されることはない。   The layout of the plurality of through holes 26 formed in the substrate 16 in the first embodiment is limited by, for example, the terminals of the bonding wires 28, but the layout of the through holes 136 formed in the heat sink 118 of the present embodiment. Is not greatly limited.

実施の形態3.
本実施の形態は、実施の形態2とは異なり、貫通穴の代わりに溝が放熱板に形成されていることを特徴とする。
Embodiment 3 FIG.
Unlike the second embodiment, the present embodiment is characterized in that a groove is formed in the heat sink instead of the through hole.

図3(a)に本実施の形態に係る半導体装置の上面図を示し、図3(b)に図3(a)においてC方向から見た半導体装置の断面図を示す。   FIG. 3A shows a top view of the semiconductor device according to this embodiment, and FIG. 3B shows a cross-sectional view of the semiconductor device viewed from the C direction in FIG.

図3において符号210で示される半導体装置において、実施の形態2の半導体装置110と異なる点は放熱板218である。したがって、放熱板218について説明する。   In the semiconductor device denoted by reference numeral 210 in FIG. 3, a different point from the semiconductor device 110 of the second embodiment is a heat sink 218. Therefore, the heat sink 218 will be described.

放熱板218は、少なくとも基板216の裏面220のキャビティ222の周縁部と対向する部分から半導体装置210の側面238とを連絡する、はんだ230を介して基板216と接合する面(接合面)232に形成された複数の溝240を有する。溝240は、基板216と放熱板218の間から外に移動しようとするはんだ230のフラックスを側面238に案内し、キャビティ222から噴出するフラックス量を抑制する役割を果たす。その結果、基板216と放熱板218のはんだ230による接合時にキャビティ222から飛散するはんだの量が抑制される。   The heat radiating plate 218 is connected to a surface (joint surface) 232 that is joined to the substrate 216 via the solder 230 and communicates with the side surface 238 of the semiconductor device 210 from a portion facing the peripheral edge of the cavity 222 on the back surface 220 of the substrate 216. A plurality of grooves 240 are formed. The groove 240 plays a role of guiding the flux of the solder 230 that is about to move from between the substrate 216 and the heat sink 218 to the side surface 238 and suppressing the amount of flux ejected from the cavity 222. As a result, the amount of solder scattered from the cavity 222 when the substrate 216 and the heat sink 218 are joined by the solder 230 is suppressed.

本実施の形態の半導体装置は、実施の形態2とは異なり放熱板の裏面に貫通穴の開口が形成されていないため、放熱板の裏面に他の半導体装置の構成要素を取り付けることができる。   Unlike the second embodiment, the semiconductor device of the present embodiment has no through-hole opening formed on the back surface of the heat sink, so that other semiconductor device components can be attached to the back surface of the heat sink.

実施の形態4.
本実施の形態の半導体装置は、実施の形態2が放熱板の接合面から裏面を連絡する貫通穴を有するのに対し、放熱板の接合面から放熱板の側面を連絡する貫通穴を有することに特徴がある。
Embodiment 4 FIG.
The semiconductor device of the present embodiment has a through hole that communicates the side surface of the heat sink from the joint surface of the heat sink, whereas the second embodiment has a through hole that communicates the back surface from the joint surface of the heat sink. There is a feature.

図4(a)に本実施の形態に係る半導体装置の上面図を示し、図4(b)に図4(a)においてD方向から見た半導体装置の断面図を示す。   FIG. 4A shows a top view of the semiconductor device according to this embodiment, and FIG. 4B shows a cross-sectional view of the semiconductor device viewed from the D direction in FIG. 4A.

図4において符号310で示される半導体装置において、実施の形態2の半導体装置110と異なる点は放熱板318である。したがって、放熱板318について説明する。 In the semiconductor device denoted by reference numeral 310 in FIG. 4, a different point from the semiconductor device 110 of the second embodiment is a heat sink 318. Therefore, the heat sink 318 will be described.

放熱板318は、少なくとも基板316の裏面320のキャビティ322の周縁部と対向する部分から半導体装置310の側面338とを連絡する複数の貫通穴342を有する。貫通穴342は、実施の形態2の半導体装置110の複数の貫通穴126と同様に機能し、基板316と放熱板318のはんだ330による接合時にキャビティ322から飛散するはんだの量を抑制する。   The heat radiating plate 318 has a plurality of through holes 342 that communicate with the side surface 338 of the semiconductor device 310 from at least a portion of the back surface 320 of the substrate 316 facing the peripheral edge of the cavity 322. The through hole 342 functions in the same manner as the plurality of through holes 126 of the semiconductor device 110 of the second embodiment, and suppresses the amount of solder scattered from the cavity 322 when the substrate 316 and the heat sink 318 are joined by the solder 330.

本実施の形態は、半導体装置のサイズが小さい場合に有効である。放熱板の接合面から側面に向かうフラックスを移動させるための流路を形成するのは実施の形態3の溝と同様であるが、本実施の形態の放熱板は該流路を貫通穴で構成することにより、基板に対する十分な大きさの接合面を確保している。実施の形態3において半導体装置のサイズが小さくなると、接合面に対する溝が占める面積が増え、基板と実質的に接合する面が減少することになる。放熱板と基板の実質的な接合面が減少すると、電気的または熱的な接続が十分に行われずに、半導体装置が十分な機能を果たせない場合がある。   This embodiment is effective when the size of the semiconductor device is small. The flow path for moving the flux from the joining surface of the heat sink to the side is formed in the same manner as the groove of the third embodiment, but the heat sink of the present embodiment is configured with a through hole. By doing so, a sufficiently large bonding surface with respect to the substrate is secured. When the size of the semiconductor device is reduced in the third embodiment, the area occupied by the groove with respect to the bonding surface increases, and the surface substantially bonded to the substrate decreases. When the substantial joint surface between the heat sink and the substrate is reduced, electrical or thermal connection may not be sufficiently performed, and the semiconductor device may not perform a sufficient function.

ここまでは、半導体装置の製造におけるはんだの溶融中、基板のキャビティから噴出するフラックスの量を抑制し、それにより、キャビティから飛散するはんだの量を抑制し、その結果、基板の主面に付着するはんだの量を抑制することができる構造の半導体装置を説明してきた。ここからは、基板の主面に付着するはんだの量を抑制することができる半導体装置の製造方法について説明する。   Up to this point, during the melting of solder in the manufacture of semiconductor devices, the amount of flux ejected from the cavity of the substrate is suppressed, thereby suppressing the amount of solder scattered from the cavity and, as a result, adhering to the main surface of the substrate. A semiconductor device having a structure capable of suppressing the amount of solder to be processed has been described. From here, a method for manufacturing a semiconductor device capable of suppressing the amount of solder adhering to the main surface of the substrate will be described.

以下、説明する半導体装置の製造方法は、実施の形態1〜4に係る半導体装置を含む、いわゆるキャビティダウン型の半導体装置の製造方法である。したがって、半導体装置の構成要素の説明に関しては省略する。   The semiconductor device manufacturing method described below is a so-called cavity down type semiconductor device manufacturing method including the semiconductor devices according to the first to fourth embodiments. Therefore, the description of the components of the semiconductor device is omitted.

実施の形態5.
図5(a)に本実施の形態の製造方法において製造中の半導体装置の上面図を示し、図5(b)に図5(a)においてE方向から見た半導体装置の断面図を示す。
Embodiment 5. FIG.
FIG. 5A shows a top view of the semiconductor device being manufactured in the manufacturing method of the present embodiment, and FIG. 5B shows a cross-sectional view of the semiconductor device viewed from the E direction in FIG. 5A.

本実施の形態の半導体装置の製造方法においては、基板416と放熱板418の接合中(はんだ430の溶融中)、基板416のキャビティ422から飛散するはんだ430の基板416の主面424への付着を防止するために、基板416の主面424上に付着防止部材444が載置される。防止部材444は、基板416に対して脱着可能なテープやシール、または膜などであって、少なくともはんだ430が付着すると不都合な部分、例えば図5に示すようにキャビティ422周縁のボンディングワイヤが接続される部分(図1〜4参照。)に貼り付けられる。当然ながら、防止部材444は、はんだ430の溶融のための高熱環境に耐えうる耐熱性を有する。防止部材444により、キャビティ422から飛散するはんだ430の基板416の主面424への付着が防止される。   In the manufacturing method of the semiconductor device of this embodiment, the solder 430 scattered from the cavity 422 of the substrate 416 is adhered to the main surface 424 of the substrate 416 during the bonding of the substrate 416 and the heat sink 418 (during melting of the solder 430). In order to prevent this, the adhesion preventing member 444 is placed on the main surface 424 of the substrate 416. The prevention member 444 is a tape, a seal, or a film that can be attached to and detached from the substrate 416. At least a part that is inconvenient when the solder 430 is attached, for example, a bonding wire around the cavity 422 as shown in FIG. (See FIGS. 1 to 4). Of course, the prevention member 444 has heat resistance that can withstand a high heat environment for melting the solder 430. The prevention member 444 prevents the solder 430 scattered from the cavity 422 from adhering to the main surface 424 of the substrate 416.

実施の形態6.
図6(a)に本実施の形態の製造方法において製造中の半導体装置の上面図を示し、図6(b)に図6(a)においてF方向から見た半導体装置の断面図を示す。
Embodiment 6 FIG.
FIG. 6A shows a top view of the semiconductor device being manufactured in the manufacturing method of the present embodiment, and FIG. 6B shows a cross-sectional view of the semiconductor device viewed from the F direction in FIG. 6A.

本実施の形態の半導体装置の製造方法においては、基板516と放熱板518の接合中(はんだ530の溶融中)、基板516のキャビティ522から飛散するはんだ530の基板516の主面524への付着を防止するために、言い換えるとキャビティ522から飛散するはんだ530をキャビティ522から出さないように捕獲するために、キャビティ522が部材546で覆われる。部材546は、空気が通過可能な耐熱性に優れた、例えば金属ウール、カーボンファイバー、耐熱紙、耐熱繊維などで構成されている。部材546を空気が通過可能なものとする理由は、気化してキャビティ522に噴出するフラックスを外に逃がすためである。捕獲部材546により、キャビティ522から飛散するはんだ530は捕獲され、その結果、キャビティ522から飛散するはんだ530の基板516の主面524への付着が防止される。   In the manufacturing method of the semiconductor device of this embodiment, the solder 530 scattered from the cavity 522 of the substrate 516 is adhered to the main surface 524 of the substrate 516 during the joining of the substrate 516 and the heat sink 518 (during melting of the solder 530). In other words, the cavity 522 is covered with the member 546 in order to capture the solder 530 scattered from the cavity 522 so as not to exit the cavity 522. The member 546 is made of, for example, metal wool, carbon fiber, heat-resistant paper, heat-resistant fiber, etc., which are excellent in heat resistance through which air can pass. The reason why air can pass through the member 546 is to release the flux that is vaporized and jetted into the cavity 522 to the outside. The solder 530 scattered from the cavity 522 is captured by the capture member 546, and as a result, the solder 530 scattered from the cavity 522 is prevented from adhering to the main surface 524 of the substrate 516.

実施の形態7.
図7(a)に本実施の形態の製造方法において製造中の半導体装置の上面図を示し、図7(b)に図7(a)においてG方向から見た半導体装置の断面図を示す。
Embodiment 7 FIG.
FIG. 7A shows a top view of the semiconductor device being manufactured in the manufacturing method of the present embodiment, and FIG. 7B shows a cross-sectional view of the semiconductor device viewed from the G direction in FIG. 7A.

本実施の形態の半導体装置の製造方法においては、基板616と放熱板618の接合中(はんだ630の溶融中)、基板616のキャビティ622から飛散するはんだ630の基板616の主面624への付着を防止するために、言い換えるとキャビティ622からはんだ630を飛散させる原因の基板616と放熱板618の間からキャビティ622に噴出するはんだ630の液状のフラックスを吸収するために、キャビティ622の内周面に沿ってフラックスを吸収する複数の吸収部材648が配置される。吸収部材648は、例えば毛細管や毛細管現象を利用して液体を吸収できるもの(例えば、スポンジ状のもの)が該当する。吸収部材648により板616と放熱板618の間からキャビティ622に噴出するはんだ630の液状のフラックスが吸収されることにより、キャビティ622から飛散するはんだ630の量が減少し、その結果、キャビティ622から飛散するはんだ630の基板616の主面624への付着が抑制される。   In the manufacturing method of the semiconductor device of the present embodiment, the solder 630 scattered from the cavity 622 of the substrate 616 is adhered to the main surface 624 of the substrate 616 during the bonding of the substrate 616 and the heat sink 618 (melting of the solder 630). In other words, in order to absorb the liquid flux of the solder 630 ejected from the space between the substrate 616 and the heat sink 618 that causes the solder 630 to scatter from the cavity 622, the inner peripheral surface of the cavity 622 is absorbed. A plurality of absorbing members 648 that absorb the flux are disposed along the line. The absorbing member 648 corresponds to, for example, a member that can absorb a liquid using a capillary tube or a capillary phenomenon (for example, a sponge member). The absorbing member 648 absorbs the liquid flux of the solder 630 ejected from between the plate 616 and the heat radiating plate 618 to the cavity 622, thereby reducing the amount of the solder 630 scattered from the cavity 622, and as a result, from the cavity 622. Adhesion of the scattered solder 630 to the main surface 624 of the substrate 616 is suppressed.

実施の形態8.
図8に本実施の形態の製造方法において製造中の半導体装置を示す。
Embodiment 8 FIG.
FIG. 8 shows a semiconductor device being manufactured in the manufacturing method of the present embodiment.

本実施の形態の半導体装置の製造方法においては、基板716と放熱板718の接合中(基板716と放熱板718を接合するはんだの溶融中)、基板716のキャビティ722から飛散するはんだの基板716の主面724への付着を防止するために、キャビティ722から飛散するはんだを半導体装置710から離れるように吹き飛ばす気流750を発生させる送風装置752が配置される。気流750は、基板716の主面724と略平行に流れている。気流750により、キャビティ722から飛散するはんだが半導体装置710から離れるように吹き飛ばされ、その結果、キャビティ722から飛散するはんだの基板716の主面724への付着が抑制される。   In the manufacturing method of the semiconductor device of this embodiment, the substrate 716 of the solder scattered from the cavity 722 of the substrate 716 during the bonding of the substrate 716 and the heat dissipation plate 718 (during melting of the solder for bonding the substrate 716 and the heat dissipation plate 718). In order to prevent the main surface 724 from adhering to the main surface 724, a blower 752 that generates an airflow 750 that blows away the solder scattered from the cavity 722 away from the semiconductor device 710 is disposed. The airflow 750 flows substantially parallel to the main surface 724 of the substrate 716. The solder scattered from the cavity 722 is blown away from the semiconductor device 710 by the air current 750, and as a result, the adhesion of the solder scattered from the cavity 722 to the main surface 724 of the substrate 716 is suppressed.

また、実施の形態8の改良例として、図9に示すように、キャビティ822上に吸引装置854によって上昇気流856を発生させ、上昇気流856によってキャビティ822から飛散するはんだ830を半導体装置830から離れるように吹き飛ばすようにしてもよい。厳密には、キャビティ822から飛散したはんだ830は、吸引装置854によって吸引される。   As an improved example of the eighth embodiment, as shown in FIG. 9, an ascending air current 856 is generated on the cavity 822 by the suction device 854, and the solder 830 scattered from the cavity 822 by the ascending air current 856 is separated from the semiconductor device 830. You may make it blow away. Strictly speaking, the solder 830 scattered from the cavity 822 is sucked by the suction device 854.

実施の形態9.
図10に本実施の形態の製造方法において製造中の半導体装置を示す。
Embodiment 9 FIG.
FIG. 10 shows a semiconductor device being manufactured in the manufacturing method of the present embodiment.

本実施の形態の半導体装置の製造方法においては、基板916と放熱板918の接合中(はんだ930の溶融中)における基板916のキャビティ922から飛散するはんだ930の基板916の主面924への付着を防止するために、基板916と放熱板918の接合を、はんだ930のフラックスの蒸気圧より高い内圧のチャンバー958内で行う。キャビティ922からのはんだ930の飛散は、基板916と放熱板918の間ではんだ930のペースト状のフラックスが急激に気化して体積膨張することによる影響が大きい。本実施の形態では、はんだ930のフラックスが気化する温度における蒸気圧よりチャンバー958の内圧を高くすることにより、該フラックスの急激な体積膨張を抑制し、それにより、キャビティ922から基板916の主面924に飛散するはんだ930の量を低くしている。   In the method for manufacturing a semiconductor device of this embodiment, the solder 930 scattered from the cavity 922 of the substrate 916 during the bonding of the substrate 916 and the heat sink 918 (during melting of the solder 930) to the main surface 924 of the substrate 916. In order to prevent this, the substrate 916 and the heat radiating plate 918 are joined in a chamber 958 having an internal pressure higher than the vapor pressure of the solder 930 flux. The scattering of the solder 930 from the cavity 922 is greatly influenced by the volume expansion due to the rapid evaporation of the paste-like flux of the solder 930 between the substrate 916 and the heat sink 918. In the present embodiment, the internal pressure of the chamber 958 is made higher than the vapor pressure at the temperature at which the flux of the solder 930 vaporizes, thereby suppressing rapid volume expansion of the flux, and thereby the main surface of the substrate 916 from the cavity 922. The amount of solder 930 that scatters to 924 is reduced.

実施の形態10.
図11に本実施の形態の製造方法において製造中の半導体装置を示す。
Embodiment 10 FIG.
FIG. 11 shows a semiconductor device being manufactured in the manufacturing method of the present embodiment.

本実施の形態の半導体装置の製造方法においては、基板1016と放熱板1018の接合中(はんだ1030の溶融中)、基板1016のキャビティ1022から飛散するはんだ1030の基板1016の主面1024への付着を防止するために、裏面1020を上方に向けた状態で基板1016を配置し、上方から放熱板1018を基板1016にはんだ1030で接合する。キャビティ1022から飛散するはんだ1030は、重力によって落下する。これにより、キャビティ1022から飛散するはんだ1030の基板1016の主面1024への付着が抑制される。   In the manufacturing method of the semiconductor device of this embodiment, the solder 1030 scattered from the cavity 1022 of the substrate 1016 is adhered to the main surface 1024 of the substrate 1016 during the bonding of the substrate 1016 and the heat sink 1018 (during melting of the solder 1030). In order to prevent this, the substrate 1016 is disposed with the back surface 1020 facing upward, and the heat radiating plate 1018 is joined to the substrate 1016 with solder 1030 from above. The solder 1030 scattered from the cavity 1022 falls due to gravity. Thereby, adhesion of the solder 1030 scattered from the cavity 1022 to the main surface 1024 of the substrate 1016 is suppressed.

以上、いくつかの実施の形態を示して本発明を説明したが、本発明はこれらの実施の形態に限定されない。例えば、基板と接合されるものは放熱板でなくてもよく、基板と半導体チップ(台座)を支持するものであればよい。また、半導体チップは、台座を介して放熱板に搭載されるが、直接放熱板に搭載してもよい。さらに、実施の形態2〜4の構造を全て有する半導体装置であってもよい。   While the present invention has been described with reference to some embodiments, the present invention is not limited to these embodiments. For example, what is joined to the substrate does not have to be a heat sink, and may be anything that supports the substrate and the semiconductor chip (pedestal). Moreover, although a semiconductor chip is mounted on a heat sink via a pedestal, it may be mounted directly on the heat sink. Further, it may be a semiconductor device having all the structures of the second to fourth embodiments.

最後に、上述の実施の形態は、併用して実施することが可能である。例えば、実施の形態1〜4の構造を有する半導体装置の製造に実施の形態5〜10の製造方法を実施することが可能である。併用した場合、キャビティから噴出するはんだの基板の主面への付着がより抑制される。   Finally, the above-described embodiments can be implemented in combination. For example, the manufacturing method of the fifth to tenth embodiments can be carried out for the manufacture of the semiconductor device having the structure of the first to fourth embodiments. When used together, the adhesion of the solder ejected from the cavity to the main surface of the substrate is further suppressed.

本発明の実施の形態1に係る半導体装置を示す図である。1 is a diagram illustrating a semiconductor device according to a first embodiment of the present invention. 本発明の実施の形態2に係る半導体装置を示す図である。It is a figure which shows the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態3に係る半導体装置を示す図である。It is a figure which shows the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態4に係る半導体装置を示す図である。It is a figure which shows the semiconductor device which concerns on Embodiment 4 of this invention. 本発明の実施の形態5に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on Embodiment 5 of this invention. 本発明の実施の形態6に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on Embodiment 6 of this invention. 本発明の実施の形態7に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on Embodiment 7 of this invention. 本発明の実施の形態8に係る半導体装置の製造方法の一例を示す図である。It is a figure which shows an example of the manufacturing method of the semiconductor device which concerns on Embodiment 8 of this invention. 本発明の実施の形態8に係る半導体装置の製造方法の別例を示す図である。It is a figure which shows another example of the manufacturing method of the semiconductor device which concerns on Embodiment 8 of this invention. 本発明の実施の形態9に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on Embodiment 9 of this invention. 本発明の実施の形態10に係る半導体装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the semiconductor device which concerns on Embodiment 10 of this invention.

符号の説明Explanation of symbols

10 半導体装置、 12 半導体部品(半導体チップ)、 16 基板、 18 支持体(放熱板)、 20 裏面、 22 収容穴(キャビティ)、 24 主面、 26 貫通穴、 30 はんだ
DESCRIPTION OF SYMBOLS 10 Semiconductor device, 12 Semiconductor components (semiconductor chip), 16 Board | substrate, 18 Support body (heat sink), 20 Back surface, 22 Housing hole (cavity), 24 Main surface, 26 Through-hole, 30 Solder

Claims (8)

半導体部品の収容穴が形成された基板の裏面と支持体がはんだによって接合され、収容穴を介して見える支持体の部分に半導体部品が搭載される半導体装置であって、
基板は、少なくとも収容穴の周縁に裏面と該裏面と対向する主面を連絡する貫通穴を有することを特徴とする半導体装置。
A semiconductor device in which a back surface of a substrate on which a housing hole for a semiconductor component is formed and a support are joined by solder, and the semiconductor component is mounted on a portion of the support that can be seen through the housing hole,
The substrate has a through hole that connects at least a back surface and a main surface facing the back surface at a periphery of the accommodation hole.
半導体部品の収容穴が形成された基板の裏面と支持体がはんだによって接合され、収容穴を介して見える支持体の部分に半導体部品が搭載される半導体装置であって、
支持体は、少なくとも基板の裏面の収容穴周縁部と対向する部分と基板に非接合の部分とを連絡する貫通穴または溝の少なくとも1つを有することを特徴とする半導体装置。
A semiconductor device in which a back surface of a substrate on which a housing hole for a semiconductor component is formed and a support are joined by solder, and the semiconductor component is mounted on a portion of the support that can be seen through the housing hole,
The support body has at least one of a through hole or a groove that communicates at least a portion facing the peripheral portion of the accommodation hole on the back surface of the substrate and a portion not joined to the substrate.
半導体部品の収容穴が形成された基板の裏面と支持体がはんだによって接合され、収容穴を介して見える支持体の部分に半導体部品が搭載される半導体装置の製造方法であって、
基板の裏面と支持体をはんだで接合するとき、収容穴から噴出するはんだの基板の主面への付着を防止するための部材を基板の主面上に載置することを特徴とする半導体装置の製造方法。
A method of manufacturing a semiconductor device in which a back surface of a substrate on which a housing hole for a semiconductor component is formed and a support are joined by solder, and the semiconductor component is mounted on a portion of the support that can be seen through the housing hole,
A semiconductor device characterized in that a member for preventing adhesion of solder ejected from a receiving hole to a main surface of a substrate when the back surface of the substrate and a support are bonded to each other is placed on the main surface of the substrate. Manufacturing method.
半導体部品の収容穴が形成された基板の裏面と支持体がはんだによって接合され、収容穴を介して見える支持体の部分に半導体部品が搭載される半導体装置の製造方法であって、
基板の裏面と支持体をはんだで接合するとき、空気が通過可能であって収容穴から噴出するはんだを捕獲するための部材で収容穴を覆うことを特徴とする半導体装置の製造方法。
A method of manufacturing a semiconductor device in which a back surface of a substrate on which a housing hole for a semiconductor component is formed and a support are joined by solder, and the semiconductor component is mounted on a portion of the support that can be seen through the housing hole,
A method for manufacturing a semiconductor device, wherein when a back surface of a substrate and a support are joined with solder, the housing hole is covered with a member that allows air to pass therethrough and captures the solder ejected from the housing hole.
半導体部品の収容穴が形成された基板の裏面と支持体がはんだによって接合され、収容穴を介して見える支持体の部分に半導体部品が搭載される半導体装置の製造方法であって、
基板の裏面と支持体をはんだで接合するとき、基板と支持体の間から収容穴に溶出するはんだのフラックスを吸収するための吸収部材を収容穴に配置することを特徴とする半導体装置の製造方法。
A method of manufacturing a semiconductor device in which a back surface of a substrate on which a housing hole for a semiconductor component is formed and a support are joined by solder, and the semiconductor component is mounted on a portion of the support that can be seen through the housing hole,
Manufacturing of a semiconductor device characterized in that when a back surface of a substrate and a support are joined with solder, an absorbing member for absorbing solder flux eluted from between the substrate and the support into the accommodation hole is disposed in the accommodation hole. Method.
半導体部品の収容穴が形成された基板の裏面と支持体がはんだによって接合され、収容穴を介して見える支持体の部分に半導体部品が搭載される半導体装置の製造方法であって、
基板の裏面と支持体をはんだで接合するとき、送風手段または吸引手段を用いて収容穴から噴出するはんだを半導体装置から離れるように吹き飛ばすまたは吸引することを特徴とする半導体装置の製造方法。
A method of manufacturing a semiconductor device in which a back surface of a substrate on which a housing hole for a semiconductor component is formed and a support are joined by solder, and the semiconductor component is mounted on a portion of the support that can be seen through the housing hole,
A method of manufacturing a semiconductor device, characterized in that when the back surface of the substrate and the support are joined with solder, the solder ejected from the accommodation hole is blown away or sucked away from the semiconductor device using a blowing means or a suction means.
半導体部品の収容穴が形成された基板の裏面と支持体がはんだによって接合され、収容穴を介して見える支持体の部分に半導体部品が搭載される半導体装置の製造方法であって、
基板の裏面と支持体のはんだによる接合を、はんだのフラックスの蒸気圧より高い圧力下で行うことを特徴とする半導体装置の製造方法。
A method of manufacturing a semiconductor device in which a back surface of a substrate on which a housing hole for a semiconductor component is formed and a support are joined by solder, and the semiconductor component is mounted on a portion of the support that can be seen through the housing hole,
A method for manufacturing a semiconductor device, comprising: joining a back surface of a substrate and a support by solder under a pressure higher than a vapor pressure of a solder flux.
半導体部品の収容穴が形成された基板の裏面と支持体がはんだによって接合され、収容穴を介して見える支持体の部分に半導体部品が搭載される半導体装置の製造方法であって、
基板の裏面と支持体をはんだで接合するとき、裏面を上方に向けた状態で基板を配置して上方から支持体を基板にはんだで接合することを特徴とする半導体装置の製造方法。
A method of manufacturing a semiconductor device in which a back surface of a substrate on which a housing hole for a semiconductor component is formed and a support are joined by solder, and the semiconductor component is mounted on a portion of the support that can be seen through the housing hole,
A method of manufacturing a semiconductor device, wherein when a back surface of a substrate and a support are joined by solder, the substrate is arranged with the back surface facing upward, and the support is joined to the substrate from above by solder.
JP2005203883A 2005-07-13 2005-07-13 Manufacturing method of semiconductor device Expired - Fee Related JP4842574B2 (en)

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JPH0888245A (en) * 1994-09-14 1996-04-02 Nec Corp Semiconductor device
JPH0897329A (en) * 1994-09-28 1996-04-12 Ibiden Co Ltd Device having electronic device therein
JPH08250847A (en) * 1995-03-09 1996-09-27 Toyota Motor Corp Soldering method for electronic component
JP2000114608A (en) * 1998-10-06 2000-04-21 Idotai Tsushin Sentan Gijutsu Kenkyusho:Kk Method for mounting circuit board and mounting structure for circuit board
JP2000164631A (en) * 1998-11-27 2000-06-16 Matsushita Electric Ind Co Ltd Method for mounting electronic components having bump
JP2003332811A (en) * 2002-05-14 2003-11-21 Matsushita Electric Ind Co Ltd Integrated circuit microwave, its manufacturing method and radio equipment
JP2003347493A (en) * 2002-05-24 2003-12-05 Denso Corp Mounting method for electronic part and contamination- preventing chip used for it
JP2004253491A (en) * 2003-02-19 2004-09-09 Matsushita Electric Ind Co Ltd Reflow soldering method and reflow soldering equipment
JP2004273927A (en) * 2003-03-11 2004-09-30 Mitsubishi Electric Corp Semiconductor package
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Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04280655A (en) * 1991-03-08 1992-10-06 Furukawa Electric Co Ltd:The High density hybrid circuit board
JPH05315467A (en) * 1992-05-06 1993-11-26 Mitsubishi Electric Corp Hybrid integrated circuit device
JPH0888245A (en) * 1994-09-14 1996-04-02 Nec Corp Semiconductor device
JPH0897329A (en) * 1994-09-28 1996-04-12 Ibiden Co Ltd Device having electronic device therein
JPH08250847A (en) * 1995-03-09 1996-09-27 Toyota Motor Corp Soldering method for electronic component
JP2000114608A (en) * 1998-10-06 2000-04-21 Idotai Tsushin Sentan Gijutsu Kenkyusho:Kk Method for mounting circuit board and mounting structure for circuit board
JP2000164631A (en) * 1998-11-27 2000-06-16 Matsushita Electric Ind Co Ltd Method for mounting electronic components having bump
JP2003332811A (en) * 2002-05-14 2003-11-21 Matsushita Electric Ind Co Ltd Integrated circuit microwave, its manufacturing method and radio equipment
JP2003347493A (en) * 2002-05-24 2003-12-05 Denso Corp Mounting method for electronic part and contamination- preventing chip used for it
JP2004253491A (en) * 2003-02-19 2004-09-09 Matsushita Electric Ind Co Ltd Reflow soldering method and reflow soldering equipment
JP2004273927A (en) * 2003-03-11 2004-09-30 Mitsubishi Electric Corp Semiconductor package
JP2004296565A (en) * 2003-03-26 2004-10-21 Sumitomo Metal Electronics Devices Inc Method for manufacturing package for housing semiconductor element

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