JPS6050354B2 - Resin-encapsulated semiconductor device - Google Patents
Resin-encapsulated semiconductor deviceInfo
- Publication number
- JPS6050354B2 JPS6050354B2 JP55161175A JP16117580A JPS6050354B2 JP S6050354 B2 JPS6050354 B2 JP S6050354B2 JP 55161175 A JP55161175 A JP 55161175A JP 16117580 A JP16117580 A JP 16117580A JP S6050354 B2 JPS6050354 B2 JP S6050354B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- insulating layer
- sealed
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】
本発明は、放熱板等への取りつけを簡便になすことのて
きる樹脂封止型半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a resin-sealed semiconductor device that can be easily attached to a heat sink or the like.
樹脂封止型半導体装置は、通常リードフレームを用いて
半導体素子組立構体を形成し、これを樹脂によつて封止
した構造となつている。この樹脂封止型半導体装置にお
ける１つの問題は、成型用・、４Ｊ−ｌｉ−−ｉ↓゛−
゛、ｌ−Ｌ−７ｊｌ。の放散が十分でなく、電力損失が
１０ワット程度に達する電力用半導体装置の実現が困難
なことてある。この問題を解決することのできる構造と
して、リードフレームの半導体素子接着部に放熱板とし
ての機能を発揮させるようにした構造が提案されるに至
つている。第１図は、かかる構造を具備する従来の樹脂
封止型半導体装置の構造の例ならびにこれを外部放熱板
へとりつける状態を説明するための図であ’る。A resin-sealed semiconductor device usually has a structure in which a semiconductor element assembly structure is formed using a lead frame, and this is sealed with resin. One problem with this resin-sealed semiconductor device is that the molding...4J-li-i↓゛-
゛, l-L-7jl. It is sometimes difficult to realize a power semiconductor device in which the power loss reaches about 10 watts due to insufficient dissipation. As a structure capable of solving this problem, a structure has been proposed in which the semiconductor element bonding portion of the lead frame functions as a heat sink. FIG. 1 is a diagram for explaining an example of the structure of a conventional resin-sealed semiconductor device having such a structure and a state in which it is attached to an external heat sink.
樹脂封止型半導体装置１は銅などのように熱伝導度の高
い金属板で形成したリードフレームの基板支持部２へ半
導体素子（基板）３を鑞付４を用いて接着し、さらに、
半導体素子電極を外部りード５へ金属細線６で接続し、
こののち、基板支持部２の裏面を露呈させる関係を成立
させて樹脂７で封止して形成されている。In the resin-sealed semiconductor device 1, a semiconductor element (substrate) 3 is bonded to a substrate support portion 2 of a lead frame made of a metal plate with high thermal conductivity such as copper using a solder 4, and further,
Connect the semiconductor element electrode to the external lead 5 with a thin metal wire 6,
Thereafter, a relationship is established in which the back surface of the substrate support section 2 is exposed, and the substrate support section 2 is sealed with a resin 7.
基板支持部２は半導体素子の１つの電極たとえば、トラ
ンジスタの場合にはコレクタ電極となつている。したが
つて、基板支持部２から外部へ延びる外部リード８はト
ランジスタの場合にはコレクタリードとなる。なお、９
は樹脂封止型半導体装置をねじ等により外部放熱板へと
りつけるためのとりつけ孔である。以上の構成からなる
樹脂封止型半導体装置では、基板支持部２が放熱板を兼
ねるところとなり、したがつて、この基板支持部２を外
部放熱板へ熱的に結合するならば、動作時に発生する熱
を効果的に放散することが可能になる。しかしながら、
すでに説明したように、基板支持部２は半導体素子の１
つの電極でもあるため、外部放熱板へのとりつけに際し
て両者間を気的に絶縁する必要があり、図示するように
、基板支持部２と外部放熱板１０との間に熱伝導を損う
ことのない程度の厚みをもつ絶縁シート１１を介在させ
ることが不可避となる。かかる構造によれば、電力損失
に関する問題の解決ははかれるものの、上記のように実
装に際してわずられしさが生じる。また、絶縁シートの
位置決めが不正確であると絶縁性が損われ、短絡事故を
起すおそれもあつた。本発明は、上述した従来の電力用
樹脂封止型半導体装置の問題点を排除することのてきる
樹脂封止型半導体装置を提供するものてあり、半導体素
子が接着される基板支持部の、少くとも半導体素子直下
に位置する部分を金属層、絶縁層ならびに金属層の３相
構造からなる積層板となし、半導体素子が接着される側
の金属層と樹脂封止ののちに表面が外部へ露呈する金属
層との間を電気的に絶縁しておくことよつて、従来構造
ては実装時に必要であつた絶縁シートを不要とした構造
に特徴がある。The substrate support portion 2 serves as one electrode of a semiconductor element, for example, a collector electrode in the case of a transistor. Therefore, the external lead 8 extending from the substrate support part 2 to the outside becomes a collector lead in the case of a transistor. In addition, 9
is a mounting hole for mounting the resin-sealed semiconductor device to an external heat sink using screws or the like. In the resin-sealed semiconductor device having the above configuration, the substrate support portion 2 also serves as a heat sink. Therefore, if the substrate support portion 2 is thermally coupled to an external heat sink, the This makes it possible to effectively dissipate heat. however,
As already explained, the substrate support part 2 supports one of the semiconductor elements.
Since the electrodes are two electrodes, it is necessary to electrically insulate between them when attaching them to an external heat sink. It is unavoidable to interpose an insulating sheet 11 having a certain thickness. Although such a structure solves the problem of power loss, it is difficult to implement as described above. Furthermore, if the positioning of the insulating sheet was inaccurate, the insulation properties would be impaired, and there was a risk that a short circuit would occur. The present invention provides a resin-sealed semiconductor device that can eliminate the problems of the conventional resin-sealed semiconductor device for electric power as described above. At least the part located directly below the semiconductor element is made into a laminate consisting of a three-phase structure of a metal layer, an insulating layer, and a metal layer, and the surface is exposed to the outside after sealing with the metal layer and resin on the side to which the semiconductor element is bonded. By electrically insulating the exposed metal layer, the structure is characterized by eliminating the need for an insulating sheet, which was required in conventional structures during mounting.
以下に図面を参照して本発明の樹脂封止型半導体装置に
ついて説明する。The resin-sealed semiconductor device of the present invention will be described below with reference to the drawings.
第２図は、本発明にかかる樹脂封止型半導体装置の１実
施例を示す断面図であり図示するように、リードフレー
ムの基板支持部２が、熱電導率の高い第１金属層１２、
絶縁層１３ならびに第２金属層１４を積層した積層板構
造となつている。FIG. 2 is a sectional view showing an embodiment of the resin-sealed semiconductor device according to the present invention.
It has a laminated plate structure in which an insulating layer 13 and a second metal layer 14 are laminated.
この部分を除いては第１図で示た従来の樹脂封止型半導
体装置と構造上の差異はない。ところで、第１金属層と
第２金属層との間に存在する絶縁層１３は、リードフレ
ームの構成要素の１つであり、半導体素子を接着するた
めの熱処理温度ても特性が劣化するものであつてはなら
ない。この要件をみたす絶縁層としては例えばポリイミ
ド樹脂層が挙げられる。以上の構造をもつ本発明の樹脂
封止型半導体装置では、絶縁層１３によつて第１金属層
と第２金属層が電気的に絶縁されているため、これを外
部放熱板へとりつけるにあたり、第２金属層１４の面を
直接外部放熱板へ当接させたとしても何等支障をきたす
ことがない。Other than this part, there is no structural difference from the conventional resin-sealed semiconductor device shown in FIG. By the way, the insulating layer 13 existing between the first metal layer and the second metal layer is one of the components of the lead frame, and its characteristics deteriorate even at the heat treatment temperature for bonding semiconductor elements. It shouldn't be. An example of an insulating layer that satisfies this requirement is a polyimide resin layer. In the resin-sealed semiconductor device of the present invention having the above structure, the first metal layer and the second metal layer are electrically insulated by the insulating layer 13, so when attaching it to an external heat sink, Even if the surface of the second metal layer 14 is brought into direct contact with the external heat sink, no problem will occur.
次に本発明の樹脂封止型半導体装置の製作条件の１実施
例を示す。Next, an example of manufacturing conditions for the resin-sealed semiconductor device of the present invention will be described.
先ず、Ｎｉめつきが施された厚さが０．４７０７７！の
銅板と、同じくＮｉめつきが施された厚さが０．８７７
１７７！の銅板とをポリイミド樹脂を接着剤として用い
て張り合わせ金属層一絶縁層一金属層の３層構造板を準
備し、これに打ち抜き加工を施しリードフレームを形成
する。First of all, the thickness of Ni plating is 0.47077! Copper plate with a thickness of 0.877, which is also plated with Ni.
177! A three-layer structural board consisting of a metal layer, an insulating layer, and a metal layer is prepared by pasting together a copper plate and a polyimide resin using polyimide resin as an adhesive, and punching is performed on this to form a lead frame.
リードフレームの外部リード部は肉薄の銅板側で形成す
ればよく、このため、肉厚の銅板は外部リード部では不
要である。第３図は、このようにして形成されたリード
フレームの基板支持部２へー辺が３Ｔ０ＴＬのトランジ
スタ素子３″を半田付けし、さらにベース電極にエミッ
タ電極を直径２００ｐｍのアルミニウム線６１，６２を
用いてベース用外部リード５１とエミッタ用外部リード
５２に接続することによつてトランジスタ組立構体を形
成する。The external lead portion of the lead frame may be formed on the thin copper plate side, and therefore, a thick copper plate is not necessary for the external lead portion. FIG. 3 shows that a transistor element 3'' with a side of 3T0TL is soldered to the substrate support part 2 of the lead frame thus formed, and an emitter electrode is connected to the base electrode using aluminum wires 61 and 62 with a diameter of 200 pm. By connecting the base external lead 51 and the emitter external lead 52, a transistor assembly structure is formed.
リードフレームには、上記の組立部が多数連結形成され
ており、全ての組立部においてトランジスタ組立構体を
形成したのち、これらを第２図で示したように樹脂封止
し、最後に個々に分断することによつてパワートランジ
スタが形成される。第４図は、かかる本発明の樹脂封止
型パワートランジスタの過渡熱抵抗特性を、同一の外形
寸法ならびチップサイズをもつ従来構造の樹脂封止型パ
ワートランジスタの過渡熱抵抗特性と比較した結果を示
す図である。The lead frame has many of the above-mentioned assembly parts connected together, and after forming the transistor assembly structure in all the assembly parts, these are sealed with resin as shown in Figure 2, and finally separated into individual parts. By doing so, a power transistor is formed. FIG. 4 shows the results of comparing the transient thermal resistance characteristics of the resin-sealed power transistor of the present invention with those of a conventionally structured resin-sealed power transistor having the same external dimensions and chip size. FIG.
縦軸は熱抵抗Ｒｔｈ（℃／゛Ｗ）、横軸は電力印加時間
（秒）を、また、Ａは本発明のものの過渡熱抵抗特性曲
線、Ｂは従来のものの過渡熱抵抗特性曲線である。図示
するところから明らかなように、本発明の樹脂封止型パ
ワートランジスタの特性は従来のものよりもわずかに劣
るところとなるが、実装時の絶縁シートの有無によつて
実際には従来のものと何等遜色のないものとなる。なお
、本発明の樹脂封止型半導体装置の電気絶縁度ならびに
放熱特性は、絶縁層を形成する絶縁物の種類と厚みによ
つて変化する。第５図は、絶縁層がポリイミド樹脂であ
るときの絶縁層の厚みと絶縁耐圧ならびに熱抵抗の関係
を示す図てあり、Ｘは絶縁耐圧と厚みの関係を、Ｙは熱
抵抗と厚みの関係を示す。絶縁耐圧は絶縁層の厚みが５
０μｍ以下になると著しく低下する。一方、熱抵抗は絶
縁層の厚みが１０μｍ程度を超えると急増する。したが
つて、得ようとする半導体装置の特性にもよるが、一般
的に言つて、絶縁層の厚みは５０〜１１０μｍ程度の範
囲に選定することがのぞましい。さらに、絶縁層中に気
泡あるいはピンホールが存在すると電気絶縁性が損われ
るところとなるが、絶縁層の一部を２０〜３０ｐｍ程度
のポリイミドシートとしたところ、気泡あるいはピンホ
ールを減少させることのできる顕著な効果のあることが
てきた。The vertical axis is the thermal resistance Rth (°C/゛W), the horizontal axis is the power application time (seconds), A is the transient thermal resistance characteristic curve of the present invention, and B is the transient thermal resistance characteristic curve of the conventional one. . As is clear from the diagram, the characteristics of the resin-sealed power transistor of the present invention are slightly inferior to conventional ones, but depending on the presence or absence of an insulating sheet during mounting, the characteristics of the resin-sealed power transistor of the present invention are actually superior to conventional ones. It will be no different from that. Note that the electrical insulation degree and heat dissipation characteristics of the resin-sealed semiconductor device of the present invention vary depending on the type and thickness of the insulator forming the insulating layer. Figure 5 shows the relationship between the thickness of the insulating layer, dielectric strength voltage, and thermal resistance when the insulating layer is made of polyimide resin, where X represents the relationship between dielectric strength voltage and thickness, and Y represents the relationship between thermal resistance and thickness. shows. The dielectric strength voltage is determined by the thickness of the insulating layer.
When it becomes 0 μm or less, it decreases significantly. On the other hand, the thermal resistance increases rapidly when the thickness of the insulating layer exceeds about 10 μm. Therefore, although it depends on the characteristics of the semiconductor device to be obtained, it is generally desirable to select the thickness of the insulating layer in the range of about 50 to 110 μm. Furthermore, if air bubbles or pinholes exist in the insulating layer, the electrical insulation will be impaired, but when a part of the insulating layer is made of a polyimide sheet with a thickness of about 20 to 30 pm, it is possible to reduce the air bubbles or pinholes. There are things that can be done that have remarkable effects.
また、絶縁層に接する金属板の面を酸化あるいは窒化さ
せることによつて電気絶縁度のよソー層の改善がはから
れること、同面を粗面化することによつて積層体の接着
力が高められることも確認された。以上説明したところ
から明らかなように、本発明の樹脂封止型半導体装置に
よれば、実装のための作業が著るしく簡略化されるとこ
ろとなり、半導装置の組立に大きな工業的価値を奏する
ものである。In addition, by oxidizing or nitriding the surface of the metal plate that is in contact with the insulating layer, the electrical insulation of the layer can be improved, and by roughening the same surface, the adhesive strength of the laminate can be improved. It was also confirmed that the As is clear from the above explanation, according to the resin-sealed semiconductor device of the present invention, the mounting work is significantly simplified, and it has great industrial value in the assembly of semiconductor devices. It is something to play.
第１図は従来の樹脂封止型電力用半導体装置の構造を示
す断面図、第２図は本発明の一実施例にかかる樹脂封止
型電力用半導体装置の構造を示す断面図、第３図は本発
明にかかるパワートランジスタ素子組立構体の斜視図、
第４図は本発明のパワートランジスタと従来のパワート
ランジスタとの過渡熱抵抗特性を比較して示した図、第
５図は絶縁層の厚みの変化と絶縁耐圧ならびに熱抵抗の
関係を示す図である。
２・・・・・・基板支持部、３・・・・・・半導体素子
、３″・・・・・トランジスタ素子、４・・・・・・半
田、５，５１，５２，８・・・・・・外部リード、６，
６１，６２・・・・・・金属細線、７・・・・・・成型
用樹脂、９・・・・・とりつけ用開孔、１０・・・・・
・外部放熱板、１１・・・・・絶縁シート、１２，１３
・・・・・金属層、１３・・・・・絶縁層。FIG. 1 is a cross-sectional view showing the structure of a conventional resin-sealed power semiconductor device, FIG. 2 is a cross-sectional view showing the structure of a resin-sealed power semiconductor device according to an embodiment of the present invention, and FIG. The figure is a perspective view of a power transistor element assembly structure according to the present invention,
Figure 4 is a diagram showing a comparison of the transient thermal resistance characteristics of the power transistor of the present invention and a conventional power transistor, and Figure 5 is a diagram showing the relationship between changes in the thickness of the insulating layer, dielectric strength voltage, and thermal resistance. be. 2...Substrate support part, 3...Semiconductor element, 3''...Transistor element, 4...Solder, 5, 51, 52, 8... ...External lead, 6,
61, 62... Thin metal wire, 7... Resin for molding, 9... Hole for mounting, 10...
・External heat sink, 11... Insulation sheet, 12, 13
...Metal layer, 13...Insulating layer.
Claims (1)
の金属層の３層を順次積層した積層板よりなる基板支持
部の、前記第１の金属層上に接着され、前記第２の金属
層の絶縁層と接する面とは反対の面を露呈させて樹脂封
止がなされていることを特徴とする樹脂封止型半導体装
置。 ２ 絶縁層が５０〜１１０μｍの厚さのポリイミド樹脂
層であることを特徴とする特許請求の範囲第１項に記載
の樹脂封止型半導体装置。 ３ 絶縁層の一部がポリイミド樹脂シートであることを
特徴とする特許請求の範囲第１項に記載の樹脂封止型半
導体装置。 ４ 第１の金属層および第２の金属層の絶縁層と接する
表面が、酸化膜もしくは窒化膜で覆われていることを特
徴とする特許請求の範囲第１項に記載の樹脂封止型半導
体装置。[Claims] 1. A semiconductor substrate includes a first metal layer, an insulating layer, and a second metal layer.
of a substrate supporting portion made of a laminate plate in which three metal layers are successively laminated, the surface of the substrate supporting portion is bonded onto the first metal layer and is opposite to the surface of the second metal layer that is in contact with the insulating layer. A resin-sealed semiconductor device characterized in that the semiconductor device is resin-sealed. 2. The resin-sealed semiconductor device according to claim 1, wherein the insulating layer is a polyimide resin layer with a thickness of 50 to 110 μm. 3. The resin-sealed semiconductor device according to claim 1, wherein a part of the insulating layer is a polyimide resin sheet. 4. The resin-sealed semiconductor according to claim 1, wherein the surfaces of the first metal layer and the second metal layer in contact with the insulating layer are covered with an oxide film or a nitride film. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55161175A JPS6050354B2 (en) | 1980-11-14 | 1980-11-14 | Resin-encapsulated semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55161175A JPS6050354B2 (en) | 1980-11-14 | 1980-11-14 | Resin-encapsulated semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5784157A JPS5784157A (en) | 1982-05-26 |
| JPS6050354B2 true JPS6050354B2 (en) | 1985-11-08 |
Family
ID=15730004
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55161175A Expired JPS6050354B2 (en) | 1980-11-14 | 1980-11-14 | Resin-encapsulated semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6050354B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6431353U (en) * | 1987-08-03 | 1989-02-27 | ||
| WO1998035382A1 (en) * | 1997-02-10 | 1998-08-13 | Matsushita Electronics Corporation | Resin sealed semiconductor device and method for manufacturing the same |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0758746B2 (en) * | 1985-02-27 | 1995-06-21 | 株式会社東芝 | Resin-sealed semiconductor device |
| JPH0770642B2 (en) * | 1989-03-30 | 1995-07-31 | 三菱電機株式会社 | Semiconductor device |
| US5334872A (en) * | 1990-01-29 | 1994-08-02 | Mitsubishi Denki Kabushiki Kaisha | Encapsulated semiconductor device having a hanging heat spreading plate electrically insulated from the die pad |
| US5087962A (en) * | 1991-02-25 | 1992-02-11 | Motorola Inc. | Insulated lead frame using plasma sprayed dielectric |
| US5886396A (en) * | 1995-06-05 | 1999-03-23 | Motorola, Inc. | Leadframe assembly for conducting thermal energy from a semiconductor die disposed in a package |
| JP2971834B2 (en) * | 1997-06-27 | 1999-11-08 | 松下電子工業株式会社 | Method for manufacturing resin-encapsulated semiconductor device |
| JP5761280B2 (en) * | 2013-09-12 | 2015-08-12 | 株式会社デンソー | Semiconductor package and manufacturing method thereof |
-
1980
- 1980-11-14 JP JP55161175A patent/JPS6050354B2/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6431353U (en) * | 1987-08-03 | 1989-02-27 | ||
| WO1998035382A1 (en) * | 1997-02-10 | 1998-08-13 | Matsushita Electronics Corporation | Resin sealed semiconductor device and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5784157A (en) | 1982-05-26 |
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