JPH0567697A - Resin sealed-type semiconductor device - Google Patents
Resin sealed-type semiconductor deviceInfo
- Publication number
- JPH0567697A JPH0567697A JP22987891A JP22987891A JPH0567697A JP H0567697 A JPH0567697 A JP H0567697A JP 22987891 A JP22987891 A JP 22987891A JP 22987891 A JP22987891 A JP 22987891A JP H0567697 A JPH0567697 A JP H0567697A
- Authority
- JP
- Japan
- Prior art keywords
- active element
- resin
- semiconductor device
- substrate
- sealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、熱可塑性樹脂により封
止する型の半導体装置に係わり、特にリード端子以外の
封止樹脂即ち外囲器の表面と、内部の半導体素子の電気
的な絶縁の改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device of the type which is sealed with a thermoplastic resin, and in particular, the surface of the sealing resin other than the lead terminals, that is, the surface of the envelope, is electrically insulated from the internal semiconductor element. Regarding the improvement of.
【０００２】[0002]
【従来の技術】半導体基板内に不純物を導入・拡散して
造り込んだ能動素子、受動素子または回路成分をいわゆ
るトランスファモールド法により樹脂を封止する樹脂封
止型半導体装置は、量産化して実用に供されている。2. Description of the Related Art A resin-encapsulated semiconductor device in which an active element, a passive element or a circuit component made by introducing and diffusing impurities into a semiconductor substrate is encapsulated with a resin by a so-called transfer molding method is put into practical use after mass production. Have been offered to.
【０００３】この種の樹脂封止型半導体装置は、いわゆ
るリードフレームを利用する組立方式を採る型の他に、
絶縁基板に各種の電子回路用部品をハイブリッド形式で
組込んでから、樹脂により封止しかつ、各電子回路用部
品に電気的に接続するリード端子を封止樹脂層外に導出
する型も実用化している。This type of resin-encapsulated semiconductor device is not limited to the type that employs a so-called lead frame assembling method.
A type in which various electronic circuit components are assembled in a hybrid form on an insulating substrate, then sealed with resin, and lead terminals that electrically connect to each electronic circuit component are led out of the sealing resin layer It has become.
【０００４】この型の樹脂封止型半導体装置にあって
は、これを電子機器に実装する際、能動素子と電子機器
内の部品の電気的短絡を防止する観点から、いわゆるア
ウターリードであるリード端子以外の外囲器表面と、能
動素子が電気的に絶縁することが求められている。In this type of resin-encapsulated semiconductor device, a lead, which is a so-called outer lead, is mounted from the viewpoint of preventing an electrical short circuit between an active element and a component in the electronic device when it is mounted in an electronic device. It is required that the active element is electrically insulated from the surface of the envelope other than the terminals.
【０００５】図１及び図２の断面図により従来の樹脂封
止型半導体装置を説明する。図１の型は、銅または銅合
金を表面付近に設置する（以後銅製と記載する）リード
フレーム１に能動素子を造り込んだ半導体基板２を導電
性接着剤層や半田層などの導電層３を介して固着する。A conventional resin-encapsulated semiconductor device will be described with reference to the sectional views of FIGS. In the mold shown in FIG. 1, a semiconductor substrate 2 in which an active element is built in a lead frame 1 in which copper or a copper alloy is installed near the surface (hereinafter referred to as copper) is formed into a conductive layer 3 such as a conductive adhesive layer or a solder layer. Stick through.
【０００６】次に、能動素子の電極（図示せず）とアウ
ターリードとして機能するリードフレーム１のリード端
子４間に金属細線５をボンディング法により熱圧着して
電気的に接続して組立体を形成する。その後、熱可塑性
樹脂から成る封止樹脂層６により組立体を被覆して樹脂
封止型半導体装置を製造する。以下この樹脂封止型半導
体装置を絶縁タイプと記載する。Next, a thin metal wire 5 is thermocompression-bonded by a bonding method between the electrode (not shown) of the active element and the lead terminal 4 of the lead frame 1 functioning as an outer lead to electrically connect the assembly. Form. Then, the assembly is covered with a sealing resin layer 6 made of a thermoplastic resin to manufacture a resin-sealed semiconductor device. Hereinafter, this resin-encapsulated semiconductor device is referred to as an insulation type.
【０００７】これに対して図２に明かにする樹脂封止型
半導体装置は、能動素子を造り込んだ半導体基板２をマ
ウントしたリードフレーム１の裏面を露出して封止樹脂
層６面としており、絶縁されていないので、以後非絶縁
タイプと記載する。On the other hand, in the resin-sealed semiconductor device shown in FIG. 2, the back surface of the lead frame 1 on which the semiconductor substrate 2 having the active element is mounted is exposed to form the sealing resin layer 6 surface. Since it is not insulated, it will be referred to as a non-insulated type hereinafter.
【０００８】この他の形状は、図１と全く同じである。The other shapes are exactly the same as in FIG.
【０００９】[0009]
【発明が解決しようとする課題】絶縁タイプの問題点
は、非絶縁タイプに比べて外囲器の飽和熱抵抗値ＲＴｈ
（ｊ−ｃ）が大きいために、同一の能動素子を搭載する
と装置全体が許容できるパワー損失が小さくなる点にあ
る。The problem of the insulation type is that the saturation thermal resistance value RTh of the envelope is higher than that of the non-insulation type.
Since (j−c) is large, if the same active element is mounted, the power loss that can be tolerated by the entire device will be small.
【００１０】これは、絶縁用の封止樹脂の熱伝導度Ｋが
金属や半田のそれより小さく、その上リードフレーム１
の裏面を覆う封止樹脂層の厚さＡ（図１参照）を、製造
技術上の制約から、金属などと同等の熱伝導度が得られ
る程度に薄くできないことが原因である。This is because the thermal conductivity K of the insulating sealing resin is smaller than that of metal or solder, and the lead frame 1
The reason is that the thickness A (see FIG. 1) of the sealing resin layer covering the back surface of (1) cannot be made thin enough to obtain thermal conductivity equivalent to that of metal or the like due to restrictions in manufacturing technology.
【００１１】例えば、市販されている中で最も熱伝導特
性が良い封止樹脂（Ｋ＝０．０４Ｗ／ｃｍ℃）は、現在
一般に使用されている厚さ０．５ｍｍの銅製リードフレ
ームのＫ＝４．２Ｗ／ｃｍ℃と同等の熱伝導度特性を得
るに約０．００５ｍｍ以下の厚さが必要になる。For example, the commercially available encapsulating resin (K = 0.04 W / cm ° C.) having the best thermal conductivity is K = of the 0.5 mm-thick copper lead frame currently in general use. A thickness of about 0.005 mm or less is required to obtain a thermal conductivity characteristic equivalent to 4.2 W / cm ° C.
【００１２】しかし、約０．６ｍｍの厚さが製造上限界
であるので、約０．００５ｍｍ以下の厚さは、到底実現
不可能な値である。即ち、平均粒形を持った熱可塑性封
止樹脂を適用しているために、０．５ｍｍ以下の狭い場
所に入り難くどうしても巣即ちボイド（Ｖｏｉｄ）が発
生するために約０．６ｍｍの厚さが必要になる。However, since a thickness of about 0.6 mm is a manufacturing limit, a thickness of about 0.005 mm or less is an unrealizable value. That is, since a thermoplastic sealing resin having an average particle shape is applied, it is difficult to enter a narrow space of 0.5 mm or less, and a void or void is inevitably generated, so that a thickness of about 0.6 mm is obtained. Will be required.
【００１３】本発明は、このような事情により成された
もので、特に飽和熱抵抗特性を改善する点に目的があ
る。The present invention has been made under such circumstances, and its object is to improve the saturation thermal resistance characteristic.
【００１４】[0014]
【課題を解決するための手段】セラミック基板と，この
セラミック基板の表面に取付ける能動素子と，この組立
体を被覆する封止樹脂層と，この封止樹脂層から露出す
る前記セラミック基板の裏面に本発明に係わる樹脂封止
型半導体装置の特徴がある。更に、前記セラミック基板
をアルミニウム及び窒素を主成分とする点にも特徴があ
る。A ceramic substrate, an active element mounted on the surface of the ceramic substrate, a sealing resin layer covering the assembly, and a back surface of the ceramic substrate exposed from the sealing resin layer. The resin-sealed semiconductor device according to the present invention is characterized. Another feature is that the ceramic substrate contains aluminum and nitrogen as main components.
【００１５】[0015]
【作用】本発明に係わる樹脂封止型半導体装置は、熱伝
導度の大きいＡｌＮ材質のセラミック基板（以下ＡｌＮ
基板と記載する）の一面に能動素子を搭載し、この搭載
面と反対面即ちセラミック基板裏面の一部分を外囲器の
外部に露出する形状が得られるように封止樹脂層で被覆
する。即ち、封止樹脂層の表面にセラミック基板の裏面
が露出する形状となる。The resin-encapsulated semiconductor device according to the present invention is provided with a ceramic substrate (hereinafter referred to as AlN) made of an AlN material having high thermal conductivity.
An active element is mounted on one surface (referred to as a substrate), and a surface opposite to the mounting surface, that is, a part of the back surface of the ceramic substrate is covered with a sealing resin layer so as to obtain a shape exposed to the outside of the envelope. That is, the back surface of the ceramic substrate is exposed on the front surface of the sealing resin layer.
【００１６】能動素子は、例えばシリコン基板に所定の
不純物を導入・拡散して造り込んだもので、これをセラ
ミック基板の表面に形成する銅箔などから構成する金属
パターンに半田などを利用して形成するので、セラミッ
ク基板の裏面には、例えば酸化銅などの金属薄層を形成
して応力の均衡を保つこともある。このように本発明に
おけるセラミック基板裏面には、セラミック層または金
属薄層が露出する形状である。The active element is formed by introducing and diffusing predetermined impurities into a silicon substrate, for example, and using solder or the like for a metal pattern formed of copper foil or the like formed on the surface of the ceramic substrate. Since it is formed, a thin metal layer such as copper oxide may be formed on the back surface of the ceramic substrate to keep the stress balance. As described above, the ceramic substrate or the metal thin layer is exposed on the back surface of the ceramic substrate in the present invention.
【００１７】[0017]
【実施例】本発明に係わる樹脂封止型半導体装置の実施
例を従来技術と同一部品には同じ番号を付けた図３を参
照して説明する。表面付近を銅または同合金で構成する
リードフレーム１は、従来と同様にベッド部（図示せ
ず）とインナーリード（樹脂封止層外に導出した部分は
アウターリードと記載する）を備えており、ベッド部に
マウントする半導体基板２には、能動素子を造り込んで
いる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a resin-sealed semiconductor device according to the present invention will be described with reference to FIG. The lead frame 1 whose surface is made of copper or the same alloy is provided with a bed portion (not shown) and an inner lead (a portion led out to the outside of the resin sealing layer is referred to as an outer lead) as in the conventional case. An active element is built in the semiconductor substrate 2 mounted on the bed.
【００１８】能動素子としては、例えばシリコン半導体
基板に所定の不純物を導入・拡散して電力用トランジス
タ通称ジャイアントトランジスタなどの他に、例えばＤ
−ＭＯＳなどのＦＥＴも適用可能であり、勿論他の半導
体素子も利用できる。As the active element, for example, in addition to a power transistor commonly called a giant transistor by introducing and diffusing a predetermined impurity in a silicon semiconductor substrate, for example, D
A FET such as -MOS is also applicable, and of course other semiconductor elements can be used.
【００１９】このような能動素子を造り込んだ半導体基
板２を融点が３００℃程度の半田層３によりリードフレ
ーム１に固着する。A semiconductor substrate 2 having such an active element built therein is fixed to a lead frame 1 by a solder layer 3 having a melting point of about 300.degree.
【００２０】リードフレーム１に形成するインナーリー
ドと、能動素子に形成する各電極の電気的接続は、Ａ
ｌ、Ａｕまたは銅などの金属細線５を熱圧着法を利用す
る。The electrical connection between the inner lead formed on the lead frame 1 and each electrode formed on the active element is A
The metal thin wire 5 made of 1, Au, copper, or the like is used by thermocompression bonding.
【００２１】更に、例えば蒸着工程により金属パターン
を形成したＡｌＮなどから成るセラミック基板７に、半
田層３より融点の低いＳｎ−Ｐｂ半田層８により一体に
して組立体を形成する。組立体は、セラミック基板７に
電子機器に必要な回路用の部品（図示せず）を能動素子
の他に取付けることにより構成する。Further, for example, an Sn-Pb solder layer 8 having a melting point lower than that of the solder layer 3 is integrated with a ceramic substrate 7 made of AlN or the like having a metal pattern formed by a vapor deposition process to form an assembly. The assembly is constructed by attaching circuit components (not shown) necessary for electronic equipment to the ceramic substrate 7 in addition to the active elements.
【００２２】次に組立体をいわゆるトランスファーモー
ルド法により熱可塑性樹脂６を封止すると共に、封止樹
脂層６外にアウターリード４を導出して電子機器との接
続に備える。Next, the assembly is sealed with the thermoplastic resin 6 by the so-called transfer molding method, and the outer leads 4 are led out of the sealing resin layer 6 to prepare for connection with electronic equipment.
【００２３】[0023]
【発明の効果】従来、絶縁タイプの熱可塑性樹脂封止型
半導体装置は、非絶縁タイプのものに比べて、外囲器の
飽和熱熱抵抗値が非常に大きかったのに対して、本発明
では、は飽和熱熱抵抗が大幅に改善された絶縁タイプの
熱可塑性樹脂封止型半導体装置を実現することができ
る。即ち、１ｍｍ平方の半導体基板をセラミック基板に
マウントした場合、Ｒｔｈ（ｊ−ｃ）は、従来の非絶縁
タイプと絶縁タイプが夫々５℃／Ｗと１７℃／Ｗである
のに対して、本発明に係わる熱可塑性樹脂封止型半導体
装置は約１０℃／Ｗが得られた。In the conventional insulating type thermoplastic resin-sealed semiconductor device, the saturation thermal resistance value of the envelope is much larger than that of the non-insulated type semiconductor device. In, it is possible to realize an insulating type thermoplastic resin-sealed semiconductor device in which the saturation thermal resistance is significantly improved. That is, when a 1 mm square semiconductor substrate is mounted on a ceramic substrate, Rth (jc) is 5 ° C./W and 17 ° C./W in the conventional non-insulated type and the insulated type, respectively. The thermoplastic resin-sealed semiconductor device according to the present invention obtained about 10 ° C./W.
【図１】従来の熱可塑性樹脂封止型半導体装置の断面図
である。FIG. 1 is a cross-sectional view of a conventional thermoplastic resin-sealed semiconductor device.
【図２】従来の他の熱可塑性樹脂封止型半導体装置の断
面図である。FIG. 2 is a sectional view of another conventional thermoplastic resin-sealed semiconductor device.
【図３】本発明の熱可塑性樹脂封止型半導体装置の断面
図である。FIG. 3 is a cross-sectional view of a thermoplastic resin-sealed semiconductor device of the present invention.
１：リードフレーム、 ２：半導体基板、 ３、８：半田層、 ４：アウターリード、 ５：金属細線、 ６：熱可塑性封止樹脂層、 ７：セラミック基板。 1: Lead frame, 2: Semiconductor substrate, 3, 8: Solder layer, 4: Outer lead, 5: Thin metal wire, 6: Thermoplastic encapsulating resin layer, 7: Ceramic substrate.
Claims (2)
表面に設置する能動素子と，この組立体を被覆する封止
樹脂層と，この封止樹脂層表面に露出する前記セラミッ
ク基板の裏面を具備することを特徴とする樹脂封止型半
導体装置1. A ceramic substrate, an active element provided on the surface of the ceramic substrate, a sealing resin layer covering the assembly, and a back surface of the ceramic substrate exposed on the surface of the sealing resin layer. Resin-sealed semiconductor device characterized by
窒素を主成分とすることを特徴とする樹脂封止型半導体
装置2. A resin-encapsulated semiconductor device characterized in that the ceramic substrate contains aluminum and nitrogen as main components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22987891A JPH0567697A (en) | 1991-09-10 | 1991-09-10 | Resin sealed-type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22987891A JPH0567697A (en) | 1991-09-10 | 1991-09-10 | Resin sealed-type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0567697A true JPH0567697A (en) | 1993-03-19 |
Family
ID=16899125
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22987891A Pending JPH0567697A (en) | 1991-09-10 | 1991-09-10 | Resin sealed-type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0567697A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000091802A (en) * | 1998-09-11 | 2000-03-31 | Matsushita Electric Ind Co Ltd | Microwave circuit |
| JP2004128420A (en) * | 2002-10-07 | 2004-04-22 | Fuji Electric Fa Components & Systems Co Ltd | Semiconductor module and manufacturing method thereof |
| JP2011172482A (en) * | 2011-05-23 | 2011-09-01 | Hitachi Ltd | Inverter |
| JP2013085470A (en) * | 2012-12-10 | 2013-05-09 | Hitachi Ltd | Inverter |
| WO2015029635A1 (en) * | 2013-08-28 | 2015-03-05 | 住友電気工業株式会社 | Method for manufacturing wide band gap semiconductor device, method for manufacturing semiconductor module, wide band gap semiconductor device and semiconductor module |
| KR20210115535A (en) * | 2020-03-13 | 2021-09-27 | 주식회사 파워로직스 | Apparatus For Manufacturing Protection Circuit Module |
| WO2022164620A1 (en) * | 2021-01-27 | 2022-08-04 | Cree, Inc. | Packaged electronic devices having substrates with thermally conductive adhesive layers |
-
1991
- 1991-09-10 JP JP22987891A patent/JPH0567697A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000091802A (en) * | 1998-09-11 | 2000-03-31 | Matsushita Electric Ind Co Ltd | Microwave circuit |
| JP2004128420A (en) * | 2002-10-07 | 2004-04-22 | Fuji Electric Fa Components & Systems Co Ltd | Semiconductor module and manufacturing method thereof |
| JP2011172482A (en) * | 2011-05-23 | 2011-09-01 | Hitachi Ltd | Inverter |
| JP2013085470A (en) * | 2012-12-10 | 2013-05-09 | Hitachi Ltd | Inverter |
| WO2015029635A1 (en) * | 2013-08-28 | 2015-03-05 | 住友電気工業株式会社 | Method for manufacturing wide band gap semiconductor device, method for manufacturing semiconductor module, wide band gap semiconductor device and semiconductor module |
| US9640619B2 (en) | 2013-08-28 | 2017-05-02 | Sumitomo Electric Industries, Ltd. | Methods of manufacturing wide band gap semiconductor device and semiconductor module, and wide band gap semiconductor device and semiconductor module |
| KR20210115535A (en) * | 2020-03-13 | 2021-09-27 | 주식회사 파워로직스 | Apparatus For Manufacturing Protection Circuit Module |
| WO2022164620A1 (en) * | 2021-01-27 | 2022-08-04 | Cree, Inc. | Packaged electronic devices having substrates with thermally conductive adhesive layers |
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