JP3234614B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

Info

Publication number
JP3234614B2
JP3234614B2 JP23823891A JP23823891A JP3234614B2 JP 3234614 B2 JP3234614 B2 JP 3234614B2 JP 23823891 A JP23823891 A JP 23823891A JP 23823891 A JP23823891 A JP 23823891A JP 3234614 B2 JP3234614 B2 JP 3234614B2
Authority
JP
Japan
Prior art keywords
insulating substrate
semiconductor chip
contacts
bump
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP23823891A
Other languages
Japanese (ja)
Other versions
JPH0582586A (en
Inventor
誠蔵 大前
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP23823891A priority Critical patent/JP3234614B2/en
Publication of JPH0582586A publication Critical patent/JPH0582586A/en
Application granted granted Critical
Publication of JP3234614B2 publication Critical patent/JP3234614B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は、樹脂封止型の半導体
装置及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device and a method of manufacturing the same.

【0002】[0002]

【従来の技術】従来のこの種の半導体装置を図7に示
す。ダイパッド12上に接合材14を介して半導体チッ
プ1が接合されている。半導体チップ1には複数のボン
ディングパッド10が形成されており、それぞれ対応す
るリード13に金属細線11を介して電気的に接続され
ている。半導体チップ1、ダイパッド12、金属細線1
1及びリード13の一部はモールド樹脂からなるパッケ
ージ本体6により封止されている。
2. Description of the Related Art A conventional semiconductor device of this type is shown in FIG. The semiconductor chip 1 is bonded on the die pad 12 via a bonding material 14. A plurality of bonding pads 10 are formed on the semiconductor chip 1, and are electrically connected to corresponding leads 13 via thin metal wires 11. Semiconductor chip 1, die pad 12, thin metal wire 1
1 and a part of the lead 13 are sealed by a package body 6 made of a mold resin.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、リード
13をパッケージ本体6により保持するために、リード
13の埋め込み長さL1を適当な値以上に設定する必要
がある。また、半導体チップ1のボンディングパッド1
0とリード13とを接続する金属細線11を無理のない
適正な形状とするために、ダイパッド12とリード13
との間に適度な間隔L2を設ける必要がある。このた
め、半導体チップ1に比べてパッケージ全体が大きくな
るという問題点があった。また、金属細線11と半導体
チップ1の端部との接触を回避するために、半導体チッ
プ1の内部回路の構成に拘わらず、半導体チップ1の各
ボンディングパッド10を半導体チップ1の周縁部に配
置する必要があり、その結果半導体チップ1の電気的特
性を十分に引き出せない恐れがあるという問題点もあっ
た。
However, in order to hold the leads 13 by the package body 6, it is necessary to set the embedded length L1 of the leads 13 to an appropriate value or more. The bonding pad 1 of the semiconductor chip 1
In order to form the fine metal wire 11 connecting the lead 0 and the lead 13 into a reasonable and reasonable shape, the die pad 12 and the lead 13
It is necessary to provide an appropriate distance L2 between the two. For this reason, there is a problem that the entire package is larger than the semiconductor chip 1. In addition, in order to avoid contact between the thin metal wires 11 and the ends of the semiconductor chip 1, the respective bonding pads 10 of the semiconductor chip 1 are arranged at the peripheral edge of the semiconductor chip 1 irrespective of the internal circuit configuration of the semiconductor chip 1. Therefore, there is also a problem that the electrical characteristics of the semiconductor chip 1 may not be sufficiently brought out.

【0004】この発明はこのような問題点を解消するた
めになされたもので、小型で且つ半導体チップの電気的
特性を十分に引き出すことのできる半導体装置を提供す
ることを目的とする。また、この発明はこのような半導
体装置を得ることのできる半導体装置の製造方法を提供
することも目的としている。
The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor device which is small in size and can sufficiently bring out the electrical characteristics of a semiconductor chip. Another object of the present invention is to provide a method for manufacturing a semiconductor device capable of obtaining such a semiconductor device.

【0005】[0005]

【課題を解決するための手段】この発明に係る半導体装
置は、複数の第1のバンプ電極が形成された半導体チッ
プと、半導体チップを搭載するための絶縁基板と、絶縁
基板の第1の面に形成されると共にそれぞれ対応する半
導体チップの第1のバンプ電極に接合される複数の接点
と、絶縁基板の第2の面に形成されると共にそれぞれ対
応する接点とは異なる位置に配置された複数の第2のバ
ンプ電極と、絶縁基板の第1の面上に形成されると共に
それぞれ一端が対応する接点に電気的に接続され且つ他
端が絶縁基板を挟んで対応する第2のバンプ電極と同じ
位置に配置された複数の接続部材と、絶縁基板を貫通し
て設けられ且つそれぞれ対応する第2のバンプ電極と接
続部材の他端とを電気的に接続する複数のスルーホール
と、半導体チップと絶縁基板の第1の面とを樹脂封止す
るパッケージ本体とを備えたものである。また、この発
明に係る半導体装置の製造方法は、それぞれ半導体チッ
プの複数の第1のバンプ電極に対応させて絶縁基板の第
1の面に複数の接点を形成すると共に第1のバンプ電極
とは異なる位置に配置された複数の第2のバンプ電極を
絶縁基板の第2の面に形成し、それぞれ一端が対応する
接点に電気的に接続され且つ他端が絶縁基板を挟んで対
応する第2のバンプ電極と同じ位置に配置されるように
絶縁基板の第1の面に複数の接続部材を形成し、互いに
対応する第2のバンプ電極と接続部材の他端とをそれぞ
れ絶縁基板を貫通するスルーホールによって電気的に接
続し、半導体チップの第1のバンプ電極がそれぞれ対応
する絶縁基板の接点に接触するように半導体チップと絶
縁基板とを位置合わせし、半導体チップの第1のバンプ
電極と絶縁基板の接点との接触部を加熱してこれらを拡
散接合させ、半導体チップと絶縁基板の第1の面とを樹
脂封止する方法である。
A semiconductor device according to the present invention has a semiconductor chip on which a plurality of first bump electrodes are formed, an insulating substrate for mounting the semiconductor chip, and a first surface of the insulating substrate. And a plurality of contacts formed on the second bump surface of the corresponding semiconductor chip and respectively connected to the first bump electrodes of the corresponding semiconductor chip, and a plurality of contacts formed on the second surface of the insulating substrate and arranged at positions different from the respective corresponding contacts. And a second bump electrode formed on the first surface of the insulating substrate and
One end is electrically connected to the corresponding contact and the other is
The end is the same as the corresponding second bump electrode across the insulating substrate
Penetrate through the insulating substrate and the multiple connection members
Provided in contact with the corresponding second bump electrodes.
Multiple through-holes electrically connecting the other end of the connecting member
And a package body for resin-sealing the semiconductor chip and the first surface of the insulating substrate. Further, in the method of manufacturing a semiconductor device according to the present invention, a plurality of contacts are formed on the first surface of the insulating substrate corresponding to the plurality of first bump electrodes of the semiconductor chip, respectively. A plurality of second bump electrodes arranged at different positions are formed on the second surface of the insulating substrate, and one end of each of the second bump electrodes corresponds to the second bump electrode.
The other end is electrically connected to the contact and the other end is
So that it is located at the same position as the corresponding second bump electrode
Forming a plurality of connecting members on the first surface of the insulating substrate,
Connect the corresponding second bump electrode and the other end of the connection member
Electrically connected by through holes passing through the insulating substrate
Subsequently, the semiconductor chip and the insulating substrate are aligned with each other such that the first bump electrodes of the semiconductor chip contact the corresponding contacts of the insulating substrate, and the first bump electrodes of the semiconductor chip and the contacts of the insulating substrate are connected. This is a method in which the contact portions are heated and diffusion-bonded to each other, and the semiconductor chip and the first surface of the insulating substrate are sealed with resin.

【0006】[0006]

【作用】この発明においては、半導体チップの複数の第
1のバンプ電極に絶縁基板の複数の接点が直接接合され
ると共に絶縁基板の第2のバンプ電極がこの半導体装置
の実装用の電極となる。
According to the present invention, a plurality of contacts of an insulating substrate are directly joined to a plurality of first bump electrodes of a semiconductor chip, and the second bump electrodes of the insulating substrate serve as mounting electrodes of the semiconductor device. .

【0007】[0007]

【実施例】以下、この発明の実施例を添付図面に基づい
て説明する。図1はこの発明の第1実施例に係る半導体
装置を示す断面図である。半導体チップ21の第1の面
21a上に複数の第1のバンプ電極22が形成されてい
る。これらのバンプ電極22は、半導体チップ21の内
部回路の構成に即した適当な位置に配されており、第1
の面21aの周縁部及び中央部を問わず自由に配置され
ている。一方、セラミックからなる絶縁基板23の第1
の面23a上にはそれぞれ半導体チップ21の第1のバ
ンプ電極22に対応する位置に複数の接点24が形成さ
れており、互いに対応する半導体チップ21の第1のバ
ンプ電極22と絶縁基板23の接点24とが接合され電
気的に接続されている。また、絶縁基板23の第2の面
23b上にはそれぞれ接点24に対応する位置に複数の
第2のバンプ電極26が形成されている。互いに対応す
る接点24と第2のバンプ電極26とは絶縁基板23を
貫通して設けられたスルーホール25により電気的に接
続されており、第2のバンプ電極26がこの半導体装置
の実装用の電極となる。
Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention. A plurality of first bump electrodes 22 are formed on a first surface 21a of the semiconductor chip 21. These bump electrodes 22 are arranged at appropriate positions in accordance with the configuration of the internal circuit of the semiconductor chip 21.
Irrespective of the peripheral portion and the central portion of the surface 21a. On the other hand, the first insulating substrate 23 made of ceramic
A plurality of contacts 24 are formed on the surface 23a of the semiconductor chip 21 at positions corresponding to the first bump electrodes 22 of the semiconductor chip 21, respectively. The first bump electrodes 22 and the insulating substrate 23 of the semiconductor chip 21 corresponding to each other are formed. The contact 24 is joined and electrically connected. Further, a plurality of second bump electrodes 26 are formed on the second surface 23b of the insulating substrate 23 at positions corresponding to the contacts 24, respectively. The corresponding contact 24 and the second bump electrode 26 are electrically connected by a through hole 25 penetrating the insulating substrate 23, and the second bump electrode 26 is used for mounting the semiconductor device. It becomes an electrode.

【0008】半導体チップ21と絶縁基板23の第1の
面23aとがモールド樹脂からなるパッケージ本体27
により封止されている。このパッケージ本体27により
半導体チップ21が保護されると共に半導体チップ21
の第1のバンプ電極22と絶縁基板23の接点24との
接合部が保護されている。なお、半導体チップ21の第
1のバンプ電極22は例えば錫から、絶縁基板23に設
けられた接点24は例えば半田から形成されている。
The semiconductor chip 21 and the first surface 23a of the insulating substrate 23 are made of a molding resin 27 made of a molding resin.
Is sealed. The semiconductor chip 21 is protected by the package body 27 and the semiconductor chip 21
The joint between the first bump electrode 22 and the contact 24 of the insulating substrate 23 is protected. The first bump electrodes 22 of the semiconductor chip 21 are formed of, for example, tin, and the contacts 24 provided on the insulating substrate 23 are formed of, for example, solder.

【0009】この半導体装置においては、半導体チップ
21の第1のバンプ電極22に絶縁基板23の接点24
が直接接合され、絶縁基板23に設けられた第2のバン
プ電極26が半導体装置の実装用電極となるため、図7
に示した従来の半導体装置で用いられるようなリード1
3及び金属細線11が不要となる。その結果、半導体装
置の小型化が達成された。また、半導体チップ21の第
1のバンプ電極22は第1の面21a内において半導体
チップ21の内部回路の構成に応じて都合のよい位置に
自由に設けることができるため、第1のバンプ電極22
に接続される半導体チップ21の内部配線を最短距離で
設けることが可能となる。その結果、半導体チップ21
の信号処理の高速化が達成される。また、内部配線の抵
抗が低減されることから、半導体チップ21のリニア特
性が向上する。
In this semiconductor device, the first bump electrode 22 of the semiconductor chip 21 is connected to the contact 24 of the insulating substrate 23.
7 are directly bonded, and the second bump electrode 26 provided on the insulating substrate 23 becomes a mounting electrode of the semiconductor device.
Lead 1 used in the conventional semiconductor device shown in FIG.
3 and the thin metal wire 11 become unnecessary. As a result, miniaturization of the semiconductor device has been achieved. In addition, the first bump electrode 22 of the semiconductor chip 21 can be freely provided at a convenient position in the first surface 21a according to the configuration of the internal circuit of the semiconductor chip 21.
It is possible to provide the internal wiring of the semiconductor chip 21 connected to the shortest distance. As a result, the semiconductor chip 21
The speed of the signal processing is improved. Further, since the resistance of the internal wiring is reduced, the linear characteristics of the semiconductor chip 21 are improved.

【0010】このような半導体装置は次のようにして製
造することができる。まず、半導体チップ21の第1の
バンプ電極22に対応させて絶縁基板23に接点24、
スルーホール25及び第2のバンプ電極26を形成す
る。次に、図2に示されるように、接点24が形成され
ている第1の面23aが上方を向くように絶縁基板23
を加熱治具30の上に載置する。この絶縁基板23の接
点24上に対応する半導体チップ21の第1のバンプ電
極22が接触するように半導体チップ21を絶縁基板2
3に位置合わせする。この状態で加熱治具30を昇温さ
せることにより半導体チップ21の第1のバンプ電極2
2と絶縁基板23の接点24との接合部を加熱し、これ
らを拡散接合させる。このようにして絶縁基板23上に
搭載された半導体チップ21を絶縁基板23と共に図3
に示されるように上金型28のキャビティハーフ28a
と下金型29のキャビティハーフ29aとで形成される
キャビティ内に収容し、双方の金型28及び29を型締
めする。この状態で、上金型28に形成されているゲー
ト28bを介してキャビティ内に熔融状態のモールド樹
脂を注入し、その後樹脂を冷却することにより図1に示
される半導体装置が製造される。
[0010] Such a semiconductor device can be manufactured as follows. First, a contact 24 is formed on the insulating substrate 23 in correspondence with the first bump electrode 22 of the semiconductor chip 21.
A through hole 25 and a second bump electrode 26 are formed. Next, as shown in FIG. 2, the insulating substrate 23 is placed such that the first surface 23a on which the contact 24 is formed faces upward.
Is placed on the heating jig 30. The semiconductor chip 21 is placed on the insulating substrate 2 such that the first bump electrode 22 of the corresponding semiconductor chip 21 contacts the contact 24 of the insulating substrate 23.
Align to 3. In this state, the temperature of the heating jig 30 is raised, so that the first bump electrode 2 of the semiconductor chip 21 is formed.
The joint between the substrate 2 and the contact 24 of the insulating substrate 23 is heated and these are diffused and joined. The semiconductor chip 21 mounted on the insulating substrate 23 in this manner is combined with the insulating substrate 23 in FIG.
The cavity half 28a of the upper mold 28 as shown in FIG.
The lower mold 29 is housed in a cavity formed by the cavity half 29a and the molds 28 and 29 are clamped. In this state, the mold resin in a molten state is injected into the cavity through the gate 28b formed in the upper mold 28, and then the resin is cooled, whereby the semiconductor device shown in FIG. 1 is manufactured.

【0011】上記の第1実施例では、絶縁基板23がセ
ラミックから形成されていたが、これに限るものではな
く、電気絶縁性と適度な機械的強度を有していればよ
い。例えば、図4に示される第2実施例のように、ポリ
イミドからなる絶縁基板33の上に半導体チップ31を
搭載し、半導体チップ31と絶縁基板33の第1の面3
3aをパッケージ本体37で樹脂封止してもよい。ま
た、図5に示される第3実施例のように、ガラスエポキ
シからなる絶縁基板43の上に半導体チップ41を搭載
し、半導体チップ41と絶縁基板43の第1の面43a
をパッケージ本体47で樹脂封止することもできる。
In the above-described first embodiment, the insulating substrate 23 is formed of ceramic. However, the present invention is not limited to this, and it is sufficient that the insulating substrate 23 has electrical insulation and appropriate mechanical strength. For example, as in the second embodiment shown in FIG. 4, a semiconductor chip 31 is mounted on an insulating substrate 33 made of polyimide, and the semiconductor chip 31 and the first surface 3 of the insulating substrate 33 are mounted.
3a may be resin-sealed with the package body 37. Also, as in the third embodiment shown in FIG. 5, a semiconductor chip 41 is mounted on an insulating substrate 43 made of glass epoxy, and the semiconductor chip 41 and the first surface 43a of the insulating substrate 43 are mounted.
Can be resin-sealed by the package body 47.

【0012】図6に第4実施例に係る半導体装置の断面
を示す。絶縁基板53の第2の面53b上には、この半
導体装置を実装する上で適した位置に複数の第2のバン
プ電極56が形成されている。これらの第2のバンプ電
極56はそれぞれスルーホール55を介して絶縁基板5
3の第1の面53a上に形成された接続部材58の一端
部に電気的に接続されている。接続部材58は金属箔か
ら形成されており、接続部材58の他端部上にそれぞれ
接点54が形成されている。これらの接点54は、半導
体チップ51の第1のバンプ電極52に対応する位置に
形成され、各接点54が対応する半導体チップ51のバ
ンプ電極52に接合されている。そして、半導体チップ
51と絶縁基板53の第1の面53aとがパッケージ本
体57により樹脂封止されている。この第4実施例にお
いては、半導体装置の実装用の電極となる第2のバンプ
電極56を半導体チップ51の第1のバンプ電極52と
異なる位置に自由に配置することができるので、半導体
装置の実装時の自由度が高くなるという利点を生じる。
FIG. 6 shows a cross section of a semiconductor device according to a fourth embodiment. On the second surface 53b of the insulating substrate 53, a plurality of second bump electrodes 56 are formed at positions suitable for mounting the semiconductor device. These second bump electrodes 56 are respectively connected to the insulating substrate 5 through the through holes 55.
3 is electrically connected to one end of a connection member 58 formed on the first surface 53a. The connection member 58 is formed from a metal foil, and a contact 54 is formed on the other end of the connection member 58. These contacts 54 are formed at positions corresponding to the first bump electrodes 52 of the semiconductor chip 51, and each contact 54 is joined to the corresponding bump electrode 52 of the semiconductor chip 51. Then, the semiconductor chip 51 and the first surface 53 a of the insulating substrate 53 are resin-sealed by the package body 57. In the fourth embodiment, the second bump electrode 56 serving as an electrode for mounting the semiconductor device can be freely arranged at a position different from that of the first bump electrode 52 of the semiconductor chip 51. There is an advantage that the degree of freedom in mounting is increased.

【0013】[0013]

【発明の効果】以上説明したように、この発明に係る半
導体装置は、複数の第1のバンプ電極が形成された半導
体チップと、半導体チップを搭載するための絶縁基板
と、絶縁基板の第1の面に形成されると共にそれぞれ対
応する半導体チップの第1のバンプ電極に接合される複
数の接点と、絶縁基板の第2の面に形成されると共にそ
れぞれ対応する接点とは異なる位置に配置された複数の
第2のバンプ電極と、絶縁基板の第1の面上に形成され
ると共にそれぞれ一端が対応する接点に電気的に接続さ
れ且つ他端が絶縁基板を挟んで対応する第2のバンプ電
極と同じ位置に配置された複数の接続部材と、絶縁基板
を貫通して設けられ且つそれぞれ対応する第2のバンプ
電極と接続部材の他端とを電気的に接続する複数のスル
ーホールと、半導体チップと絶縁基板の第1の面とを樹
脂封止するパッケージ本体とを備えているので、小型化
が達成されると共に半導体チップの電気的特性を十分に
引き出すことができる。また、この発明に係る半導体装
置の製造方法は、それぞれ半導体チップの複数の第1の
バンプ電極に対応させて絶縁基板の第1の面に複数の接
点を形成すると共に第1のバンプ電極とは異なる位置に
配置された複数の第2のバンプ電極を絶縁基板の第2の
面に形成し、それぞれ一端が対応する接点に電気的に接
続され且つ他端が絶縁基板を挟んで対応する第2のバン
プ電極と同じ位置に配置されるように絶縁基板の第1の
面に複数の接続部材を形成し、互いに対応する第2のバ
ンプ電極と接続部材の他端とをそれぞれ絶縁基板を貫通
するスルーホールによって電気的に接続し、半導体チッ
プの第1のバンプ電極がそれぞれ対応する絶縁基板の接
点に接触するように半導体チップと絶縁基板とを位置合
わせし、半導体チップの第1のバンプ電極と絶縁基板の
接点との接触部を加熱してこれらを拡散接合させ、半導
体チップと絶縁基板の第1の面とを樹脂封止するので、
小型で且つ半導体チップの電気的特性を十分に引き出す
ことのできる半導体装置の製造が可能となる。
As described above, the semiconductor device according to the present invention has a semiconductor chip on which a plurality of first bump electrodes are formed, an insulating substrate for mounting the semiconductor chip, and a first insulating substrate. a plurality of contacts which are joined to the first bump electrodes of the corresponding semiconductor chip is formed into the surface of, it is disposed at a position different from the corresponding contact is formed in a second surface of the insulating substrate And a plurality of second bump electrodes formed on the first surface of the insulating substrate.
And one end is electrically connected to the corresponding contact.
And the other end corresponds to the second bump electrode with the insulating substrate interposed therebetween.
A plurality of connecting members arranged at the same position as the poles and an insulating substrate
And corresponding second bumps provided through the
A plurality of vias for electrically connecting the electrode and the other end of the connection member.
Since the semiconductor device is provided with a package body for sealing the semiconductor chip and the first surface of the insulating substrate with a resin, the miniaturization can be achieved and the electrical characteristics of the semiconductor chip can be sufficiently brought out. Further, in the method of manufacturing a semiconductor device according to the present invention, a plurality of contacts are formed on the first surface of the insulating substrate corresponding to the plurality of first bump electrodes of the semiconductor chip, respectively. A plurality of second bump electrodes arranged at different positions are formed on the second surface of the insulating substrate, and one end of each is electrically connected to a corresponding contact.
A second bump connected to the other end with the insulating substrate interposed therebetween.
Of the insulating substrate so as to be located at the same position as the
A plurality of connecting members are formed on the surface, and second bars corresponding to each other are formed.
Pump electrode and the other end of the connection member penetrate the insulating substrate
The semiconductor chip and the insulating substrate are aligned so that the first bump electrodes of the semiconductor chip are in contact with the corresponding contacts of the insulating substrate, and the first bump electrodes of the semiconductor chip are electrically connected to each other. Since the contact portion between the semiconductor chip and the contact of the insulating substrate is heated and diffusion-bonded, and the semiconductor chip and the first surface of the insulating substrate are resin-sealed,
It is possible to manufacture a semiconductor device which is small and can sufficiently bring out the electrical characteristics of a semiconductor chip.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の第1実施例に係る半導体装置を示す
断面図である。
FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

【図2】図1の半導体装置を製造する方法の一工程を示
す断面図である。
FIG. 2 is a sectional view showing one step of a method of manufacturing the semiconductor device of FIG. 1;

【図3】図1の半導体装置を製造する方法の他の工程を
示す断面図である。
FIG. 3 is a sectional view showing another step of a method for manufacturing the semiconductor device of FIG. 1;

【図4】この発明の第2実施例に係る半導体装置を示す
断面図である。
FIG. 4 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

【図5】この発明の第3実施例に係る半導体装置を示す
断面図である。
FIG. 5 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.

【図6】この発明の第4実施例に係る半導体装置を示す
断面図である。
FIG. 6 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.

【図7】従来の半導体装置を示す断面図である。FIG. 7 is a sectional view showing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

21 半導体チップ 22 第1のバンプ電極 23 絶縁基板 24 接点 25 スルーホール 26 第2のバンプ電極 27 パッケージ本体 31 半導体チップ 33 絶縁基板 37 パッケージ本体 41 半導体チップ 43 絶縁基板 47 パッケージ本体 51 半導体チップ 52 第1のバンプ電極 53 絶縁基板 54 接点 55 スルーホール 56 第2のバンプ電極 57 パッケージ本体 58 接続部材 Reference Signs List 21 semiconductor chip 22 first bump electrode 23 insulating substrate 24 contact 25 through hole 26 second bump electrode 27 package body 31 semiconductor chip 33 insulating substrate 37 package body 41 semiconductor chip 43 insulating substrate 47 package body 51 semiconductor chip 52 first Bump electrode 53 insulating substrate 54 contact point 55 through hole 56 second bump electrode 57 package body 58 connecting member

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/60 311 H01L 23/12 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/60 311 H01L 23/12

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 複数の第1のバンプ電極が形成された半
導体チップと、 前記半導体チップを搭載するための絶縁基板と、 前記絶縁基板の第1の面に形成されると共にそれぞれ対
応する前記半導体チップの第1のバンプ電極に接合され
る複数の接点と、 前記絶縁基板の第2の面に形成されると共にそれぞれ対
応する前記接点とは異なる位置に配置された複数の第2
のバンプ電極と、前記絶縁基板の第1の面上に形成されると共にそれぞれ
一端が対応する前記接点に電気的に接続され且つ他端が
前記絶縁基板を挟んで対応する第2のバンプ電極と同じ
位置に配置された複数の接続部材と、 前記絶縁基板を貫通して設けられ且つそれぞれ対応する
第2のバンプ電極と接続部材の他端とを電気的に接続す
る複数のスルーホールと、 前記半導体チップと前記絶縁基板の第1の面とを樹脂封
止するパッケージ本体とを備えたことを特徴とする半導
体装置。
A semiconductor chip on which a plurality of first bump electrodes are formed; an insulating substrate for mounting the semiconductor chip; and a semiconductor formed on a first surface of the insulating substrate and corresponding to the semiconductor chip. A plurality of contacts joined to the first bump electrodes of the chip; and a plurality of second contacts formed on the second surface of the insulating substrate and arranged at positions different from the corresponding contacts .
And a bump electrode formed on the first surface of the insulating substrate and
One end is electrically connected to the corresponding contact and the other end is
Same as the corresponding second bump electrode with the insulating substrate interposed
A plurality of connection members arranged at positions, and provided through the insulating substrate and corresponding to the respective connection members.
The second bump electrode is electrically connected to the other end of the connection member.
A plurality of through-holes, and a package body for resin-sealing the semiconductor chip and the first surface of the insulating substrate.
【請求項2】 それぞれ半導体チップの複数の第1のバ
ンプ電極に対応させて絶縁基板の第1の面に複数の接点
を形成すると共に第1のバンプ電極とは異なる位置に配
置された複数の第2のバンプ電極を絶縁基板の第2の面
に形成し、それぞれ一端が対応する接点に電気的に接続され且つ他
端が絶縁基板を挟んで対応する第2のバンプ電極と同じ
位置に配置されるように絶縁基板の第1の面に複数の接
続部材を形成し、 互いに対応する第2のバンプ電極と接続部材の他端とを
それぞれ絶縁基板を貫通するスルーホールによって電気
的に接続し、 半導体チップの第1のバンプ電極がそれぞれ対応する絶
縁基板の接点に接触するように半導体チップと絶縁基板
とを位置合わせし、 半導体チップの第1のバンプ電極と絶縁基板の接点との
接触部を加熱してこれらを拡散接合させ、 半導体チップと絶縁基板の第1の面とを樹脂封止するこ
とを特徴とする半導体装置の製造方法。
2. A method according to claim 1, wherein a plurality of contacts are formed on the first surface of the insulating substrate in correspondence with the plurality of first bump electrodes of the semiconductor chip, and the plurality of contacts are arranged at positions different from the first bump electrodes. A second bump electrode is formed on the second surface of the insulating substrate, and one end is electrically connected to a corresponding contact and
The end is the same as the corresponding second bump electrode across the insulating substrate
A plurality of contacts on the first surface of the insulating substrate so that
Forming a connection member, and connecting the second bump electrode and the other end of the connection member corresponding to each other to each other.
Electricity is generated by through holes penetrating the insulating substrate, respectively.
The semiconductor chip and the insulating substrate are aligned so that the first bump electrodes of the semiconductor chip contact the corresponding contacts of the insulating substrate, respectively, and the contact between the first bump electrode of the semiconductor chip and the insulating substrate A semiconductor device and a first surface of an insulating substrate are resin-sealed by heating a contact portion of the semiconductor device with the semiconductor chip and diffusion bonding them.
JP23823891A 1991-09-18 1991-09-18 Semiconductor device and manufacturing method thereof Expired - Lifetime JP3234614B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23823891A JP3234614B2 (en) 1991-09-18 1991-09-18 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23823891A JP3234614B2 (en) 1991-09-18 1991-09-18 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH0582586A JPH0582586A (en) 1993-04-02
JP3234614B2 true JP3234614B2 (en) 2001-12-04

Family

ID=17027202

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23823891A Expired - Lifetime JP3234614B2 (en) 1991-09-18 1991-09-18 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3234614B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2833996B2 (en) * 1994-05-25 1998-12-09 日本電気株式会社 Flexible film and semiconductor device having the same
JP3176542B2 (en) * 1995-10-25 2001-06-18 シャープ株式会社 Semiconductor device and manufacturing method thereof
JP2982729B2 (en) * 1997-01-16 1999-11-29 日本電気株式会社 Semiconductor device
US5889332A (en) * 1997-02-21 1999-03-30 Hewlett-Packard Company Area matched package

Also Published As

Publication number Publication date
JPH0582586A (en) 1993-04-02

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