JP2959480B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2959480B2 JP2959480B2 JP8212375A JP21237596A JP2959480B2 JP 2959480 B2 JP2959480 B2 JP 2959480B2 JP 8212375 A JP8212375 A JP 8212375A JP 21237596 A JP21237596 A JP 21237596A JP 2959480 B2 JP2959480 B2 JP 2959480B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- hole
- semiconductor element
- semiconductor device
- cover
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 78
- 238000004519 manufacturing process Methods 0.000 title description 11
- 239000000758 substrate Substances 0.000 claims description 49
- 229920005989 resin Polymers 0.000 claims description 26
- 239000011347 resin Substances 0.000 claims description 26
- 238000007789 sealing Methods 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims 1
- 238000000034 method Methods 0.000 description 11
- 238000001721 transfer moulding Methods 0.000 description 6
- 230000010354 integration Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/4805—Shape
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/732—Location after the connecting process
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/01013—Aluminum [Al]
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- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は、樹脂封止型の半導体装
置及びその製造方法に関し、特に電源配線及び信号配線
のインダクタンス、キャパシタンス及び抵抗を低減する
ことにより、高集積・高速の半導体素子を基板に搭載す
ることができる半導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device and a method of manufacturing the same, and more particularly, to a highly integrated and high-speed semiconductor device by reducing inductance, capacitance and resistance of power supply wiring and signal wiring. The present invention relates to a semiconductor device that can be mounted on a substrate and a method for manufacturing the same.
【0002】[0002]
【従来の技術】半導体素子の高集積化に伴い、半導体素
子を搭載する集積回路用パッケージの多ピン化が急速に
進んでいる。例えば、パッケージの外周部に沿って外部
リードを配置するクワッド・フラット・パッケージ(Q
FP)では、外部リードのピッチが0.65mmから
0.5mm〜0.4mmに縮小されている。このQFP
では、ピン数が増加すると、ピン間のピッチが狭くなる
ので、400ピン程度が多ピン化の限界となっている。
一方、近年の半導体素子の高集積化・高機能化により、
500ピン以上の半導体素子のパッケージが求められる
ようになっている。2. Description of the Related Art With the increase in the degree of integration of semiconductor devices, the number of pins of integrated circuit packages on which semiconductor devices are mounted is rapidly increasing. For example, a quad flat package (Q) in which external leads are arranged along the outer periphery of the package
FP), the pitch of the external leads is reduced from 0.65 mm to 0.5 mm to 0.4 mm. This QFP
In this case, as the number of pins increases, the pitch between the pins becomes narrower, so that about 400 pins are the limit of increasing the number of pins.
On the other hand, due to recent high integration and high functionality of semiconductor devices,
A package of a semiconductor element having 500 pins or more has been required.
【0003】そこで、このような要請に対応することが
できる集積回路用パッケージとして、外部との接続部を
パッケージの裏面全体に配置することができるボール・
グリット・アレイ(BGA)パッケージが開発され、実
用化されている。[0003] Therefore, as a package for an integrated circuit which can respond to such a demand, a ball-type package in which a connection portion with the outside can be arranged on the entire back surface of the package.
Grit array (BGA) packages have been developed and put into practical use.
【0004】BGAパッケージ構造を有する半導体装置
は、例えば、特開平7−321246号公報や特開平7
−245360号公報等に開示されているが、基本的に
は図5に示すような構造をしている。すなわち、ガラス
エポキシ樹脂等の基板5の表面には、表面信号配線1a
と半導体素子搭載部4とが設けられ、基板5の裏面に
は、裏面信号配線1b及びグランド(GND)配線1c
が設けられる。裏面信号配線1bは、格子状に配列され
た外部接続端子である半田ボール3と電気的に接続され
る。また、基板5には、表面と裏面とを連通するスルー
ホール2が半導体素子搭載部4から間隔を隔てた位置に
形成される。A semiconductor device having a BGA package structure is disclosed in, for example, Japanese Patent Application Laid-Open No.
Although it is disclosed in Japanese Unexamined Patent Publication No. 245360, it basically has a structure as shown in FIG. That is, the surface signal wiring 1a is provided on the surface of the substrate 5 such as a glass epoxy resin.
And a semiconductor element mounting portion 4 are provided. On the back surface of the substrate 5, a back surface signal wiring 1b and a ground (GND) wiring 1c are provided.
Is provided. The back surface signal wiring 1b is electrically connected to the solder balls 3, which are external connection terminals arranged in a grid. In the substrate 5, through holes 2 communicating between the front surface and the back surface are formed at positions spaced from the semiconductor element mounting portion 4.
【0005】BGAパッケージ構造を有する半導体装置
を製造する場合には、基板5の半導体素子搭載部4上に
マウント材(図示せず)を介して半導体素子8を搭載
し、半導体素子8の電極と基板の表面信号配線1aの間
を金属細線であるワイヤ9で接続する。次いで、半導体
素子8及び金属細線9を含む主要部がトランスファーモ
ールド法により、封止樹脂10により封止される。When a semiconductor device having a BGA package structure is manufactured, a semiconductor element 8 is mounted on a semiconductor element mounting portion 4 of a substrate 5 via a mounting material (not shown), and the electrodes of the semiconductor element 8 are connected to each other. The surface signal wirings 1a of the substrate are connected by wires 9 which are thin metal wires. Next, a main part including the semiconductor element 8 and the thin metal wire 9 is sealed with a sealing resin 10 by a transfer molding method.
【0006】このようなBGAパッケージ構造を有する
半導体装置は、基板の裏面全体を外部接続領域として使
用できるので、QFPに比べ、パッケージを小型化で
き、半導体装置の多ピン化にも対応することができる。In the semiconductor device having such a BGA package structure, the entire back surface of the substrate can be used as an external connection region. Therefore, the size of the package can be reduced as compared with the QFP, and the semiconductor device can cope with an increase in the number of pins of the semiconductor device. it can.
【0007】特開平7−321246号公報では、パッ
ケージの反り等の変形を抑えるため、透孔を形成したプ
レートが封止樹脂の表面に基板と対向するように固着さ
れている半導体装置が開示されている。Japanese Patent Application Laid-Open No. 7-32246 discloses a semiconductor device in which a plate having a through hole is fixed to the surface of a sealing resin so as to oppose the substrate in order to suppress deformation such as warpage of the package. ing.
【0008】また、特開平7ー245360号公報で
は、半導体チップ下面と樹脂系基板上面との間隙部に、
その間隙部の一端側からいわゆる毛細管現象を利用して
封止樹脂を流し込む封止樹脂の充填方法が開示されてい
る。In Japanese Patent Application Laid-Open No. Hei 7-245360, a gap between a lower surface of a semiconductor chip and an upper surface of a resin-based substrate is provided.
A method of filling the sealing resin by pouring the sealing resin from one end of the gap portion using a so-called capillary phenomenon is disclosed.
【0009】[0009]
【発明が解決しようとする課題】従来のBGAパッケー
ジ構造を有する半導体装置では、基板5の表面信号配線
1aと裏面信号配線1bを電気的に接続するためのスル
ーホール2は、トランスファーモールド領域外に形成さ
れている。これは、トランスファーモールド領域内にス
ルーホール2を形成すると、トランスファーモールドの
際に、封入樹脂10がスルーホール2内に充填されてし
まい、封入樹脂10がスルーホール2を通過して、基板
5の裏面を覆ってしまったり、スルーホール2の電気的
接続を切断してしまう等の問題が生じるためである。In the conventional semiconductor device having a BGA package structure, the through hole 2 for electrically connecting the front surface signal wiring 1a and the rear surface signal wiring 1b of the substrate 5 is located outside the transfer mold area. Is formed. This is because, when the through-hole 2 is formed in the transfer mold area, the encapsulating resin 10 is filled in the through-hole 2 during the transfer molding, and the encapsulating resin 10 passes through the through-hole 2 to form the substrate 5. This is because problems such as covering the back surface or disconnecting the electrical connection of the through hole 2 occur.
【0010】このように、スルーホール2はトランスフ
ァーモールド領域外の基板5に形成されているので、基
板5の表面信号配線1aと裏面信号配線1bは、トラン
スファーモールド領域外のスルーホール2を介して迂回
して電気的に接続されることとなる。その結果、電源配
線及び信号配線のインダクタンス、キャパシタンス、抵
抗が増加し、半導体素子、半導体装置の性能が低化する
といった不具合があった。As described above, since the through hole 2 is formed in the substrate 5 outside the transfer mold area, the front surface signal wiring 1a and the back surface signal wiring 1b of the substrate 5 are connected via the through hole 2 outside the transfer mold area. It is electrically connected by bypass. As a result, the inductance, capacitance, and resistance of the power supply wiring and the signal wiring are increased, and the performance of the semiconductor element and the semiconductor device is reduced.
【0011】また、封入方法として、特開平7ー245
360号公報に示すように、フリップチップ実装を行う
場合に、毛細管現象を利用した封止樹脂の充填方法を用
いることも可能であるが、汎用チップを搭載し、ワイヤ
ーボンディング法を用いた金属細線によって電気的な接
続を行う汎用のBGAパッケージ及び製造方法に適用す
ることは困難である。[0011] As an encapsulation method, Japanese Patent Application Laid-Open No. 7-245
As shown in Japanese Patent Publication No. 360, it is possible to use a sealing resin filling method utilizing a capillary phenomenon when performing flip-chip mounting. However, a general-purpose chip is mounted and a thin metal wire using a wire bonding method is used. It is difficult to apply to a general-purpose BGA package for making electrical connection and a manufacturing method.
【0012】本発明は、上記問題点に鑑みてなされたも
のであり、電源配線及び信号配線のインダクタンス、キ
ャパシタンス、抵抗を低減し、高集積・高速の半導体素
子を搭載することができる半導体装置及びその製造方法
を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a semiconductor device capable of reducing inductance, capacitance, and resistance of a power supply wiring and a signal wiring and mounting a highly integrated and high-speed semiconductor element. It is an object of the present invention to provide a manufacturing method thereof.
【0013】[0013]
【課題を解決するための手段】本発明の半導体装置は、
表面に半導体素子を搭載する基板と、その基板の表面と
裏面とを連通して形成されるスルーホールと、そのスル
ーホールを介して前記半導体素子と電気的に接続され、
前記基板の裏面に設けられる外部接続端子と、前記スル
ーホールの開口部上に載置される平板からなるカバー
と、そのカバーの表面を封止する封止樹脂と、を有し、
前記スル−ホ−ルは全て前記封止樹脂内部に位置するこ
とを特徴とするものである。According to the present invention, there is provided a semiconductor device comprising:
A substrate on which a semiconductor element is mounted on the front surface, a through hole formed by communicating the front surface and the back surface of the substrate, and electrically connected to the semiconductor element via the through hole ,
An external connection terminal provided on a back surface of the substrate;
-A cover made of a flat plate placed on the opening of the hole
And a sealing resin for sealing the surface of the cover,
The through-holes are all located inside the sealing resin .
【0014】スルーホールは、半導体素子の搭載部分近
傍に形成されるのが好ましい。The through hole is preferably formed in the vicinity of the mounting portion of the semiconductor element.
【0015】カバーは、半導体素子の搭載部分に対応す
る位置に切欠部が形成されていてもよい。また、カバー
は、表面を絶縁処理した金属板であり、例えば、表面に
アルマイト処理を施し絶縁処理したアルミニウム板であ
る。The cover may have a cutout at a position corresponding to the mounting portion of the semiconductor element. The cover is a metal plate whose surface is insulated, for example, an aluminum plate whose surface is anodized by alumite treatment.
【0016】本発明の半導体装置の製造方法は、(1)
表面と裏面とを連通するスルーホールが形成された基板
に半導体素子を搭載する工程と、(2)前記スルーホー
ルを介して前記半導体素子と前記基板の裏面に設けられ
る外部接続端子とを電気的に接続する工程と、(3)前
記スルーホールの開口部上に平板からなるカバーを載置
する工程と、(4)前記スル−ホ−ルが全て封止樹脂の
内部に位置するように前記カバーの表面を封止樹脂で封
止する工程と、を有し、(1)から(4)の順序で行う
ことを特徴とするものである。The method of manufacturing a semiconductor device according to the present invention comprises the steps of (1)
Mounting a semiconductor element on a substrate in which a through hole communicating between the front surface and the back surface is formed ;
Provided on the back surface of the semiconductor element and the substrate via a
Electrically connecting the external connection terminal to the external connection terminal;
Place a cover made of a flat plate on the opening of the through hole
And (4) all of the sulfolole is formed of a sealing resin.
Seal the surface of the cover with sealing resin so that it is located inside.
And stopping in the order of (1) to (4) .
【0017】本発明によれば、スルーホールがカバーに
よって塞がれることにより、トランスファーモールド工
程において、封入樹脂がスルーホール内に入り込むこと
がないので、スルーホールを基板の所望の位置に形成す
ることができる。特に、スルーホールが、半導体素子の
搭載部分近傍に形成されている場合には、基板の表面及
び裏面の電源配線及び信号配線を最短距離で接続するこ
とができる。また、本発明の半導体装置は、従来の基板
製造、組立工程を変更することなく製造できる。According to the present invention, since the through-hole is closed by the cover, the encapsulating resin does not enter the through-hole in the transfer molding process, so that the through-hole is formed at a desired position on the substrate. Can be. In particular, when the through hole is formed near the mounting portion of the semiconductor element, the power supply wiring and the signal wiring on the front and back surfaces of the substrate can be connected with the shortest distance. Further, the semiconductor device of the present invention can be manufactured without changing conventional substrate manufacturing and assembling processes.
【0018】[0018]
【発明の実施の形態】以下、本発明の実施の形態を図1
から図4を参照しながら説明する。但し、従来と同一に
相当する部分は同一符号を附して、その説明を省略す
る。FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to FIG. However, portions corresponding to those in the related art are denoted by the same reference numerals, and description thereof is omitted.
【0019】本発明に係る半導体装置は、BGAパッケ
ージ構造を有するものであり、図1に示すように、ガラ
スエポキシ樹脂等の基板5を有する。基板5の表面に
は、表面信号配線1aと半導体素子搭載部4とが設けら
れ、基板5の裏面には、裏面信号配線1b及びグランド
(GND)配線1cが設けられる。裏面信号配線1b
は、格子状に配列された外部接続端子である半球形の半
田ボール3と電気的に接続される。また、基板5には、
表面と裏面とを連通するスルーホール2が半導体素子搭
載部4の近傍に形成される。The semiconductor device according to the present invention has a BGA package structure, and has a substrate 5 made of glass epoxy resin or the like as shown in FIG. The front surface signal wiring 1a and the semiconductor element mounting portion 4 are provided on the front surface of the substrate 5, and the back surface signal wiring 1b and the ground (GND) wiring 1c are provided on the back surface of the substrate 5. Back signal wiring 1b
Are electrically connected to hemispherical solder balls 3 which are external connection terminals arranged in a lattice. Also, the substrate 5 includes
A through hole 2 connecting the front surface and the back surface is formed near the semiconductor element mounting portion 4.
【0020】基板5の表面の半導体素子搭載部4上には
半導体素子8が搭載され、ワイヤボンディングにより、
半導体素子8の電極と表面信号配線1aとが金属細線で
あるワイヤ9によって電気的に接続される。A semiconductor element 8 is mounted on the semiconductor element mounting portion 4 on the surface of the substrate 5 and is bonded by wire bonding.
The electrode of the semiconductor element 8 and the surface signal wiring 1a are electrically connected by a wire 9 which is a thin metal wire.
【0021】本発明の半導体装置はさらに、基板5に形
成されたスルーホール2の基板表面側の開口部2aを塞
ぐカバー6を有する。図2に示すように、カバー6は、
半導体素子8が搭載される中央部分に切欠部6aが形成
される平板であり、このカバー6によって、充填される
封入樹脂10がスルーホール2内に入り込むのを防止す
る。また、カバー6が基板5と接合する裏面には、トラ
ンスファー封入温度で硬化する例えばポリイミド系の接
着剤7が塗布される。カバー6の材質としては、ガラス
エポキシ基板5と同一の材質を使用してもよい。The semiconductor device of the present invention further has a cover 6 for closing the opening 2a on the substrate surface side of the through hole 2 formed in the substrate 5. As shown in FIG. 2, the cover 6
This is a flat plate having a notch 6a formed at the center where the semiconductor element 8 is mounted. The cover 6 prevents the filled resin 10 from entering the through hole 2. On the back surface where the cover 6 is bonded to the substrate 5, for example, a polyimide-based adhesive 7 that is cured at the transfer encapsulation temperature is applied. As the material of the cover 6, the same material as that of the glass epoxy substrate 5 may be used.
【0022】本発明の半導体装置を製造する場合には、
まず、基板5の半導体素子搭載部4上にマウント材(図
示せず)を介して半導体素子8を搭載する。次いで、半
導体素子8の電極と基板5の表面信号配線1aの間をワ
イヤ9で接続する。In manufacturing the semiconductor device of the present invention,
First, the semiconductor element 8 is mounted on the semiconductor element mounting portion 4 of the substrate 5 via a mounting material (not shown). Next, a wire 9 is connected between the electrode of the semiconductor element 8 and the surface signal wiring 1 a of the substrate 5.
【0023】次いで、カバー6の裏面に接着材7を塗布
し、カバー6の裏面と基板5の表面とを接着し、スルー
ホール2の基板表面側の開口部2aをカバー6で塞ぐ。
次いで、基板5は、図3に示すように上下の金型11,
11間にセッティングされ、トランスファーモールド法
により、封止樹脂10で封止される。このとき、スルー
ホール2の基板表面側の開口部2aがカバー6によって
塞がれているので、上下の金型11,11間に充填され
た封入樹脂10がスルーホール2内に入り込むことはな
い。Next, an adhesive 7 is applied to the back surface of the cover 6, the back surface of the cover 6 is adhered to the surface of the substrate 5, and the opening 2 a of the through hole 2 on the substrate surface side is closed by the cover 6.
Next, as shown in FIG.
11 and sealed with a sealing resin 10 by a transfer molding method. At this time, since the opening 2 a of the through hole 2 on the substrate surface side is closed by the cover 6, the sealing resin 10 filled between the upper and lower molds 11, 11 does not enter the through hole 2. .
【0024】このようにして封止樹脂10がカバー6の
表面を含む部分を被覆して、基板5の表裏面に配線した
信号配線1a,1bが接続された半導体装置が完成す
る。In this manner, the semiconductor device in which the sealing resin 10 covers the portion including the surface of the cover 6 and the signal wirings 1a and 1b wired on the front and back surfaces of the substrate 5 are completed.
【0025】本発明によれば、スルーホール2がカバー
6によって塞がれることにより、トランスファーモール
ド工程において、封入樹脂10がスルーホール2内に入
り込むことがないので、スルーホール2を所望の位置に
形成することができる。特に、スルーホール2が、半導
体素子搭載部4の近傍に形成されている場合には、基板
5の表面及び裏面の信号配線1a,1bを最短距離で接
続することができる。その結果、本発明に係る半導体装
置は、電源配線及び信号配線のインダクタンス、キャパ
シタンス、及び抵抗を低減することができ、半導体素子
の高集積化・高速化に対応することが可能になる。According to the present invention, since the through-hole 2 is closed by the cover 6, the encapsulating resin 10 does not enter the through-hole 2 in the transfer molding process, so that the through-hole 2 can be moved to a desired position. Can be formed. In particular, when the through hole 2 is formed near the semiconductor element mounting portion 4, the signal wirings 1a and 1b on the front and back surfaces of the substrate 5 can be connected with the shortest distance. As a result, the semiconductor device according to the present invention can reduce the inductance, the capacitance, and the resistance of the power supply wiring and the signal wiring, and can cope with high integration and high speed of the semiconductor element.
【0026】また、本発明の半導体装置は、従来の基板
製造、組立工程を変更することなく、製造できるので、
生産性にも優れている。Further, the semiconductor device of the present invention can be manufactured without changing the conventional substrate manufacturing and assembling steps.
Excellent productivity.
【0027】図4は、本発明の変形例を示す断面図であ
る。この変形例では、切欠部を有するカバーとして、表
面を絶縁処理した金属板、例えば、表面にアルマイト処
理を施し絶縁処理したアルミニウム板16が用いられて
いる。このような絶縁処理したアルミニウム板16を用
いることにより、パッケージの熱伝導率を改善すること
が可能となるため、パッケージの熱抵抗を従来のBGA
パッケージ構造よりも30〜40%低減することができ
る。FIG. 4 is a sectional view showing a modification of the present invention. In this modification, a metal plate whose surface is insulated, for example, an aluminum plate 16 whose surface is anodized and insulated, is used as the cover having the notch. The use of such an insulated aluminum plate 16 makes it possible to improve the thermal conductivity of the package.
30 to 40% less than the package structure.
【0028】なお本発明は、上記実施の形態に限定され
ることはなく、特許請求の範囲に記載された技術的事項
の範囲内において、種々の変更が可能である。The present invention is not limited to the above embodiment, and various changes can be made within the scope of the technical matters described in the claims.
【0029】[0029]
【発明の効果】本発明によれば、スルーホールがカバー
によって塞がれることにより、トランスファーモールド
工程において、封入樹脂がスルーホール内に入り込むこ
とがないので、スルーホールを所望の位置に形成するこ
とができる。特に、スルーホールが、半導体素子の搭載
部分近傍に形成されている場合には、基板の表面及び裏
面の電源配線及び信号配線を最短距離で接続することが
できる。その結果、本発明に係る半導体装置は、電源配
線及び信号配線のインダクタンス、キャパシタンス、及
び抵抗を低減することができ、半導体素子の高集積化・
高速化に対応することが可能になる。According to the present invention, since the through-hole is closed by the cover, the encapsulating resin does not enter the through-hole in the transfer molding process, so that the through-hole can be formed at a desired position. Can be. In particular, when the through hole is formed near the mounting portion of the semiconductor element, the power supply wiring and the signal wiring on the front and back surfaces of the substrate can be connected with the shortest distance. As a result, the semiconductor device according to the present invention can reduce the inductance, the capacitance, and the resistance of the power supply wiring and the signal wiring, and achieve high integration of the semiconductor element.
It is possible to cope with high speed.
【0030】また、本発明の半導体装置は、従来の基板
製造、組立工程を変更することなく、製造できるので、
生産性にも優れている。Further, the semiconductor device of the present invention can be manufactured without changing the conventional substrate manufacturing and assembling steps.
Excellent productivity.
【図1】本発明に係る半導体装置の断面図である。FIG. 1 is a sectional view of a semiconductor device according to the present invention.
【図2】本発明に係る半導体装置の一部断面斜視図であ
る。FIG. 2 is a partial cross-sectional perspective view of a semiconductor device according to the present invention.
【図3】本発明に係る半導体装置の製造工程の一部を示
す断面図である。FIG. 3 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the present invention.
【図4】本発明の変形例を示す半導体装置の断面図であ
る。FIG. 4 is a sectional view of a semiconductor device showing a modification of the present invention.
【図5】従来の半導体装置を示す断面図である。FIG. 5 is a sectional view showing a conventional semiconductor device.
1a:表面信号配線 1b:裏面信号配線 1c:グランド(GND)配線 2:スルーホール 2a:開口部 3:半田ボール(外部接続端子) 4:半導体素子搭載部 5:基板 6:カバー 6a:切欠部 7:接着剤 9:ワイヤ 10:封止樹脂 11:金型 16:表面を絶縁処理したアルミニウム板 1a: Front signal wiring 1b: Back signal wiring 1c: Ground (GND) wiring 2: Through hole 2a: Opening 3: Solder ball (external connection terminal) 4: Semiconductor element mounting part 5: Substrate 6: Cover 6a: Notch 7: Adhesive 9: Wire 10: Sealing resin 11: Mold 16: Aluminum plate whose surface is insulated
Claims (7)
ールと、 そのスルーホールを介して前記半導体素子と電気的に接
続され、前記基板の裏面に設けられる外部接続端子と、 前記スルーホールの開口部上に載置される平板からなる
カバーと、 そのカバーの表面を封止する封止樹脂と、 を有し、前記スル−ホ−ルは全て前記封止樹脂内部に位
置することを特徴とする半導体装置。A substrate on which a semiconductor element is mounted on a front surface, a through hole formed by connecting the front surface and the back surface of the substrate, and an electric connection with the semiconductor element via the through hole; possess an external connection terminal provided on a rear surface of the substrate, and a cover made of a flat plate that is placed on the opening of the through hole, and a sealing resin for sealing the surface of the cover, the said sul - ho -All the screws are located inside the sealing resin.
Wherein a to location.
分近傍に形成されることを特徴とする請求項1に記載の
半導体装置。2. The semiconductor device according to claim 1, wherein the through hole is formed near a mounting portion of the semiconductor element.
応する位置に切欠部が形成されていることを特徴とする
請求項1又は2に記載の半導体装置。3. The semiconductor device according to claim 1, wherein the cover has a notch at a position corresponding to a mounting portion of the semiconductor element.
であることを特徴とする請求項1乃至3のいずれか1つ
の項に記載の半導体装置。4. The semiconductor device according to claim 1, wherein the cover is a metal plate whose surface is insulated.
し絶縁処理したアルミニウム板であることを特徴とする
請求項4に記載の半導体装置。5. The semiconductor device according to claim 4, wherein said cover is an aluminum plate whose surface has been subjected to alumite treatment and insulation treatment.
ルーホールと、 そのスルーホールを介して前記半導体素子と電気的に接
続され、前記基板の裏面に設けられる外部接続端子と、 前記複数のスルーホールの開口部上に載置され、前記半
導体素子の搭載部分に対応する位置に切欠部が形成され
た平板からなるカバーと、 そのカバーの表面を封止する封止樹脂と、 を有し、前記複数のスル−ホ−ルは全て前記封止樹脂内
部に位置することを特徴とする半導体装置。6. A substrate on which a semiconductor element is mounted on a front surface, a plurality of through holes formed by connecting the front surface and the back surface of the substrate, and a plurality of through holes electrically connected to the semiconductor element via the through holes. An external connection terminal provided on the back surface of the substrate, and a cover made of a flat plate which is mounted on the openings of the plurality of through holes and has a cutout formed at a position corresponding to a mounting portion of the semiconductor element, possess a sealing resin for sealing the surface of the cover, wherein the plurality of sul - Ho - in all Le is the sealing resin
A semiconductor device, wherein the semiconductor device is located in a part .
た基板に半導体素子を搭載する工程と、 (2)前記スルーホールを介して前記半導体素子と前記
基板の裏面に設けられる外部接続端子とを電気的に接続
する工程と、 (3)前記スルーホールの開口部上に平板からなるカバ
ーを載置する工程と、 (4)前記スル−ホ−ルが全て封止樹脂の内部に位置す
るように前記カバーの表面を封止樹脂で封止する工程
と、 を有し、(1)から(4)の順序で行うことを特徴とす
る半導体装置の製造方法。7. A step of mounting a semiconductor element on a substrate provided with a through hole communicating between the front surface and the rear surface, and a step of mounting the semiconductor element on the rear surface of the substrate via the through hole. (3) placing a cover made of a flat plate on the opening of the through-hole, and (4) sealing the resin through-hole entirely. Located inside
And a step of sealing the surface of the cover with a sealing resin as described above , wherein the steps are performed in the order of (1) to (4).
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8212375A JP2959480B2 (en) | 1996-08-12 | 1996-08-12 | Semiconductor device and manufacturing method thereof |
US08/909,963 US6037656A (en) | 1996-08-12 | 1997-08-12 | Semiconductor integrated circuit device having short signal paths to terminals and process of fabrication thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8212375A JP2959480B2 (en) | 1996-08-12 | 1996-08-12 | Semiconductor device and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH1056098A JPH1056098A (en) | 1998-02-24 |
JP2959480B2 true JP2959480B2 (en) | 1999-10-06 |
Family
ID=16621533
Family Applications (1)
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JP8212375A Expired - Fee Related JP2959480B2 (en) | 1996-08-12 | 1996-08-12 | Semiconductor device and manufacturing method thereof |
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JP (1) | JP2959480B2 (en) |
Families Citing this family (14)
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JPH0525602A (en) * | 1991-07-17 | 1993-02-02 | Nippon Steel Corp | Production of aluminum plated austenitic stainless steel having excellent plating adhesion |
JP3602968B2 (en) * | 1998-08-18 | 2004-12-15 | 沖電気工業株式会社 | Semiconductor device and substrate connection structure thereof |
JP2000294894A (en) * | 1998-12-21 | 2000-10-20 | Seiko Epson Corp | Circuit board, its manufacture, display device using the same and electronics |
US6954362B2 (en) * | 2001-08-31 | 2005-10-11 | Kyocera Wireless Corp. | System and method for reducing apparent height of a board system |
TWI239080B (en) * | 2002-12-31 | 2005-09-01 | Advanced Semiconductor Eng | Semiconductor chip package and method for the same |
EP1601017A4 (en) * | 2003-02-26 | 2009-04-29 | Ibiden Co Ltd | Multilayer printed wiring board |
US20090044967A1 (en) * | 2006-03-14 | 2009-02-19 | Sharp Kabushiki Kaisha | Circuit board, electronic circuit device, and display device |
US8188379B2 (en) * | 2008-07-04 | 2012-05-29 | Unimicron Technology Corp. | Package substrate structure |
JP5236377B2 (en) * | 2008-07-16 | 2013-07-17 | シャープ株式会社 | Semiconductor device and display device |
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JP2013125765A (en) | 2011-12-13 | 2013-06-24 | Elpida Memory Inc | Semiconductor device |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS582054A (en) * | 1981-06-26 | 1983-01-07 | Fujitsu Ltd | Semiconductor device |
FR2556503B1 (en) * | 1983-12-08 | 1986-12-12 | Eurofarad | ALUMINA INTERCONNECTION SUBSTRATE FOR ELECTRONIC COMPONENT |
JPS63118241A (en) * | 1986-11-07 | 1988-05-23 | Kanegafuchi Chem Ind Co Ltd | Continuous preparation of laminated sheet for electrical use |
JPS63131593A (en) * | 1986-11-20 | 1988-06-03 | 日本電気株式会社 | Thick film circuit board |
US5216278A (en) * | 1990-12-04 | 1993-06-01 | Motorola, Inc. | Semiconductor device having a pad array carrier package |
JPH0566996A (en) * | 1991-09-06 | 1993-03-19 | Shikoku Nippon Denki Software Kk | Cache control system |
US5563446A (en) * | 1994-01-25 | 1996-10-08 | Lsi Logic Corporation | Surface mount peripheral leaded and ball grid array package |
JPH07245360A (en) * | 1994-03-02 | 1995-09-19 | Toshiba Corp | Semiconductor package and its manufacture |
JPH07321246A (en) * | 1994-05-19 | 1995-12-08 | Shinko Electric Ind Co Ltd | Semiconductor device |
US5468999A (en) * | 1994-05-26 | 1995-11-21 | Motorola, Inc. | Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding |
FR2723257B1 (en) * | 1994-07-26 | 1997-01-24 | Sgs Thomson Microelectronics | BGA INTEGRATED CIRCUIT BOX |
US5808873A (en) * | 1997-05-30 | 1998-09-15 | Motorola, Inc. | Electronic component assembly having an encapsulation material and method of forming the same |
-
1996
- 1996-08-12 JP JP8212375A patent/JP2959480B2/en not_active Expired - Fee Related
-
1997
- 1997-08-12 US US08/909,963 patent/US6037656A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6037656A (en) | 2000-03-14 |
JPH1056098A (en) | 1998-02-24 |
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