JPH04120771A - Delay cell for master slice system ic device - Google Patents
Delay cell for master slice system ic deviceInfo
- Publication number
- JPH04120771A JPH04120771A JP2241995A JP24199590A JPH04120771A JP H04120771 A JPH04120771 A JP H04120771A JP 2241995 A JP2241995 A JP 2241995A JP 24199590 A JP24199590 A JP 24199590A JP H04120771 A JPH04120771 A JP H04120771A
- Authority
- JP
- Japan
- Prior art keywords
- master slice
- integrated circuit
- capacitor
- circuit device
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 abstract description 20
- 229910052751 metal Inorganic materials 0.000 abstract description 20
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はマスタースライス方式集積回路装置における遅
延回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay circuit in a master slice type integrated circuit device.
従来のマスタースライス方式集積回路装置は、遅延回路
を構成するために、論理回路素子の遅延時間を用いて遅
延回路を構成していた。In a conventional master slice type integrated circuit device, the delay time of a logic circuit element is used to construct a delay circuit.
近年、マスタースライス方式集積回路装置の論理回路素
子の遅延時間は、高速化してきており、論理回路素子で
あるインバータの遅延時間は、Ｉｎｓを下回るようにな
ってきている。よって、前述の従来技術で論理回路素子
の遅延時間を用いて遅延回路を構成しようとすると、論
理回路素子数が増加し集積回路装置の面積が増加する。In recent years, the delay time of logic circuit elements in master slice integrated circuit devices has become faster, and the delay time of inverters, which are logic circuit elements, has become less than Ins. Therefore, if an attempt is made to construct a delay circuit using the delay time of the logic circuit elements using the above-mentioned prior art, the number of logic circuit elements will increase and the area of the integrated circuit device will increase.
そのため、集積回路のコストの増加、集積回路の大型化
という問題点を有する。Therefore, there are problems in that the cost of the integrated circuit increases and the integrated circuit becomes larger.
そこで本発明は、このような問題点を解決するもので、
その目的とするところはマスタースライス方式集積回路
装置の面積を増加させることなく、遅延回路を構成する
ことを目的とする。Therefore, the present invention aims to solve these problems.
The purpose is to configure a delay circuit without increasing the area of a master slice type integrated circuit device.
本発明のマスタースライス方式集積回路装置用遅延セル
は、
ａ）マスタースライス方式集積回路装置の入出力セル領
域内に配置されたセルにおいて、ｂ）前ｇ己セル番よキ
ャパシタと、
Ｃ）信号配線接続端子と、
ｄ）電源配線接続端子とを有し、
ｅ）前記キャパシタの第一電極は、前記信号配線接続端
子と接続され、前記キャパシタの第二電極は、前記電源
配線接続端子と電気的に接続されており、
ｆ）前記キャパシタの断面構造は、上層から、電源配線
層、電気的絶縁層、信号配線層、電気的絶縁層、マスタ
ースライス方式集積回路装置基板の順に構成され、
ｇ）前記マスタースライス方式集積回路装置基板と電源
配線層とは、同電位であることを特徴とするマスタース
ライス方式集積回路装置用遅延セル。The delay cell for a master slice integrated circuit device of the present invention includes: a) a cell arranged in the input/output cell area of the master slice integrated circuit device, b) a capacitor according to the previous cell number, and C) signal wiring. and d) a power supply wiring connection terminal, e) the first electrode of the capacitor is connected to the signal wiring connection terminal, and the second electrode of the capacitor is electrically connected to the power supply wiring connection terminal. f) The cross-sectional structure of the capacitor is configured in the following order from the upper layer: a power supply wiring layer, an electrical insulation layer, a signal wiring layer, an electrical insulation layer, and a master slice integrated circuit device substrate; g) A delay cell for a master slice integrated circuit device, wherein the master slice integrated circuit device substrate and the power wiring layer are at the same potential.
第１図は、本発明の一実施例におけるマスタースライス
方式集積回路装置用遅延セル全体の平面図であり、１０
１はマスタースライス方式集積回路装置用遅延セル、１
０２は第一層目金属配線、１０３は第二層目金属配線、
１０４はパッド電極開口部であり、パッド電極開口部１
０４の下には、第一層目金属配線１０２と第二層目金属
配線１０３とが、電気的絶縁膜を挟んで配置され、キャ
パシタを構成する。１０５は電源配線接続端子、１０６
は信号配線接続端子であり、電源配線接続端子１０５は
、マスタースライス方式集積回路装置基板と同じ電圧が
供給され、信号配線接続端子１０６は、遅延を付けたい
信号配線に接続する。FIG. 1 is a plan view of the entire delay cell for a master slice type integrated circuit device in one embodiment of the present invention, and is
1 is a delay cell for a master slice type integrated circuit device;
02 is the first layer metal wiring, 103 is the second layer metal wiring,
104 is a pad electrode opening, and pad electrode opening 1
04, a first layer metal wiring 102 and a second layer metal wiring 103 are arranged with an electrical insulating film in between, forming a capacitor. 105 is a power supply wiring connection terminal, 106
is a signal wiring connection terminal, the power supply wiring connection terminal 105 is supplied with the same voltage as the master slice type integrated circuit device board, and the signal wiring connection terminal 106 is connected to the signal wiring to which a delay is to be added.
なお、マスタースライス方式集積回路装置用遅延セルは
、マスタースライス方式集積回路装置の入出力セル配置
領域内の任意の位置に配置できるようにセル化されてい
る。Note that the delay cell for the master slice integrated circuit device is formed into cells so that it can be placed at any position within the input/output cell arrangement area of the master slice integrated circuit device.
第２図は、第１図の線ａにおける垂直縦方向の断面図で
あり、２０１，２０３，２０５は電気的絶縁膜、２０２
は第一層目金属配線であり、電源配線に接続される。２
０４は第二層目金属配線であり、信号配線と接続する。FIG. 2 is a vertical cross-sectional view taken along line a in FIG.
is the first layer metal wiring and is connected to the power supply wiring. 2
04 is a second layer metal wiring, which is connected to the signal wiring.
２０６はマスタースライス方式集積回路装置基板、２０
７はパッド電極開口部である。前記第一層目金属配線２
０２と、前記第二層目金属配線２０４との間に第一のキ
ャパシタが形成され、同じく、前記第二層目金属配線２
０４とマスタースライス方式集積回路装置基板２０６と
の間に第二のキャパシタが形成される。206 is a master slice type integrated circuit device board, 20
7 is a pad electrode opening. Said first layer metal wiring 2
A first capacitor is formed between the second layer metal wiring 204 and the second layer metal wiring 204.
A second capacitor is formed between the master slice integrated circuit device substrate 206 and the master slice integrated circuit device substrate 206 .
また、第２図の２０２，２０４，２０７は、それぞれ第
１図の１０２． １０３，１０４と等しい。202, 204, 207 in FIG. 2 are respectively 102. in FIG. 1. Equal to 103 and 104.
第３図は、本発明の一実施例におけるマスタースライス
方式集積回路装置の一部平面図であり、３０１はマスタ
ースライス方式集積回路装置、３０２はリードフレーム
、３０３はトランジスタ配置領域、３０４ ハＶ Ｄ
Ｄ側電源配線、３０５はＶＳＳ側電源配線、３０６は本
発明のマスタースライス方式集積回路装置用遅延セル（
以下、遅延セルと略す）であり、遅延セル３０６は、前
記第１図及び、第２図に示された構造をなしている。３
１０は信号配線、３１１，３１２は論理回路素子であり
、論理回路素子３１１の出力は、論理回路素子３１２の
入力と遅延セル３０６の信号配線接続端子に接続される
。３０７は入出力セル、３０８はパッド電極開口部、３
０９はボンディングワイヤーであり、前記遅延セル３０
６の配置位置は、前記人出力セル３０７の配置されてい
ない、入出力セル配’ｌ１ｆＡ域内に配置され、前記信
号配線３１０は、信号配線接続端子に電気的接続され、
前記ｖＳＳ側電源配線３０５は、電源配線接続端子に電
気的に接続される。前記実施例では、マスタースライス
方式集積回路装置基板の電位がｖＳＳの場合である。な
お、マスタースライス方式集積回路多量基板の電位がＶ
ＤＤの場合、遅延セルの電源接続端子は、ＶＤＤに電気
的に接続する。FIG. 3 is a partial plan view of a master slice integrated circuit device according to an embodiment of the present invention, in which 301 is a master slice integrated circuit device, 302 is a lead frame, 303 is a transistor arrangement area, and 304 is a V D
D side power supply wiring, 305 is VSS side power supply wiring, 306 is a delay cell for master slice type integrated circuit device of the present invention (
(hereinafter abbreviated as delay cell), and the delay cell 306 has the structure shown in FIGS. 1 and 2. 3
10 is a signal wiring; 311 and 312 are logic circuit elements; the output of the logic circuit element 311 is connected to the input of the logic circuit element 312 and the signal wiring connection terminal of the delay cell 306; 307 is an input/output cell, 308 is a pad electrode opening, 3
09 is a bonding wire, and the delay cell 30
The arrangement position No. 6 is arranged in the input/output cell arrangement '11fA area where the human output cell 307 is not arranged, and the signal wiring 310 is electrically connected to the signal wiring connection terminal,
The vSS side power supply wiring 305 is electrically connected to a power supply wiring connection terminal. In the embodiment described above, the potential of the master slice type integrated circuit device substrate is vSS. It should be noted that the potential of the master slicing integrated circuit board is V.
In the case of DD, the power supply connection terminal of the delay cell is electrically connected to VDD.
なお、前記遅延セル３０６の使用個数は、任意である。Note that the number of delay cells 306 used is arbitrary.
第４図は、第３図における線すの断面図と等価回路を示
した電気回路図であり、４０１は本発明のマスタースラ
イス方式集積回路装置用遅延セル、４０２．４０３は論
理回路素子、４０４は信号配線、４０５はＶＳＳ側電源
配線であり、論理回路素子４０２の出力は、論理回路素
子４０３の入力と遅延セル４０１の信号配線接続端子と
に接続される。４０６は第一層目金属配線と第二層目金
層配線との間に形成されるキャパシタを示し、４０７は
第二層目金属配線とマスタースライス方式集積回路装置
基板との間に形成されるキャパシタを示す。FIG. 4 is an electric circuit diagram showing a cross-sectional view of the wires and an equivalent circuit in FIG. is a signal wiring, 405 is a VSS side power supply wiring, and the output of the logic circuit element 402 is connected to the input of the logic circuit element 403 and the signal wiring connection terminal of the delay cell 401. Reference numeral 406 indicates a capacitor formed between the first layer metal wiring and the second layer gold layer wiring, and 407 indicates a capacitor formed between the second layer metal wiring and the master slice type integrated circuit device substrate. Shows a capacitor.
なお、第４図に示されている４０１，４０２゜４０３．
４０４，４０５は、それぞれ、第３図の３０６．３１１
，３１２，３１０，３０５と同じものを示す。Note that 401, 402°, 403. as shown in FIG.
404 and 405 are 306 and 311 in Fig. 3, respectively.
, 312, 310, and 305.
以上、述べたように本発明によれば、マスタースライス
方式集積回路装置の入出力セル配置領域内にキャパシタ
を設け、このキャパシタをＶＳＳ側電源配線と信号配線
とに接続する構造にしたため、マスタースライス方式集
積回路装置の面積を増加させることなく、遅延回路を構
成することが可能となる。また、信号配線層を、電源配
線層とマスタースライス方式集積回路装置基板とにより
はさみこみ、電源配線層とマスタースライス方式集積回
路装置基板とを同電位にすることにより、電気的容量の
大きいキャパシタを作成することができる。これにより
、集積回路のコストの低下、集積回路の小型化、集積回
路装置の安定動作などの効果を有する。As described above, according to the present invention, a capacitor is provided in the input/output cell arrangement area of a master slice integrated circuit device, and this capacitor is connected to the VSS side power supply wiring and signal wiring, so that the master slice It becomes possible to configure a delay circuit without increasing the area of the integrated circuit device. In addition, a capacitor with a large electrical capacity is created by sandwiching the signal wiring layer between the power supply wiring layer and the master slice integrated circuit device substrate, and by making the power supply wiring layer and the master slice integrated circuit device substrate have the same potential. can do. This has the effect of reducing the cost of integrated circuits, reducing the size of integrated circuits, and stabilizing the operation of integrated circuit devices.
第１図は、本発明の一実施例におけるマスクスライス方
式集積回路装置用遅延セル全体の平面図。
１０１・・・マスタースライス方式集積回路装置用遅延
セル
１０２・・・第一層目金属配線
１０３・・・第二層目金属配線
１０４・・・パッド電極開口部
１０５・・・電源配線接続端子
１０６・・・信号配線接続端子
第２図は、第１図の線ａにおける垂直縦方向の断面図。
２０１．２０３，２０５・・・電気的絶縁膜２０２・・
・第一層目金属配線
２０４・・・第二層目金属配線
２０６・・・マスタースライス方式集積回路装置基板
２０７・・・パッド電極開口部
第３図は、本発明の一実施例におけるマスタースライス
方式集積回路装置の一部平面図。
３０１・・・マスタースライス方式集積回路装置３０２
・・・リードフレーム
３０３・・・トランジスタ配置領域
３０４・・・ＶＤＤ側電源配線
３０５・・・ＶＳＳ側電源配線
３０６・・・マスタースライス方式集積回路装置用遅延
セル
３０７・・・入出力セル
３０８・・・パッド電極
３０９・・・ボンディングワイヤー
３１０・・・信号配線
３１１．３１２・・・論理回路素子
第４図は、第３図における線すの断面図と等価回路を示
した電気回路図。
４０１・・・マスタースライス方式集積回路装置用遅延
セル
４０２．４０３・・・論理回路素子
４０４・・・信号配線
４０５・・・ＶＳＳ側電源配線
４０６・・・第一層目金属配線層と第二層目金属配線層
との間に形成されるキャパシ
タ
４０７・・・第二層目金属配線層とマスタースライス方
式集積回路装置基板との間に
形成されるキャパシタ
以 上FIG. 1 is a plan view of the entire delay cell for a mask slice integrated circuit device in one embodiment of the present invention. 101... Delay cell for master slice type integrated circuit device 102... First layer metal wiring 103... Second layer metal wiring 104... Pad electrode opening 105... Power supply wiring connection terminal 106 . . . Signal wiring connection terminal FIG. 2 is a vertical cross-sectional view taken along line a in FIG. 1. 201.203,205... Electrical insulating film 202...
・First layer metal wiring 204...Second layer metal wiring 206...Master slice type integrated circuit device substrate 207...Pad electrode opening FIG. 3 shows a master slice in one embodiment of the present invention. FIG. 2 is a partial plan view of the integrated circuit device. 301... Master slice type integrated circuit device 302
. . . Lead frame 303 . ...Pad electrode 309...Bonding wire 310...Signal wiring 311, 312...Logic circuit element FIG. 4 is an electric circuit diagram showing a cross-sectional view of the wires in FIG. 401...Delay cell for master slice type integrated circuit device 402.403...Logic circuit element 404...Signal wiring 405...VSS side power supply wiring 406...First layer metal wiring layer and second layer Capacitor 407 formed between the second metal wiring layer...capacitor formed between the second metal wiring layer and the master slice integrated circuit device substrate
Claims (1)
域内に配置されたセルにおいて、 ｂ）前記セルはキャパシタと、 ｃ）信号配線接続端子と、 ｄ）電源配線接続端子とを有し、 ｅ）前記キャパシタの第一電極は、前記信号配線接続端
子と接続され、前記キャパシタの第二電極は、前記電源
配線接続端子と電気的に接続されており、 ｆ）前記キャパシタの断面構造は、上層から、電源配線
層、電気的絶縁層、信号配線層、電気的絶縁層、マスタ
ースライス方式集積回路装置基板の順に構成され、 ｇ）前記マスタースライス方式集積回路装置基板と電源
配線層とは、同電位であることを特徴とするマスタース
ライス方式集積回路装置用遅延セル。[Claims] a) A cell arranged in an input/output cell area of a master slice integrated circuit device, b) the cell includes a capacitor, c) a signal wiring connection terminal, and d) a power supply wiring connection terminal. e) a first electrode of the capacitor is connected to the signal wiring connection terminal, and a second electrode of the capacitor is electrically connected to the power supply wiring connection terminal; and f) of the capacitor. The cross-sectional structure is composed of a power wiring layer, an electrical insulating layer, a signal wiring layer, an electrical insulating layer, and a master slice integrated circuit device substrate in this order from the upper layer, and g) the master slice integrated circuit device substrate and the power supply wiring. A delay cell for a master slice type integrated circuit device, which is characterized in that the layers have the same potential.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2241995A JPH04120771A (en) | 1990-09-12 | 1990-09-12 | Delay cell for master slice system ic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2241995A JPH04120771A (en) | 1990-09-12 | 1990-09-12 | Delay cell for master slice system ic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04120771A true JPH04120771A (en) | 1992-04-21 |
Family
ID=17082686
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2241995A Pending JPH04120771A (en) | 1990-09-12 | 1990-09-12 | Delay cell for master slice system ic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04120771A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6476459B2 (en) * | 1998-07-15 | 2002-11-05 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit device with capacitor formed under bonding pad |
| JP2012164910A (en) * | 2011-02-09 | 2012-08-30 | Lapis Semiconductor Co Ltd | Semiconductor integrated circuit, semiconductor chip, and design approach of semiconductor integrated circuit |
-
1990
- 1990-09-12 JP JP2241995A patent/JPH04120771A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6476459B2 (en) * | 1998-07-15 | 2002-11-05 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit device with capacitor formed under bonding pad |
| JP2012164910A (en) * | 2011-02-09 | 2012-08-30 | Lapis Semiconductor Co Ltd | Semiconductor integrated circuit, semiconductor chip, and design approach of semiconductor integrated circuit |
| US8907711B2 (en) | 2011-02-09 | 2014-12-09 | Lapis Semiconductor Co., Ltd. | Integrated circuit having latch circuits and using delay circuits to fetch data bits in synchronization with clock signals |
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