JPH01185943A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH01185943A JPH01185943A JP63011335A JP1133588A JPH01185943A JP H01185943 A JPH01185943 A JP H01185943A JP 63011335 A JP63011335 A JP 63011335A JP 1133588 A JP1133588 A JP 1133588A JP H01185943 A JPH01185943 A JP H01185943A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- substrate
- electrode pad
- hole
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000000463 material Substances 0.000 claims abstract description 6
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 14
- 239000004020 conductor Substances 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000009434 installation Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 210000004709 eyebrow Anatomy 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に関し、特に装置基板の表
裏両面に形成した回路を相互に接続する構造を有する半
導体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a structure in which circuits formed on both the front and back surfaces of a device substrate are interconnected.
従来、半導体集積回路装置では、第４図に示すように、
半導体集積回路基板の中央領域に内部回路部ｌを形成し
、その周囲に入出力回路部２を形成し、更にその周囲に
電極パッド３を配設した構成となついる。この電極パッ
ド３は基板に設けた回路配線によって前記入出力回路部
２に接続されており、ここにボンディングワイヤを接続
することにより外部への電気接続が行われる。このため
、電極パッド３はボンディングワイヤを接続することが
できるように所定以上の寸法に形成する必要がある。Conventionally, in a semiconductor integrated circuit device, as shown in FIG.
The internal circuit section 1 is formed in the central region of the semiconductor integrated circuit board, the input/output circuit section 2 is formed around the internal circuit section 1, and the electrode pads 3 are arranged around the internal circuit section 1. This electrode pad 3 is connected to the input/output circuit section 2 by circuit wiring provided on the substrate, and electrical connection to the outside is achieved by connecting a bonding wire here. For this reason, the electrode pad 3 needs to be formed to have a predetermined size or more so that the bonding wire can be connected thereto.
第５図はその一例の断面構造であり、基板１１は厚い酸
化膜１２で画成された領域に素子拡散層１３を形成し、
これで内部回路部や入出力回路部を構成している。そし
て、この上には層間絶縁膜１４、下層配線１５９層間絶
縁膜１６を順次形成し、この上に上層配線１７を形成し
ている。そして、この上層配線１７を覆う絶縁膜１８の
一部に窓１８ａを設け、この窓１８ａにおいて露呈され
る上層配線１７の一部を電極パッド３として構成してい
る。FIG. 5 shows a cross-sectional structure of an example, in which a substrate 11 has an element diffusion layer 13 formed in a region defined by a thick oxide film 12,
This constitutes the internal circuit section and input/output circuit section. Then, an interlayer insulating film 14, a lower layer interconnect 159, and an interlayer insulating film 16 are sequentially formed on this, and an upper layer interconnect 17 is formed on this. A window 18a is provided in a part of the insulating film 18 covering the upper layer wiring 17, and the part of the upper layer wiring 17 exposed in the window 18a is configured as the electrode pad 3.
（発明が解決しようとする課題〕
上述した従来の集積回路装置では、集積回路装置の高集
積化に伴って電極パッド３の数が増大されると、これに
より第４図に示したように電極パッド３の配設スペース
も増大し、したがって入出力回路部２及び内部回路部１
の配設スペースが低減され、これらの回路に制限を受け
、高集積化が困難になるという問題がある。また、逆に
電極パッド３の数が制限されることもあり、回路設計の
自由度が損なわれることになる。(Problems to be Solved by the Invention) In the above-mentioned conventional integrated circuit device, when the number of electrode pads 3 increases as the integrated circuit device becomes more highly integrated, the number of electrode pads 3 increases as shown in FIG. The space for arranging the pad 3 also increases, and therefore the input/output circuit section 2 and the internal circuit section 1
There is a problem in that the installation space for these circuits is reduced, and these circuits are restricted, making it difficult to achieve high integration. Moreover, the number of electrode pads 3 may be limited, conversely, and the degree of freedom in circuit design will be impaired.
本発明は電極パッドの増大する一方で回路部の配設スペ
ースの減少を防止することを可能にした半導体集積回路
装置を提供することを目的としている。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device which makes it possible to prevent a decrease in the installation space of a circuit section even as the number of electrode pads increases.
本発明の半導体集積回路装置は、半導体基板の裏面周辺
部に電極パッドを配設するとともに、半導体基板の表面
周辺部にはこの電極パッドに対応してスルーホール部を
配設し、この電極パッドとスルーホール部とを半導体基
板を貫通するロッド状の配線材により相互に電気的に接
続し、かつ半導体基板の表面側ではスルーホール部の周
囲に入出力回路部を配設した構成としている。In the semiconductor integrated circuit device of the present invention, electrode pads are arranged around the back surface of the semiconductor substrate, and through-holes are arranged corresponding to the electrode pads around the front surface of the semiconductor substrate. and the through-hole portion are electrically connected to each other by a rod-shaped wiring member penetrating the semiconductor substrate, and an input/output circuit portion is arranged around the through-hole portion on the front side of the semiconductor substrate.
上述した構成の半導体集積回路装置では、電極パッドを
基板の裏面に配設し、表面側では微小面積のスルーホー
ル部を配設してその周囲に入出力回路部を配設するので
、その分向部回路部の面積を増大し、かつ基板の表裏面
を有効に利用した回路装置を構成することが可能となる
。In the semiconductor integrated circuit device having the above-mentioned configuration, electrode pads are arranged on the back side of the substrate, and a through-hole section with a minute area is arranged on the front side, and the input/output circuit section is arranged around it. It becomes possible to increase the area of the facing circuit section and to configure a circuit device that effectively utilizes the front and back surfaces of the substrate.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示し、同図（ａ）は一部の
表面図、同図（ｂ）は裏面図である。FIG. 1 shows an embodiment of the present invention, with FIG. 1(a) being a partial front view and FIG. 1(b) being a back view.
この半導体集積回路装置は、チップの周辺部に配設する
電極バッド３をチップ裏面に配設し、チップ表面には内
部回路部１や入出力回路部２に接続される回路４に接続
されたスルーホール部５を配設している。そして、チッ
プ表面では入出力回路部２を、このスルーホール部５の
周囲に配設し、その分向部回路部１の面積を周辺方向に
拡大させている。This semiconductor integrated circuit device has electrode pads 3 disposed around the periphery of the chip on the back side of the chip, and electrode pads 3 on the chip surface connected to a circuit 4 connected to an internal circuit section 1 and an input/output circuit section 2. A through hole portion 5 is provided. The input/output circuit section 2 is arranged around the through hole section 5 on the chip surface, and the area of the circuit section 1 is expanded in the peripheral direction.
第２図はその一部の断面図である。半導体集積回路装置
のチップを構成する基板１１は、表面側では厚い酸化膜
１２で画成された領域に素子拡散層１３を形成し、これ
で内部回路部や入出力回路部を構成している。そして、
この上には眉間絶縁膜１４．下層配線１５３層間絶縁膜
１６を順次形成し、この上に上層配線１７及び絶縁膜１
８を形成している。FIG. 2 is a sectional view of a part thereof. A substrate 11 constituting a chip of a semiconductor integrated circuit device has an element diffusion layer 13 formed on the front side in a region defined by a thick oxide film 12, and constitutes an internal circuit section and an input/output circuit section. . and,
On top of this is an insulating film 14 between the eyebrows. Lower layer wiring 153 and interlayer insulating film 16 are sequentially formed, and upper layer wiring 17 and insulating film 1 are formed thereon.
8 is formed.
また、基板１１の裏面側では必要な回路部を適宜形成す
るとともに、その面上に形成した絶縁膜１９上には配線
２０で電極パッド３を形成し、絶縁膜２１で周囲を覆っ
ている。Further, necessary circuit sections are appropriately formed on the back surface side of the substrate 11, and electrode pads 3 are formed with wiring 20 on an insulating film 19 formed on that surface, and the periphery is covered with an insulating film 21.
そして、前記基板１１の厚さ方向に貫通孔２２を開設し
、ここに周面を絶縁コーテイング膜２４で被覆されたロ
ッド状の配線材２３を挿通し、かつその上下端を夫々前
記上層配線１７．電極パッド３としての配線２０に接続
することにより、上層配線１７の一部に形成したスルー
ホール部５を電極パッド３に電気接続させている。Then, a through hole 22 is formed in the thickness direction of the substrate 11, and a rod-shaped wiring member 23 whose peripheral surface is covered with an insulating coating film 24 is inserted through the through hole 22, and the upper and lower ends thereof are connected to the upper layer wiring 17, respectively. ．． By connecting to the wiring 20 as the electrode pad 3, the through hole portion 5 formed in a part of the upper layer wiring 17 is electrically connected to the electrode pad 3.
このスルーホール部５の製造方法を第３図（ａ）乃至第
３図（ｄ）の模式的な断面図で説明する。A method of manufacturing this through-hole portion 5 will be explained with reference to schematic cross-sectional views shown in FIGS. 3(a) to 3(d).
先ず、第３図（ａ）のように、半導体基板３１の表面に
酸化膜３２と絶縁膜３３．３４を形成し、裏面に絶縁膜
３５を形成する。First, as shown in FIG. 3(a), an oxide film 32 and insulating films 33 and 34 are formed on the front surface of a semiconductor substrate 31, and an insulating film 35 is formed on the back surface.
次に、第３図（ｂ）のように、半導体基板３１にレーザ
ビームを照射し、基板の表裏を貫通する孔３６を開設す
る。そして、周囲を絶縁材３８でコーティングされたロ
ッド状の導体３７を基板の厚さに切断し、その両端を露
呈させた上で第３図（ｃ）のように貫通孔３６内に挿入
する。Next, as shown in FIG. 3(b), the semiconductor substrate 31 is irradiated with a laser beam to form a hole 36 passing through the front and back of the substrate. Then, a rod-shaped conductor 37 whose periphery is coated with an insulating material 38 is cut to the thickness of the substrate, and with both ends exposed, the rod-shaped conductor 37 is inserted into the through hole 36 as shown in FIG. 3(c).
しかる上で、第３図（ｄ）のように、前記基板の表面側
絶縁膜３４及び裏面側絶縁膜３５の各露呈面に対してメ
タライズ処理を施し、夫々に導体１０３９．４０を形成
する。このメタライズにより、前記導体３７の両端は夫
々導体膜３９．４０に電気的に接続され、これで両導体
膜３９．４０が電気接続される。Then, as shown in FIG. 3(d), a metallization process is performed on each exposed surface of the front side insulating film 34 and the back side insulating film 35 of the substrate to form conductors 1039 and 40, respectively. Due to this metallization, both ends of the conductor 37 are electrically connected to the conductor films 39, 40, respectively, and thus both the conductor films 39, 40 are electrically connected.
したがって、前記第２図の構成において、ロッド状の配
線材２３を第３図の方法により基板１１内に埋設させる
ことにより、上層配線１７を配線２０に接続できる。こ
れにより、基板１１の表面側の回路４に接続されている
スルーホール部５を裏面側に設けた電極パッド３に電気
接続し、この電極パッド３を通して外部への電気接続を
行うことができる。したがって、従来外部接続用バット
を配置していた基板の表面領域には小さな面積のスルー
ホール部５を設けるのみでよ（、その周辺を入出力回路
部２として使用することにより、内部回路部１の面積を
第４図に示した従来のものに比較して大幅に増大できる
。Therefore, in the configuration shown in FIG. 2, the upper layer wiring 17 can be connected to the wiring 20 by embedding the rod-shaped wiring material 23 in the substrate 11 by the method shown in FIG. Thereby, the through-hole portion 5 connected to the circuit 4 on the front side of the substrate 11 can be electrically connected to the electrode pad 3 provided on the back side, and electrical connection to the outside can be made through this electrode pad 3. Therefore, it is only necessary to provide a small-area through-hole section 5 in the surface area of the board where the external connection bat has conventionally been placed (by using the area around it as the input/output circuit section 2, The area can be greatly increased compared to the conventional one shown in FIG.
なお、ロッド状配線材２３は周面に絶縁コーテイング膜
２４を施しているため基板１１とは電気的に絶縁状態を
保持することができる。Note that since the rod-shaped wiring member 23 has an insulating coating film 24 applied to its peripheral surface, it can maintain an electrically insulated state from the substrate 11.
以上説明したように本発明は、半導体基板の裏面周辺部
に配設した電極パッドと、表面周辺部に配設したスルー
ホール部とを半導体基板を貫通するロッド状の配線材に
より相互に電気的に接続しているので、表面側では微小
面積のスルーホール部を配設するのみでよく、スルーホ
ール部の周囲に入出力回路部を配設でき、その分向部回
路部の面積を増大し、かつ基板の両面有効利用を図り、
高集積度の回路装置を構成できる効果がある。As explained above, the present invention connects the electrode pads arranged around the back side of the semiconductor substrate and the through-hole parts arranged around the front side to each other electrically by means of a rod-shaped wiring material penetrating the semiconductor substrate. Since it is connected to the front side, it is only necessary to arrange a through-hole section with a small area on the front side, and the input/output circuit section can be arranged around the through-hole section, which increases the area of the circuit section in that direction. , and effectively utilize both sides of the board.
This has the effect of making it possible to configure a highly integrated circuit device.
第１図（ａ）及び（ｂ）は本発明の一実施例の一部の表
面図及び裏面図、第２図は本発明の一実施例の要部の拡
大断面図、第３図（ａ）乃至第３図（ｄ）は製造方法の
一例を工程順に示す模式的な断面図、第４図は従来構造
の半導体集積回路装置の一部の表面図、第５図は従来構
造の一部の拡大断面図である。
１・・・内部回路部、２・・・入出力回路部、３・・・
電極パッド、４・・・回路、５・・・スルーホール、１
１・・・基板、１２・・・厚い酸化膜、１３・・・拡散
層、１４・・・層間絶縁膜、１５・・・下層配線、１６
・・・層間絶縁膜、１７・・・上層配線、１８・・・絶
縁膜、１９・・・絶縁膜、２０・・・配線、２１・・・
絶縁膜、２２・・・貫通孔、２３・・・配線材、２４・
・・絶縁コーテイング膜、３１・・・基板、３２・・・
酸化膜、３３．３４・・・絶縁膜、３５・・・絶縁膜、
３６・・・貫通孔、３７・・・絶縁材、３８・・・絶縁
コーテイング膜、３９．４０・・・導体膜。
第３図1(a) and (b) are front and back views of a part of an embodiment of the present invention, FIG. 2 is an enlarged sectional view of a main part of an embodiment of the present invention, and FIG. 3(a) ) to 3(d) are schematic cross-sectional views showing an example of the manufacturing method in the order of steps, FIG. 4 is a surface view of a part of a semiconductor integrated circuit device with a conventional structure, and FIG. 5 is a part of a conventional structure. FIG. 1... Internal circuit section, 2... Input/output circuit section, 3...
Electrode pad, 4... Circuit, 5... Through hole, 1
DESCRIPTION OF SYMBOLS 1... Substrate, 12... Thick oxide film, 13... Diffusion layer, 14... Interlayer insulating film, 15... Lower layer wiring, 16
... Interlayer insulating film, 17... Upper layer wiring, 18... Insulating film, 19... Insulating film, 20... Wiring, 21...
Insulating film, 22... Through hole, 23... Wiring material, 24...
...Insulating coating film, 31...Substrate, 32...
Oxide film, 33. 34... Insulating film, 35... Insulating film,
36... Through hole, 37... Insulating material, 38... Insulating coating film, 39.40... Conductor film. Figure 3
Claims (1)
力回路部を有する半導体集積回路装置において、半導体
基板の裏面周辺部に電極パッドを配設するとともに、半
導体基板の表面周辺部にはこの電極パッドに対応してス
ルーホール部を配設し、前記電極パッドとスルーホール
部とを半導体基板を貫通するロッド状の配線材により相
互に電気的に接続し、かつ半導体基板の表面側では前記
スルーホール部の周囲に入出力回路部を配設したことを
特徴とする半導体集積回路装置。1. In a semiconductor integrated circuit device that has an internal circuit section and an input/output circuit section at least on the front side of the semiconductor substrate, electrode pads are arranged around the back side of the semiconductor substrate, and electrode pads are arranged around the front side of the semiconductor substrate. A through-hole portion is provided corresponding to the pad, and the electrode pad and the through-hole portion are electrically connected to each other by a rod-shaped wiring material penetrating the semiconductor substrate, and the through-hole portion is provided on the surface side of the semiconductor substrate. A semiconductor integrated circuit device characterized in that an input/output circuit section is arranged around a hole section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63011335A JPH01185943A (en) | 1988-01-21 | 1988-01-21 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63011335A JPH01185943A (en) | 1988-01-21 | 1988-01-21 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01185943A true JPH01185943A (en) | 1989-07-25 |
Family
ID=11775161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63011335A Pending JPH01185943A (en) | 1988-01-21 | 1988-01-21 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01185943A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5432357A (en) * | 1992-04-16 | 1995-07-11 | Kabushiki Kaisha Kobe Seiko Sho | Diamond film electronic devices |
| US5449929A (en) * | 1992-12-21 | 1995-09-12 | Mitsubishi Denki Kabushiki Kaisha | IPG transistor semiconductor integrated circuit device |
| US5737052A (en) * | 1994-12-07 | 1998-04-07 | International Business Machines Corporation | Liquid crystal display and manufacturing process thereof with drive circuit and active matrix connected via through hole |
| JP2006108236A (en) * | 2004-10-01 | 2006-04-20 | Shinko Electric Ind Co Ltd | Method for manufacturing substrate with through electrode |
| JP2006135233A (en) * | 2004-11-09 | 2006-05-25 | Renesas Technology Corp | Semiconductor device and manufacturing method thereof |
| US7531876B2 (en) | 2004-09-24 | 2009-05-12 | Kabushiki Kaisha Toshiba | Semiconductor device having power semiconductor elements |
| US8115312B2 (en) | 2004-06-30 | 2012-02-14 | Renesas Electronics Corporation | Semiconductor device having a through electrode |
-
1988
- 1988-01-21 JP JP63011335A patent/JPH01185943A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5432357A (en) * | 1992-04-16 | 1995-07-11 | Kabushiki Kaisha Kobe Seiko Sho | Diamond film electronic devices |
| US5449929A (en) * | 1992-12-21 | 1995-09-12 | Mitsubishi Denki Kabushiki Kaisha | IPG transistor semiconductor integrated circuit device |
| US5737052A (en) * | 1994-12-07 | 1998-04-07 | International Business Machines Corporation | Liquid crystal display and manufacturing process thereof with drive circuit and active matrix connected via through hole |
| US8115312B2 (en) | 2004-06-30 | 2012-02-14 | Renesas Electronics Corporation | Semiconductor device having a through electrode |
| US8436468B2 (en) | 2004-06-30 | 2013-05-07 | Renesas Electronics Corporation | Semiconductor device having a through electrode |
| US7531876B2 (en) | 2004-09-24 | 2009-05-12 | Kabushiki Kaisha Toshiba | Semiconductor device having power semiconductor elements |
| JP2006108236A (en) * | 2004-10-01 | 2006-04-20 | Shinko Electric Ind Co Ltd | Method for manufacturing substrate with through electrode |
| JP2006135233A (en) * | 2004-11-09 | 2006-05-25 | Renesas Technology Corp | Semiconductor device and manufacturing method thereof |
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