JPH0745928A - Composite electronic part - Google Patents

Composite electronic part

Info

Publication number
JPH0745928A
JPH0745928A JP18506393A JP18506393A JPH0745928A JP H0745928 A JPH0745928 A JP H0745928A JP 18506393 A JP18506393 A JP 18506393A JP 18506393 A JP18506393 A JP 18506393A JP H0745928 A JPH0745928 A JP H0745928A
Authority
JP
Japan
Prior art keywords
wiring board
wiring
electronic component
face
composite electronic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18506393A
Other languages
Japanese (ja)
Inventor
Takashi Kobayashi
崇司 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP18506393A priority Critical patent/JPH0745928A/en
Publication of JPH0745928A publication Critical patent/JPH0745928A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To omit wiring in multiple layers for a wiring board by arranging at least one electronic part on each of both surfaces of the wiring board so as to face each other and so as to hold the wiring board at the upper surface and the rear surface of at the rear surface and the upper surface of the respective electronic parts. CONSTITUTION:An IC 2 is provided so that a surface 2 faces upward. An electrode, which is formed on an upper surface 2' is connected to an upper surface 1' of a wiring board 1 with a wiring 4 on the wiring board 1 by a wire bonding method. A surface 3' of an IC 3 is made to face a lower surface 1'' of the wiring board 1. The electrode, which is formed on the surface 3', is made to face the connecting part of a wiring 6 on the wiring board 1 through an anisotropic conductive resin 7 and connected to the connecting part. The wiring 6 on the side of the upper surface 1' of the wiring board 1 is connected to the wiring 7 on the side of the lower surface 1' of the wiring board 1 by passing the wiring by way of a through hole 8 provided in the wiring substrate 1. Thus, it is not necessary to form complicated wiring patterns.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、例えばメモリーモジュ
ール、ミラー回路等のハイブリッドIC等の複数個の電
子部品を配線基板の両面に搭載した複合電子部品に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite electronic component in which a plurality of electronic components such as a hybrid IC such as a memory module and a mirror circuit are mounted on both sides of a wiring board.

【0002】[0002]

【従来の技術】ハイブリッドIC等の複合電子部品にお
いて、より集積度を向上させて小型化を図る場合の手法
として、配線基板の両面に電子部品を搭載する方法があ
る。従来、この方法において、例えば上記電子部品とし
てベアチップICを配線基板の両面に対向させて配置さ
せる場合、その実装構造の概略断面図を図10に示すよ
うに、配線基板21の上面及び下面を問わず、ベアチッ
プIC22,23は、その表面(電極形成面)22’,
23’を上記配線基板21に対して上側にして、換言す
れば上記配線基板21の両面におけるベアチップIC2
2,23の裏面22”,23”で配線基板21を狭持す
るようにして搭載され、ベアチップIC22,23の表
面22’,23’に形成された電極と配線基板21の配
線とをワイヤボンディング方式により接続するという構
造とされていた。
2. Description of the Related Art In composite electronic parts such as hybrid ICs, there is a method of mounting electronic parts on both sides of a wiring board as a method for further improving the degree of integration and reducing the size. Conventionally, in this method, for example, when bare chip ICs as the above-mentioned electronic parts are arranged facing both sides of a wiring board, the upper surface and the lower surface of the wiring board 21 may be arranged as shown in the schematic sectional view of the mounting structure in FIG. First, the bare chip ICs 22 and 23 have surface (electrode forming surface) 22 ',
23 ′ is on the upper side of the wiring board 21, in other words, the bare chip ICs 2 on both surfaces of the wiring board 21.
Wire bonding is performed between the electrodes formed on the front surfaces 22 ′ and 23 ′ of the bare chip ICs 22 and 23 and the wirings of the wiring board 21, which are mounted so as to sandwich the wiring board 21 between the back surfaces 22 ″ and 23 ″ of the wiring boards 2 and 23. It was structured to connect by the method.

【0003】また、上記方法において、例えばモールド
パッケージICを配線基板の両面に搭載する場合、図1
1に示すように、配線基板21の両面におけるモールド
パッケージIC25,26は、やはりその表面(素子形
成面側)25’,26’を上記配線基板21に対して上
側になるように搭載され、モールドパッケージIC2
5,26のアウターリード27を配線基板21の配線に
半田付け等により接続するという構造とされていた。
Further, in the above method, for example, when the mold package ICs are mounted on both sides of the wiring board, as shown in FIG.
As shown in FIG. 1, the mold package ICs 25 and 26 on both surfaces of the wiring board 21 are mounted such that their surfaces (element forming surface side) 25 ′ and 26 ′ are on the upper side of the wiring board 21 and are molded. Package IC2
The outer leads 27 of 5, 26 are connected to the wiring of the wiring board 21 by soldering or the like.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上記の
ような従来の方法により配線基板の両面に電子部品を対
向配置すると、該対向配置する電子部品同士が、例えば
同種又は類似するものである場合等、電源端子用、接地
端子用、入力端子用、出力端子用等の電極の配列を同一
もしくは類似とするときは、配線を用いて上記電子部品
の電極同士を接続して共通に導出するか、もしくは何れ
の電極同士をも単一の外部導出端子に接続できるように
配線を近接して引き出すようにする必要があるので、配
線基板両面において配線が長くしかも非常に複雑なパタ
ーンとなってしまう。
However, when the electronic components are arranged facing each other on both sides of the wiring board by the conventional method as described above, the electronic components arranged facing each other are, for example, the same or similar. , When the electrodes of the power supply terminal, the ground terminal, the input terminal, the output terminal, etc. are arranged to be the same or similar, the electrodes of the electronic component are connected to each other by using wiring or are commonly led out, Alternatively, since it is necessary to draw out the wirings closely so that any of the electrodes can be connected to a single external lead-out terminal, the wirings are long on both sides of the wiring board and become a very complicated pattern.

【0005】即ち、図12及び図13に示すように、配
線基板21の両面に、例えば同種のベアチップIC2
2,23を対向配置して上記ベアチップIC22の電極
1とベアチップIC23の電極a1といったふうにベア
チップIC22と23とで共通する電極同士を配線基板
21の配線により接続する場合について説明すると、同
種のベアチップICA1,A2を配線基板21の両面
に、各々ベアチップICA1,A2が該配線基板21に
対して電極形成面を上側にして対向配置すると、上記配
線基板21の上面と下面とでベアチップICA1,A2
の電極a1,a2,a3,a4の位置が反転して対辺側にな
るため、接続のための配線を対辺まで延ばさないと配線
基板21の両面で共通の電極を接続できず、そのために
配線が配線基板21両面で長く且つ複雑に張り巡らせた
パターンとせざるおえないのである。従って、配線の占
める面積は大きくなり、高集積化の妨げとなる原因にな
っている。
That is, as shown in FIGS. 12 and 13, for example, bare chip ICs 2 of the same kind are formed on both surfaces of the wiring board 21.
To describe the case where 2,23 to face arranged to connect the wiring electrodes a 1 and interconnect the common electrode together with the bare chip IC22 Fu such electrodes a 1 of the bare chip IC23 and 23 and the substrate 21 of the bare chip IC22, allogeneic When the bare chips ICA1 and A2 are arranged on both surfaces of the wiring board 21 so that the bare chips ICA1 and A2 face the wiring board 21 with the electrode forming surface facing upward, the bare chips ICA1 and A2
Since the positions of the electrodes a 1 , a 2 , a 3 , and a 4 of FIG. 2 are reversed to the opposite side, the common electrode cannot be connected on both sides of the wiring board 21 unless the wiring for connection is extended to the opposite side. For this reason, the wiring must be a long and complicated pattern on both sides of the wiring board 21. Therefore, the area occupied by the wiring becomes large, which is a cause of hindering high integration.

【0006】そこで、上記配線の面積の問題を解消する
ために、配線基板21を多層構造としその層間に配線を
通す方法も行われているが、やはり配線は複雑となり、
このような配線基板を製造するために別途設備が必要で
工程数も増え高コストとなってしまう。また、配線が交
差したり近接することにより、配線相互の干渉によるク
ロストーク等のノイズが発生することに起因する信頼性
の低下という問題もあるのである。
Therefore, in order to solve the problem of the area of the wiring, a method of forming the wiring substrate 21 in a multilayer structure and passing the wiring between the layers is also performed, but the wiring becomes complicated, too.
Separate equipment is required to manufacture such a wiring board, resulting in an increase in the number of steps and a high cost. Further, there is also a problem that reliability decreases due to noise such as crosstalk due to mutual interference between wirings due to the wirings crossing or approaching each other.

【0007】更に、上記のように配線が長くなるので、
高速化の妨げにもなっている。
Furthermore, since the wiring becomes long as described above,
It is also an obstacle to speeding up.

【0008】本発明は、上記課題を解消し、高信頼性で
高集積化且つ高速化に対応できる複合電子部品を提供す
ることを目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide a composite electronic component which is highly reliable and can be integrated and speeded up.

【0009】[0009]

【課題を解決するための手段】本発明者は、上記目的を
達成すべく鋭意研究を重ねた結果、複数個の電子部品を
配線基板の両面に搭載するにおいて、配線を共有できる
電極をする電子部品同士を、配線基板を介して断面視同
じ向きとなるように配置するときは、配線を最短にでき
ることを見出した。
As a result of intensive studies to achieve the above object, the present inventor has found that when a plurality of electronic components are mounted on both sides of a wiring board, an electronic device having electrodes that can share wiring is used. It has been found that the wiring can be minimized when the parts are arranged so as to have the same direction in a sectional view through the wiring board.

【0010】即ち、本発明は、次の複合電子部品に係る
ものである。
That is, the present invention relates to the following composite electronic component.

【0011】素子形成面側を表面とする電子部品の複
数個を配線基板の両面に搭載してなる複合電子部品にお
いて、上記配線基板の両面で少なくとも一個の電子部品
同士を、それぞれの電子部品の表面と裏面もしくは裏面
と表面とで上記配線基板を挟持するように対向配置する
構造を有することを特徴とする複合電子部品。
In a composite electronic component in which a plurality of electronic components having the element formation surface as the surface are mounted on both sides of a wiring board, at least one electronic component on each side of the wiring board is A composite electronic component having a structure in which a front surface and a back surface or a back surface and a front surface are arranged so as to face each other so as to sandwich the wiring substrate.

【0012】配線基板に対向配置する電子部品が同一
もしくは類似の入力端子用又は出力端子用の電極配列を
備えることを特徴とする上記に記載の複合電子部品。
[0012] The composite electronic component as described above, wherein the electronic components arranged opposite to the wiring board have the same or similar electrode arrays for input terminals or output terminals.

【0013】配線基板に対向配置する電子部品が同一
もしくは類似の電源端子用又は接地端子用の電極配列を
備えることを特徴とする上記に記載の複合電子部品。
The composite electronic component as described above, wherein the electronic components arranged opposite to the wiring board have the same or similar electrode arrays for power terminals or ground terminals.

【0014】配線基板に対向配置する電子部品の一方
もしくは両方がベアチップ部品であることを特徴とする
上記〜のいずれかに記載の複合電子部品。
The composite electronic component according to any one of the above 1 to 3, wherein one or both of the electronic components arranged facing the wiring board are bare chip components.

【0015】配線基板に形成された配線と電子部品の
電極とが、配線基板に対向配置する電子部品の一方がワ
イヤ接続され、他方が対面接続されていることを特徴と
する上記〜のいずれかに記載の複合電子部品。
The wiring formed on the wiring board and the electrode of the electronic component are such that one of the electronic components facing the wiring substrate is wire-connected and the other is face-to-face connected. The composite electronic component described in.

【0016】配線基板に対向配置する電子部品同士の
電極が、上記配線基板に形成された配線を、上記配線基
板に設けられたスルーホールを通すことにより、上記配
線基板の一方の面側から共通にして導出される上記〜
のいずれかに記載の複合電子部品。
Electrodes of electronic parts arranged opposite to each other on the wiring board are made common from one surface side of the wiring board by passing the wiring formed on the wiring board through through holes provided on the wiring board. Derived above
The composite electronic component according to any one of 1.

【0017】[0017]

【作用】上記のような配置構造としたので、配線基板を
介して対向設置される電子部品同士は、その電極をも上
記配線基板に対して対向する位置にくることとなる。従
って、上記電子部品同士が例えば電源端子用、接地端子
用、入力端子用、出力端子用等の少なくとも何れかの電
極を、電子部品上において同一もしくは近傍する位置に
配列形成されている場合、上記電子部品同士の電極を配
線基板に対して略面対称となる位置に配置されることと
なり、上記電極同士を接続し引き出す配線の長さを最短
にできるのである。
With the arrangement structure as described above, the electronic components placed opposite to each other via the wiring board have their electrodes at positions facing the wiring board. Therefore, in the case where the electronic components are formed by arranging at least one of electrodes for power supply terminals, ground terminals, input terminals, output terminals, etc. at the same or near positions on the electronic components, The electrodes of the electronic components are arranged at positions substantially symmetrical with respect to the wiring board, and the length of the wiring connecting and connecting the electrodes can be minimized.

【0018】上記のように配線を最短にして配線基板の
両面における電子部品同士の電極を接続できるので、他
の配線と相互に干渉しない程度に密度的或いは距離的に
余裕をもたせてパターン形成でき、全体としての配線パ
ターンは極めて単純なパターンとし得ることとなる。
As described above, since the electrodes can be connected to each other on both sides of the wiring board by making the wiring as short as possible, it is possible to form a pattern with a sufficient density or distance so as not to interfere with other wiring. The wiring pattern as a whole can be a very simple pattern.

【0019】また、配線長さを短くできるので、複合電
子部品としての信頼性を向上し得、しかも高速化が図れ
ることとなる。更に、配線を短くできる分、配線の占有
面積を減らすことができるので、より集積度を向上し得
ることとなる。
Further, since the wiring length can be shortened, the reliability of the composite electronic component can be improved and the speed can be increased. Further, since the wiring can be shortened, the area occupied by the wiring can be reduced, so that the degree of integration can be further improved.

【0020】[0020]

【実施例】以下、実施例を示し、本発明の特徴とすると
ころをより詳細に説明する。
EXAMPLES Examples will be shown below to describe the features of the present invention in more detail.

【0021】図1に本発明の第1の実施例の概略断面図
を示す。図において、符号1は配線基板を、符号2,3
はベアチップIC(以下「IC」という)を示す。ここ
では上記IC2とIC3とは、同種のもので、素子形成
面側の表面に電極が形成されており、その電極配置パタ
ーンも同一で、この電極が形成された面を、以下IC
2,3の表面2’,3’という。上記配線基板1の両面
には、IC2及びIC3が上記配線基板1を狭持するよ
うに対向配置されている。上記IC2は、その表面2’
を上にして、上記配線基板1の上面1’に上記表面2’
に形成された電極が配線基板1上の配線4とワイヤボン
ディング法によりワイヤ5で接続されて配置され、上記
IC3はその表面3’を配線基板1の下面1”に、上記
表面3’に形成された電極が配線基板1上の配線6の接
続部と異方性導電樹脂層7を介して対面接続されてい
る。上記配線基板1の上面1’側の配線6は、配線基板
1に設けられたスルーホール8に配線を通すことにより
配線基板1の下面1’側の配線7と接続される。
FIG. 1 shows a schematic sectional view of the first embodiment of the present invention. In the figure, reference numeral 1 is a wiring board, and reference numerals 2 and 3
Indicates a bare chip IC (hereinafter referred to as “IC”). Here, the above IC2 and IC3 are of the same kind, and an electrode is formed on the surface on the element forming surface side, and the electrode arrangement pattern is also the same.
A few surfaces 2 ', 3'. IC2 and IC3 are arranged on both sides of the wiring board 1 so as to face each other so as to sandwich the wiring board 1. The IC2 has a surface 2 '
On the upper surface 1'of the wiring board 1 and the front surface 2 '
The electrodes formed on the wiring board 1 are connected to the wiring 4 on the wiring board 1 by wires 5 by a wire bonding method, and the IC 3 has its surface 3'formed on the lower surface 1 "of the wiring board 1 and on the surface 3 '. The formed electrodes are face-to-face connected to the connection portion of the wiring 6 on the wiring board 1 through the anisotropic conductive resin layer 7. The wiring 6 on the upper surface 1'side of the wiring board 1 is provided on the wiring board 1. By passing the wiring through the through hole 8 provided, the wiring 7 is connected to the wiring 7 on the lower surface 1 ′ side of the wiring board 1.

【0022】次に、図2及び図3に図1における配線基
板1の両面でのIC2,3の配置状態を説明する拡大斜
視図を示し、更に第1の実施例について詳述する。図2
に示すように、配線基板1の下面1”には、IC3の各
電極3a〜3fに対応するように配線6a〜6fが配設
されている。各配線6a〜6fは、配線基板1の端縁部
から対応するIC3の各電極3a〜3fとの接続部に向
かって直線的に形成されており、その途中には配線基板
1の上面1’の配線4a〜4f(図3参照)と接続でき
るようにスルーホール8a〜8fの開口部が配置されて
いる。
Next, FIGS. 2 and 3 show enlarged perspective views for explaining the arrangement state of the ICs 2 and 3 on both surfaces of the wiring board 1 in FIG. 1, and the first embodiment will be described in detail. Figure 2
As shown in FIG. 3, wirings 6a to 6f are arranged on the lower surface 1 ″ of the wiring board 1 so as to correspond to the respective electrodes 3a to 3f of the IC 3. The wirings 6a to 6f are the ends of the wiring board 1. It is linearly formed from the edge portion toward the connection portion with the corresponding electrodes 3a to 3f of the IC 3, and is connected to the wirings 4a to 4f (see FIG. 3) on the upper surface 1 ′ of the wiring board 1 in the middle thereof. The openings of the through holes 8a to 8f are arranged so that they can be formed.

【0023】上記IC3は、配線基板1の下面1”の所
定位置に塗布又は印刷等により設けられた異方性導電樹
脂層7を介して各電極3a〜3fがそれぞれ配線6a〜
6fと電気的に接続するように対面接続配置される。
In the IC 3, the electrodes 3a to 3f are respectively connected to the wirings 6a to 3f via the anisotropic conductive resin layer 7 provided by coating or printing at a predetermined position on the lower surface 1 "of the wiring substrate 1.
Face-to-face connection is arranged so as to be electrically connected to 6f.

【0024】次に、図3に示すように、上記配線基板1
の上面1’にIC2を、上記配線基板1の下面1”のI
C3と面対称となるように、その電極2a〜2fが形成
された面を上にして搭載し、これら電極2a〜2fはそ
れぞれ対応する配線基板1の上面1’の各スルーホール
8a〜8fの開口部から直線的に延びる配線4a〜4f
の端部にワイヤボンディングによりワイヤ接続される。
Next, as shown in FIG. 3, the wiring board 1 is formed.
IC2 on the upper surface 1'of the wiring board 1 and I on the lower surface 1 "of the wiring board 1.
The electrodes 2a to 2f are mounted with the surfaces on which the electrodes 2a to 2f are formed facing upward so as to be plane-symmetrical to C3, and these electrodes 2a to 2f are respectively formed in the through holes 8a to 8f of the corresponding upper surface 1'of the wiring board 1. Wirings 4a to 4f linearly extending from the opening
Is connected to the end of the wire by wire bonding.

【0025】このようにして配線基板1の両面にIC2
及びIC3を搭載したので、例えばIC2の電極2aは
配線4a及びスルーホール8aを通じて配線6aと接続
され、配線基板1の下面1”よりIC3の電極3aと共
通の配線として取り出されることとなる。こうしてIC
2の各電極2a〜2fは、それぞれIC3の電極3a〜
3fと容易に配線を共有し得るのである。
In this way, the ICs 2 are formed on both sides of the wiring board 1.
Since the IC 2 and the IC 3 are mounted, for example, the electrode 2a of the IC 2 is connected to the wiring 6a through the wiring 4a and the through hole 8a and is taken out from the lower surface 1 ″ of the wiring board 1 as the wiring common to the electrode 3a of the IC 3. IC
The electrodes 2a to 2f of No. 2 are the electrodes 3a to 2f of the IC 3, respectively.
The wiring can be easily shared with 3f.

【0026】斯くして得られる配線基板は、その配線を
外部端子と接続することで複合電子部品とし得る。ま
た、例えば図4に示すように、複数個のICを電源端子
Vcc、接地端子GND及びI/O端子L1,L2を同
一(共有)にして回路配線する場合、上記のようにIC
を搭載した配線基板の複数枚を、例えば図5に示すよう
に、複数の段部を有する外部端子9を用いて多層に配置
すればよい。更に、図6に示すように、同一配線基板に
ICを第1の実施例と同様にして対向配置して設けて外
部端子10と接続することもできる。このようにすれ
ば、従来より高集積且つ薄くして複合電子部品を得るこ
とができる。但し、上記図5及び図6におけるIC3の
各電極3a〜3fは、バンプを用いたフェイスダウン方
式で配線基板1の配線6a〜6fと対面接続したものを
図示した。
The wiring board thus obtained can be made into a composite electronic component by connecting the wiring to external terminals. Further, for example, as shown in FIG. 4, when a plurality of ICs are circuit-wired with the power supply terminal Vcc, the ground terminal GND, and the I / O terminals L1 and L2 being the same (shared), as described above,
A plurality of wiring boards on which is mounted may be arranged in multiple layers using external terminals 9 having a plurality of stepped portions, as shown in FIG. 5, for example. Further, as shown in FIG. 6, it is also possible to connect the ICs to the external terminals 10 by disposing the ICs on the same wiring board so as to face each other in the same manner as in the first embodiment. By doing so, it is possible to obtain a composite electronic component with higher integration and thinner than before. However, each of the electrodes 3a to 3f of the IC 3 in FIGS. 5 and 6 is shown as being face-to-face connected with the wirings 6a to 6f of the wiring board 1 by a face-down method using bumps.

【0027】上記第1の実施例では、配線基板1の上下
面の配線をスルーホール8を用いて一方面から取り出し
たが、図7に示すように、配線基板1の両面の配線
4’,6’を形成し、図8に示すように、クリップ状の
接続端を有する外部端子11を用いて複合電子部品を得
れば、スルーホールを用いなくても信号を共有すること
ができ、このようにすれば更に簡単に配線基板を形成す
ることができる。
In the first embodiment, the wirings on the upper and lower surfaces of the wiring board 1 are taken out from one side by using the through holes 8. However, as shown in FIG. If a composite electronic component is obtained by forming 6 ′ and using an external terminal 11 having a clip-shaped connecting end as shown in FIG. 8, signals can be shared without using a through hole. By doing so, the wiring board can be formed more easily.

【0028】次に、本発明の第2の実施例を図9により
説明する。本実施例は、絶縁基板1の両面に同種のモー
ルドパッケージIC12及び13を搭載するものであ
る。上記モールドパッケージIC12のアウターリード
12aは、通常の方向に向け屈曲されて配線基板1の配
線4”に半田付け等により接続され、上記モールドパッ
ケージIC13のアウターリード13aは、上記アウタ
ーリード12aと反対の方向に屈曲させて配線6”と接
続される。このようにすれば、モールドパッケージIC
12と13とは、本体を断面視同方向にして配線基板1
の両面に対向配置されることとなるので、信号を共有で
きるアウターリード同士を配線基板に対して面対称に配
置でき、上記第1の実施例におけるのと同様の配線パタ
ーンで搭載できるのである。
Next, a second embodiment of the present invention will be described with reference to FIG. In this embodiment, the same type of mold package ICs 12 and 13 are mounted on both surfaces of the insulating substrate 1. The outer lead 12a of the mold package IC12 is bent in a normal direction and connected to the wiring 4 "of the wiring board 1 by soldering or the like. The outer lead 13a of the mold package IC13 is opposite to the outer lead 12a. It is bent in the direction and connected to the wiring 6 ″. In this way, the mold package IC
12 and 13 are wiring boards 1 with the main body in the same direction in cross section.
Therefore, the outer leads that can share signals can be arranged symmetrically with respect to the wiring board, and can be mounted in the same wiring pattern as in the first embodiment.

【0029】また、本発明は、電子部品の両面に電極を
有するものであっても、片面の電極をフェースダウン方
式等により対面接続で、もう片面の電極をワイヤ接続で
それぞれ配線と接続し、電子部品同士が、配線基板の上
下面で対応する電極における接続を、対面接続とワイヤ
接続と逆にして用いれば適用可能で、上記実施例と同様
の効果を得ることができるものである。
Further, according to the present invention, even if the electronic component has electrodes on both sides, the electrodes on one side are connected face-to-face by a face-down method or the like, and the electrodes on the other side are connected to wiring by wire connection, respectively. The electronic components can be applied by connecting the corresponding electrodes on the upper and lower surfaces of the wiring board in reverse to the face-to-face connection and the wire connection, and it is possible to obtain the same effect as that of the above embodiment.

【0030】以上詳述したように、本発明は、例えばメ
モリーモジュール、ミラー回路等において、同一もしく
は類似の電子部品を複数個、各種端子を並列接続して搭
載する場合に特に有効である。
As described in detail above, the present invention is particularly effective when a plurality of identical or similar electronic components and various terminals are connected in parallel in a memory module, a mirror circuit, or the like.

【0031】[0031]

【発明の効果】本発明によれば、配線基板の両面に電子
部品を、配線を最短にして搭載できるので、配線を単純
なパターンとし得、従来のように複雑に配線パターンを
形成する必要がなく、配線基板を多層にして配線する必
要もなくなる。よって、配線が交差したり近接すること
による配線相互の干渉によるクロストーク等のノイズ発
生を低減できる等、高信頼性の複合電子部品を提供でき
る。
According to the present invention, since electronic parts can be mounted on both sides of a wiring board with the shortest wiring, the wiring can be a simple pattern, and it is necessary to form a complicated wiring pattern as in the conventional case. Also, there is no need to wire the wiring board in multiple layers. Therefore, it is possible to provide a highly reliable composite electronic component in which noise such as crosstalk due to mutual interference between wirings due to wirings crossing or approaching each other can be reduced.

【0032】また、従来に比し、配線の占める面積を削
減できるのでより高集積化が図れるとともに配線が短く
できるのでより高速化が図れる。
Further, as compared with the prior art, since the area occupied by the wiring can be reduced, higher integration can be achieved and the wiring can be shortened, so that higher speed can be achieved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を示す概略断面図であ
る。
FIG. 1 is a schematic sectional view showing a first embodiment of the present invention.

【図2】図1の配線基板の下面における電子部品を搭載
状態説明する拡大斜視図である。
FIG. 2 is an enlarged perspective view illustrating a mounted state of electronic components on a lower surface of the wiring board of FIG.

【図3】図1の配線基板の上面における電子部品の搭載
状態説明する拡大斜視図である。
FIG. 3 is an enlarged perspective view illustrating a mounting state of electronic components on the upper surface of the wiring board of FIG.

【図4】第1の実施例により得られる複合電子部品の回
路図の一例である。
FIG. 4 is an example of a circuit diagram of a composite electronic component obtained according to the first embodiment.

【図5】図4の回路図に従い回路配線された複合電子部
品の一構造例を示す概略断面図である。
5 is a schematic cross-sectional view showing one structural example of a composite electronic component circuit-wiring according to the circuit diagram of FIG.

【図6】図4の回路図に従い回路配線された複合電子部
品の他の構造例を示す概略断面図である。
6 is a schematic cross-sectional view showing another structural example of the composite electronic component circuit-wiring according to the circuit diagram of FIG.

【図7】第1の実施例における配線のパターンの他の例
を示す概略断面図である。
FIG. 7 is a schematic cross-sectional view showing another example of the wiring pattern in the first embodiment.

【図8】図7に示す配線パターンを用いたときの複合電
子部品の一構造例である。
FIG. 8 is a structural example of a composite electronic component when the wiring pattern shown in FIG. 7 is used.

【図9】本発明の第2の実施例を示す概略断面図であ
る。
FIG. 9 is a schematic cross-sectional view showing a second embodiment of the present invention.

【図10】従来のベアチップICを用いたときの実装構
造を示す概略断面図である。
FIG. 10 is a schematic cross-sectional view showing a mounting structure when a conventional bare chip IC is used.

【図11】従来のモールドパッケージICを用いたとき
の実装構造を示す概略断面図である。
FIG. 11 is a schematic sectional view showing a mounting structure when a conventional mold package IC is used.

【図12】図10におけるベアチップICの電極配置を
説明する要部斜視図である。
12 is a perspective view of a main part for explaining an electrode arrangement of the bare chip IC in FIG.

【図13】図10におけるベアチップICの電極配置を
説明する要部斜視図である。
13 is a perspective view of a main part for explaining an electrode arrangement of the bare chip IC in FIG.

【符号の説明】[Explanation of symbols]

1 配線基板 2,3 ベアチップIC 2a〜2f,3a〜3f 電極 4,4’,4”,6,6’、6” 配線 5 ワイヤ 7 異方性導電樹脂 8 スルーホール 9,10,11 外部端子 12,13 モールドパッケージIC 12a,13a アウターリード 1 Wiring board 2,3 Bare chip IC 2a-2f, 3a-3f Electrode 4,4 ', 4 ", 6,6', 6" Wiring 5 Wire 7 Anisotropic conductive resin 8 Through hole 9,10,11 External terminal 12,13 Mold package IC 12a, 13a Outer lead

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 素子形成面側を表面とする電子部品の複
数個を配線基板の両面に搭載してなる複合電子部品にお
いて、上記配線基板の両面で少なくとも一個の電子部品
同士を、それぞれの電子部品の表面と裏面もしくは裏面
と表面とで上記配線基板を挟持するように対向配置する
構造を有することを特徴とする複合電子部品。
1. A composite electronic component in which a plurality of electronic components each having an element formation surface as a surface are mounted on both sides of a wiring board, and at least one electronic component is provided on each side of the wiring board. A composite electronic component having a structure in which a front surface and a back surface of a component or a back surface and a front surface of the component are arranged to face each other so as to sandwich the wiring substrate.
【請求項2】 配線基板に対向配置する電子部品が同一
もしくは類似の入力端子用又は出力端子用の電極配列を
備えることを特徴とする請求項1に記載の複合電子部
品。
2. The composite electronic component according to claim 1, wherein the electronic components arranged opposite to the wiring board have the same or similar electrode arrays for input terminals or output terminals.
【請求項3】 配線基板に対向配置する電子部品が同一
もしくは類似の電源端子用又は接地端子用の電極配列を
備えることを特徴とする請求項1に記載の複合電子部
品。
3. The composite electronic component according to claim 1, wherein the electronic components arranged opposite to the wiring board have the same or similar electrode array for power terminals or ground terminals.
【請求項4】 配線基板に対向配置する電子部品の一方
もしくは両方がベアチップ部品であることを特徴とする
請求項1〜3のいずれかに記載の複合電子部品。
4. The composite electronic component according to claim 1, wherein one or both of the electronic components arranged facing the wiring board are bare chip components.
【請求項5】 配線基板に形成された配線と電子部品の
電極とが、配線基板に対向配置する電子部品の一方がワ
イヤ接続され、他方が対面接続されていることを特徴と
する請求項1〜4のいずれかに記載の複合電子部品。
5. The wiring formed on the wiring board and the electrode of the electronic component are such that one of the electronic components arranged facing the wiring substrate is wire-connected and the other is face-to-face connected. 5. The composite electronic component according to any one of to 4.
【請求項6】 配線基板に対向配置する電子部品同士の
電極が、上記配線基板に形成された配線を、上記配線基
板に設けられたスルーホールを通すことにより、上記配
線基板の一方の面側から共通にして導出される請求項1
〜5のいずれかに記載の複合電子部品。
6. The one surface side of the wiring board, wherein electrodes of electronic components arranged opposite to each other on the wiring board pass the wiring formed on the wiring board through through holes provided in the wiring board. Claim 1 commonly derived from
7. The composite electronic component according to any one of 5 to 5.
JP18506393A 1993-07-27 1993-07-27 Composite electronic part Pending JPH0745928A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18506393A JPH0745928A (en) 1993-07-27 1993-07-27 Composite electronic part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18506393A JPH0745928A (en) 1993-07-27 1993-07-27 Composite electronic part

Publications (1)

Publication Number Publication Date
JPH0745928A true JPH0745928A (en) 1995-02-14

Family

ID=16164163

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18506393A Pending JPH0745928A (en) 1993-07-27 1993-07-27 Composite electronic part

Country Status (1)

Country Link
JP (1) JPH0745928A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008010583A (en) * 2006-06-28 2008-01-17 Toshiba Corp Circuit module and electronic device
JP2009177040A (en) * 2008-01-28 2009-08-06 Fuji Electric Systems Co Ltd Wiring method of semiconductor switching element

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008010583A (en) * 2006-06-28 2008-01-17 Toshiba Corp Circuit module and electronic device
JP2009177040A (en) * 2008-01-28 2009-08-06 Fuji Electric Systems Co Ltd Wiring method of semiconductor switching element

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