JPH08236659A - Leadless chip carrier and printed board for mounting it - Google Patents

Abstract

PURPOSE: To obtain a leadless chip carrier in which the terminal electrodes can be ensured depending on the integration of a semiconductor device to be mounted without increasing the size of the leadless chip carrier body and a printed board for mounting the leadless chip carrier. CONSTITUTION: In the leadless chip carrier provided with a plurality of terminal electrodes 3 arranged at an interval on the end face 2 of a board, the board 1 constituting the leadless chip carrier is formed in multistage and a plurality of terminal electrodes 3 are formed on the end face 2 of each board.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a leadless chip carrier on which a semiconductor chip is mounted and a printed circuit board on which the leadless chip carrier is mounted.

[0002]

2. Description of the Related Art An example of a conventional leadless chip carrier will be described with reference to FIG.

A substrate 1 which constitutes a leadless chip carrier is formed of, for example, a printed wiring board, and a terminal electrode 3 is formed on a substrate end face 2 of this printed wiring board.
The terminal electrodes 3 are formed on the substrate end surface 2 of the substrate 1 forming the chip carrier at regular intervals, and plating through holes are formed in the peripheral edge of the substrate 1 and the plating through holes are cut in half. Formed. And
This leadless chip carrier is conductively connected to a mother board made of a printed wiring board by soldering the terminal electrodes 3.

Generally, this leadless chip carrier has a recess 15 for mounting a semiconductor chip in the center of the substrate 1.
Is formed, a semiconductor chip is mounted in the recess 15, the connection terminal 9 of the circuit pattern 5 formed on the substrate 1 and the mounted semiconductor chip are connected by a bonding wire, and the recess 15 is formed by an aluminum lid. It has been used by blocking or enclosing a sealing material.

When the leadless chip carrier is mounted on a mother board made of a printed wiring board and used, the terminal electrodes 3 are used to electrically connect to the mother board. However, since the number of the terminal electrodes 3 varies depending on the degree of integration of the semiconductor chips to be mounted, in order to improve the degree of integration of the semiconductor chips and increase the number of the terminal electrodes 3, this leadless chip carrier is used. It was necessary to increase the length of the side of the substrate 1 to be configured, and it was necessary to increase the size of the leadless chip carrier body.

[0006]

The present invention has been made in view of the above circumstances, and its object is to:
Provided are a leadless chip carrier capable of securing a terminal electrode according to the integration degree of a semiconductor device to be mounted without increasing the size of the leadless chip carrier body, and a printed board on which the leadless chip carrier is mounted. Especially.

[0007]

A leadless chip carrier according to claim 1 of the present invention is a leadless chip carrier in which a plurality of terminal electrodes 3 are formed on a substrate end face 2 at intervals. It is characterized in that the constituent substrates 1 are formed in multiple stages, and a plurality of terminal electrodes 3 are formed on each substrate end face 2.

Further, the printed board on which the leadless chip carrier according to claim 2 of the present invention is mounted has a recess 6 for mounting the leadless chip carrier according to claim 1, and the bottom surface 7 of the recess 6 is formed. It is characterized by having a connection pad 4 connected to the terminal electrode 3 of the leadless chip carrier.

[0009]

The leadless chip carrier according to claim 1 of the present invention is a leadless chip carrier in which a plurality of terminal electrodes are formed at intervals on the end face of the substrate, and the substrates forming the leadless chip carrier are formed in multiple stages. ,
Since a plurality of terminal electrodes are formed on the end faces of each substrate, the number of terminal electrodes for external connection is increased, and a semiconductor chip having a high degree of integration can be mounted.

Further, in a printed circuit board on which the leadless chip carrier according to claim 2 of the present invention is mounted, a concave portion is formed in the printed circuit board, and a connection pad is formed in two portions of the concave portion. By fitting a part of the leadless chip carrier described in 1 in the recess, the connection pad and the terminal electrode of the leadless chip carrier can be connected and the leadless chip carrier can be mounted on the printed board.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 (a) is a perspective view of the surface of a leadless chip carrier according to an embodiment of the present invention, and FIG. 1 (b) is a perspective view of the back surface.

As shown in FIG. 1, the leadless chip carrier according to the present invention is composed of a substrate 1 formed in a two-step rectangular shape.

This substrate 1 is composed of a first-stage substrate 1a and a second-stage substrate 1b, and the first-stage substrate 1a and the second-stage substrate 1b have their respective end faces 2 consisting of four sides. The terminal electrodes 3 are formed at regular intervals. The terminal electrode 3 is formed by forming a plurality of plated through holes on the outer end surface of the substrate 1 and cutting the plated through holes in half, and the circuit pattern 5 formed on the front surface or the back surface of the substrate 1. Connected with. Further, the circuit pattern 5 is formed in the via hole 1 penetrating the front and back surfaces of the substrate 1.
1 and is electrically connected to each circuit pattern 5 through the via hole 11.

The leadless chip carrier of this embodiment is
As shown in the figure, the first-stage substrate 1a is formed of a substrate having a smaller outer dimension than the second-stage substrate 1b, and the second-stage substrate 1b is formed.
A mounting portion 8 for mounting a semiconductor chip is formed therein. Around the mounting portion 8, a plurality of connection terminals 9 are formed which are connected to the terminals of the semiconductor chip by bonding wires when the semiconductor chip is mounted.

The connection terminal 9 is connected to the circuit pattern 5, and the via hole 11 is connected through the circuit pattern 5.
And the terminal electrode 3.

The substrate 1 constituting this leadless chip carrier is not particularly limited, but preferably a printed wiring board having circuit patterns on the front and back can be used.

In order to form the above leadless chip carrier, a conventional method for manufacturing a leadless chip carrier can be used. A leadless chip carrier having a laminated plate as a substrate and a first substrate 1a To form. First, a laminated plate is drilled and copper plated. Next, etching is performed according to the circuit pattern, and further,
Perform nickel plating and gold plating. Then, the obtained plated through holes are half cut. Similarly, the second substrate 1b
Also, the laminated plate is used as a substrate for drilling and copper plating. Next, etching is performed according to the circuit pattern, and nickel plating and gold plating are further performed. Then, here, the first-stage substrate 1a obtained previously is overlaid, molded, or integrated by an adhesive, the integrated substrate 1 is drilled, and formed by this drilling. Similarly, the holes are copper-plated, etched according to the circuit pattern, and then nickel-plated and gold-plated. Then, the plated through holes formed in the second-stage substrate 1b are cut in half.

FIG. 5 is a partially enlarged view of a printed board on which the leadless chip carrier of the present invention shown in FIG. 1 is mounted.

As shown in the drawing, the printed board 10 on which the leadless chip carrier according to the embodiment of the present invention is mounted is formed of a multilayer printed wiring board.

As the multilayer printed wiring board, a conventionally used multilayer printed wiring board can be used. In this multilayer printed wiring board, circuit patterns are formed on the front and back surfaces and inner layers.

The printed wiring board 10 of the present invention has a surface 1
The recess 6 is formed in 0a. The concave portion 6 is formed by performing a spot facing process on the surface 10a of the printed circuit board 10 and is formed so that the leadless chip carrier having the multi-stepped shape is fitted therein.

Further, the circuit pattern of the inner layer is exposed on the bottom surface 7 of the recess 6, and the connection pad 4 is formed by this circuit pattern.

This connection pad 4 is intended to connect with a plurality of terminal electrodes 3 formed on the end face of the leadless chip carrier when the leadless chip carrier is fitted, and the substrate 1a of the leadless chip carrier. It is formed at a position facing the terminal electrode 3 formed on the.

Further, the connection pad 4 is also formed on the surface 10a, so that the connection with the terminal electrode 3 formed on the substrate 1b of the leadless chip carrier can be achieved.

FIG. 2 is a sectional view of a semiconductor chip mounted on the leadless chip carrier shown in FIG. 1 and mounted on the printed board shown in FIG.

As shown in the drawing, a semiconductor chip 12 is mounted on the mounting portion 8 of the leadless chip carrier, and the semiconductor chip 12 and the connection terminal 9 are connected by a bonding wire 13. Further, the semiconductor chip 12 and the bonding wires 13 are covered with the sealing material 16.

In the leadless chip carrier, the substrate 1a, which is a part of the substrate 1 forming the leadless chip carrier body, is fitted in the recess 6 of the printed circuit board 10.

As shown in the figure, the leadless chip carrier mounted on the printed circuit board 10 has terminal electrodes 3, connection pads 4 formed on the surface 10 a of the printed circuit board 10 and connections formed on the bottom surface 7 of the recess 6. It is connected to the pad 4 by a solder fillet 14 for fixing and electrical conduction.

Therefore, the connection pad 4 of the recess 6 is connected to the via hole 11 via the terminal electrode 3 of the substrate 1a and further connected to the semiconductor chip 12 mounted on the substrate 1b.

FIG. 3A is a perspective view of the surface of a leadless chip carrier according to another embodiment of the present invention, and FIG. 3B is a perspective view of the back surface. FIG. 4 is a sectional view of the leadless chip carrier mounted on a printed circuit board.

This leadless chip carrier has the same structure as the leadless chip carrier shown in FIG. 1 or FIG. 2, and as shown in the figure, the mounting portion 8 for mounting the semiconductor chip is formed in a step shape. It is formed on the small substrate 1a side of the substrate 1.

Since the mounting portion 8 on which the semiconductor chip is mounted is different, the path connected from the terminal electrode 4 to the connection terminal 9 via the circuit pattern 5 is different.

Further, as shown in FIG. 4, the printed circuit board on which the leadless chip carrier of this embodiment is mounted is different from the printed circuit board of FIG. 2 in that the recess 6 formed in the printed circuit board 1 forms the leadless chip carrier. Semiconductor chip 13 mounted on the leadless chip carrier when mounted
Are formed in a stepped shape to protect the. Therefore, the concave portion 6 has a bottom portion 7 having the connection pad 4 formed therein, and the bottom portion 7 is further formed with a concave portion 6a having a bottom portion 7a.

When the leadless chip carrier is mounted on the recess 6a, the semiconductor chip 12 can be easily sealed by injecting the sealing material 16 into the recess 6a.

As described above, the substrate 1 which constitutes the leadless chip carrier of the present invention is formed in a multi-step form, and a plurality of terminal electrodes are formed on the substrate end face of the substrate forming each step. The number of external terminal electrodes can be increased without increasing the size of the chip carrier. Further, the printed board on which the leadless chip carrier of the present invention is mounted is formed with a recess into which the leadless chip carrier is fitted, and a connection pad is formed which is connected to the terminal electrode of the leadless chip carrier fitted into the recess. Therefore, the leadless chip carrier can be surely connected.

The leadless chip carrier of the present invention is not limited to the one shown in FIGS. 1 to 4, but the mounting portion for mounting the semiconductor chip has a concave shape, and the leadless chip carrier is a board fitted to the printed board. Some include solder balls that can be formed on the surface and connected to the connection pads on the printed circuit board.

[0038]

As described above, according to the leadless chip carrier of the present invention and the printed circuit board on which the leadless chip carrier is mounted, the number of external input / output terminal electrodes can be significantly improved. Therefore, the number of terminals can be increased according to the electronic components to be mounted, and the degree of integration can be improved. Furthermore, by mounting the leadless chip carrier according to the present invention on a printed circuit board, the leadless chip carrier mounted on the surface of the printed circuit board can be mounted without increasing the occupied area. By designing the printed circuit board and the printed circuit board at the same time, high density and small size can be achieved.

[Brief description of drawings]

FIG. 1A is a perspective view of a leadless chip carrier according to an embodiment of the present invention. (B) It is a perspective view of the back surface of the leadless chip carrier.

FIG. 2 is a cross-sectional view of the leadless chip carrier of FIG. 1 mounted on a printed circuit board.

FIG. 3A is a perspective view of a leadless chip carrier according to another embodiment of the present invention. (B) It is a perspective view of the back surface of the leadless chip carrier.

FIG. 4 is a cross-sectional view of the leadless chip carrier of FIG. 1 mounted on a printed circuit board.

FIG. 5 is a partially enlarged view of a printed circuit board on which the leadless chip carrier of the present invention is mounted.

FIG. 6 is a perspective view of a conventional leadless chip carrier.

[Explanation of symbols]

 1 substrate 2 substrate end face 3 terminal electrode 4 connection pad 5 circuit pattern 6 recess 7 bottom 9 connection terminal 11 via hole

Claims (2)

[Claims] 1. A plurality of terminal electrodes (3) are provided on a substrate end surface (2).
In a leadless chip carrier formed at intervals with each other, substrates (1) constituting the leadless chip carrier are formed in multiple stages, and a plurality of terminal electrodes (3) are formed on each substrate end face (2). Leadless chip carrier characterized by the following. 2. A recess (6) for mounting the leadless chip carrier according to claim 1 is formed, and a bottom surface (7) of the recess (6) is connected to a terminal electrode (3) of the leadless chip carrier. A printed circuit board for mounting a leadless chip carrier, which has a connection pad (4).