JP2739123B2 - Manufacturing method of electronic component mounting board - Google Patents

Manufacturing method of electronic component mounting board

Info

Publication number
JP2739123B2
JP2739123B2 JP5654291A JP5654291A JP2739123B2 JP 2739123 B2 JP2739123 B2 JP 2739123B2 JP 5654291 A JP5654291 A JP 5654291A JP 5654291 A JP5654291 A JP 5654291A JP 2739123 B2 JP2739123 B2 JP 2739123B2
Authority
JP
Japan
Prior art keywords
electronic component
component mounting
manufacturing
primary
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5654291A
Other languages
Japanese (ja)
Other versions
JPH04291788A (en
Inventor
輝代隆 塚田
洋吾 川崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP5654291A priority Critical patent/JP2739123B2/en
Publication of JPH04291788A publication Critical patent/JPH04291788A/en
Application granted granted Critical
Publication of JP2739123B2 publication Critical patent/JP2739123B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、電子部品搭載用基板の
製造方法に関し、特に、基材上に形成された電子部品搭
載用凹部に電子部品を実装するための互いに電気的に独
立した2以上の電極を有する電子部品搭載用基板の製造
方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electronic component mounting substrate, and more particularly to a method for mounting electronic components in electronic component mounting recesses formed on a substrate. The present invention relates to a method for manufacturing an electronic component mounting substrate having the above electrodes.

【0002】[0002]

【従来の技術】半導体チップ等の電子部品を外部と電気
的に接続するために使用される電子部品搭載用基板は、
従来より種々のものが案出されてきている。
2. Description of the Related Art Electronic component mounting substrates used for electrically connecting electronic components such as semiconductor chips to the outside are:
Conventionally, various things have been devised.

【0003】この種の電子部品搭載用基板に電子部品を
実装する方法としては、従来より様々な形式のものがあ
るが、昨今では高密度実装という要求から、図4に示す
ような、小型電子部品の上に他の大型電子部品を実装す
るという積層形式が採られている。
There have been various types of methods for mounting electronic components on this type of electronic component mounting board. Conventionally, however, due to the demand for high-density mounting, small electronic devices as shown in FIG. 2. Description of the Related Art A laminated type in which another large electronic component is mounted on a component has been adopted.

【0004】ところが、この積層形式による電子部品の
実装は、面積的な点においては高密度にすることができ
るが、厚さの点で不利であり、また、例えばQFPのよ
うなフラットパッケージICやTSOPのような電子部
品の場合には、その下に他の電子部品(例えば、コンデ
ンサ等のチップ部品)を実装できないという問題があっ
た。
[0004] However, the mounting of electronic components by the stacking method can achieve high density in terms of area, but is disadvantageous in terms of thickness. For example, a flat package IC such as QFP or the like can be used. In the case of an electronic component such as TSOP, another electronic component (for example, a chip component such as a capacitor) cannot be mounted thereunder.

【0005】そこで、近年では、図5に示すように、基
材10上に電子部品を収納するための電子部品搭載用凹
部20を形成し、この凹部20内に電子部品と電気的に
接続するための2以上の電極23を形成した電子部品搭
載用基板100が提案されている。
In recent years, therefore, as shown in FIG. 5, an electronic component mounting recess 20 for accommodating an electronic component is formed on the base material 10 and electrically connected to the electronic component in the recess 20. Electronic component mounting substrate 100 on which two or more electrodes 23 are formed.

【0006】ところが、このような電子部品搭載用凹部
20に2以上の電極23を有する電子部品搭載用基板1
00を製造するには、エッチング等によって2極以上の
電極23を形成する必要があるが、これらの電極23を
形成する際のレジストの密着性やその露光精度の問題か
ら、高密度で信頼性のある電子部品搭載用基板100を
製造するのが困難であった。
However, the electronic component mounting substrate 1 having two or more electrodes 23 in such an electronic component mounting recess 20.
In order to manufacture the electrode 00, it is necessary to form two or more electrodes 23 by etching or the like. It is difficult to manufacture the electronic component mounting board 100 having a problem.

【0007】そこで、次のような方法が考えられた。す
なわち、図6(a)〜(d)に示すように、基材10に
座ぐり加工によって電子部品搭載用凹部20を形成し、
その後、その側面及び底面に銅メッキ等の導体をメッキ
22してベタパターン23aを形成し、最後にこのベタ
パターン23aをエンドミルによって2極以上に分断し
て、2極以上の電極23を形成する方法である。
Therefore, the following method has been considered. That is, as shown in FIGS. 6A to 6D, the electronic component mounting concave portion 20 is formed in the base material 10 by spot facing.
Thereafter, a conductor such as copper plating is plated 22 on the side and bottom surfaces to form a solid pattern 23a, and finally the solid pattern 23a is divided into two or more poles by an end mill to form two or more pole electrodes 23. Is the way.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、このよ
うにベタパターンをエンドミルによって2極以上に分断
するという従来の方法は、メッキのバリや引き剥れが生
じ易いため、製品の信頼性に大きく影響し、また、エン
ドミルのバイト径は、最小でも0.6φmm程度である
ため、小さな電極を形成することができず、小型チップ
部品等を搭載するための電子部品搭載用基板を製造でき
ないという問題があった。
However, the conventional method of dividing a solid pattern into two or more poles by an end mill as described above tends to cause burrs and peeling of plating, which greatly affects the reliability of products. In addition, since the end mill has a cutting tool diameter of at least about 0.6 mm, a small electrode cannot be formed, and a substrate for mounting an electronic component for mounting a small chip component or the like cannot be manufactured. there were.

【0009】そこで案出されたのが本発明であって、そ
の目的とするところは、信頼性が高く、かつ、小型チッ
プ部品をも搭載することが可能な電子部品搭載用基板を
容易に製造することができる製造方法を提供することに
ある。
The present invention was devised in view of the above circumstances, and an object of the present invention is to easily manufacture an electronic component mounting substrate which is highly reliable and can mount a small chip component. It is an object of the present invention to provide a manufacturing method capable of performing the above.

【0010】[0010]

【課題を解決するための手段】以上の様な課題を解決す
るために本発明が採った手段は、実施例に対応する図面
に使用した符号を付して説明すると、「基材10上に形
成された電子部品搭載用凹部20に電子部品を実装する
ための互いに電気的に独立した2以上の電極23を有す
る電子部品搭載用基板100を、次の各工程を含んで製
造することを特徴とする電子部品搭載用基板100の製
造方法; (イ)基材10上に互いに独立した一次凹部21を少な
くとも前記電極23の数だけ形成する工程; (ロ)前記各一次凹部21の側面及び底面にメッキ22
を施す工程; (ハ)互いに隣接する前記一次凹部21の間の基材10
を前記側面のメッキ22と共に除去する工程」をその要
旨とするものである。
Means adopted by the present invention to solve the above-mentioned problems will be described with reference to the reference numerals used in the drawings corresponding to the embodiments. The electronic component mounting substrate 100 having two or more electrically independent electrodes 23 for mounting the electronic component in the formed electronic component mounting concave portion 20 is manufactured including the following steps. (A) a step of forming at least the number of the independent primary recesses 21 on the base material 10 by the number of the electrodes 23; and (b) a side surface and a bottom surface of each of the primary recesses 21. Plating 22
(C) the base material 10 between the adjacent primary recesses 21
Of removing together with the side surface plating 22 ".

【0011】つまり、この電子部品搭載用基板100の
製造方法は、電子部品搭載用凹部20に2以上の電極2
3を形成する際に、先ず、基材10上に座ぐり加工等に
よって搭載すべき電子部品の接続端子数に応じた数の一
次凹部21を互いに独立した状態で形成し(工程
(イ))、次いで、この一次凹部21の側面及び底面に
銅メッキ22等の導体メッキ22によるベタパターン2
3aを形成して電極化し(工程(ロ))、その後、隣接
する一次凹部21の間に残された基材10を、それらの
一次凹部21の側面に施されたメッキ22と共にエンド
ミルによる座ぐり加工等により除去することによって
(工程(ハ))、互いに独立していた一次凹部21を一
体化して電子部品搭載用凹部20を形成すると共に、こ
の電子部品搭載用凹部20に2以上の電極23を形成す
る工程を含むことを特徴とするものである。
In other words, the method of manufacturing the electronic component mounting substrate 100 includes the steps of:
When forming 3, first, the number of primary recesses 21 corresponding to the number of connection terminals of electronic components to be mounted on the base material 10 is formed in a state independent of each other by a counterbore process or the like (step (a)). Then, a solid pattern 2 formed by conductor plating 22 such as copper plating 22 is formed on the side and bottom surfaces of the primary recess 21.
3a is formed and turned into an electrode (step (b)), and then the base material 10 left between the adjacent primary concave portions 21 is spotted by an end mill together with the plating 22 applied to the side surfaces of the primary concave portions 21. By removing by processing or the like (step (c)), the primary concave portions 21 which are independent from each other are integrated to form the electronic component mounting concave portion 20 and the two or more electrodes 23 are formed in the electronic component mounting concave portion 20. Is formed.

【0012】なお、工程(ハ)において、一次凹部21
の間の基材10を除去する際に、その座ぐり加工の深さ
は、一次凹部21の底面に施されたメッキ22を剥さな
いようにするために、その底面より0.05〜0.1m
m程浅く行うのが望ましい。
In the step (c), the primary recess 21
When removing the base material 10 between the primary recesses 21, the depth of the counterbore processing is 0.05 to 0 mm from the bottom surface of the primary recess 21 in order to prevent the plating 22 applied on the bottom surface from being peeled off. .1m
It is desirable that the depth be as small as about m.

【0013】また、この工程において、座ぐり加工を行
うエンドミルのバイト径は、メッキ22のかえりを少な
くすると共に絶縁を充分なものとするために、隣接する
一次凹部21の間の距離より、0.5〜1.0mm程大
きい径のものを使用するのが望ましい。
In this step, the diameter of the end mill for performing the counterbore processing is set to be smaller than the distance between the adjacent primary recesses 21 in order to reduce the burrs of the plating 22 and to ensure sufficient insulation. It is desirable to use one having a diameter as large as about 0.5 to 1.0 mm.

【0014】[0014]

【発明の作用】上記のような手段を採ることにより、本
発明に係る製造方法は、次のように作用する。即ち、工
程(イ)及び(ロ)において、予め互いに独立した形
で、一次凹部21内に電極23を形成しておくため、他
の電極23との絶縁性が充分に行われる。
By adopting the means as described above, the manufacturing method according to the present invention operates as follows. That is, in the steps (a) and (b), the electrode 23 is formed in the primary recess 21 in advance in a manner independent of each other, so that the insulation with the other electrodes 23 is sufficiently performed.

【0015】また、工程(ハ)においては、座ぐり加工
する際に、一次凹部21の側面に施されたメッキ22の
バリは、隣りの一次凹部21側へ逃げることなく、その
一次凹部21内へ逃げ込むため、この製造方法によって
形成された各電極23の絶縁性が確実に確保される。ま
た、この工程により、側面のメッキ22のバリは、この
方法によって形成された電子部品搭載用凹部20と一次
凹部21とのギャップ内に納まって凸状となるため、電
子部品の実装を障げることがない。さらに、この工程に
おいて、一次凹部21の底面に施されたメッキ22の剥
れは、一次凹部21の長穴形状に沿って剥れるため、電
極23が欠けたり、ショートしたりすることがない。
In the step (c), the burrs of the plating 22 applied to the side surface of the primary recess 21 do not escape to the adjacent primary recess 21 side when the spot facing is performed. In this case, the insulation of each electrode 23 formed by this manufacturing method is reliably ensured. Also, by this step, the burrs of the plating 22 on the side face are convex within the gap between the electronic component mounting concave portion 20 and the primary concave portion 21 formed by this method, which hinders mounting of the electronic component. Never. Further, in this step, the plating 22 applied to the bottom surface of the primary recess 21 is peeled off along the elongated hole shape of the primary recess 21, so that the electrode 23 is not chipped or short-circuited.

【0016】さらに、一次凹部21を極小に形成するこ
とによって極めて小さな電極23をも容易に形成するこ
とができるため、小型チップ部品を搭載できる電子部品
搭載用基板100を容易に製造することが可能となる。
Further, since the very small electrode 23 can be easily formed by forming the primary concave portion 21 to a minimum, the electronic component mounting substrate 100 on which a small chip component can be mounted can be easily manufactured. Becomes

【0017】[0017]

【実施例】次に、本発明に係る電子部品搭載用基板10
0の製造方法の一実施例について、図面を参照しつつ工
程順に説明する。
Next, an electronic component mounting substrate 10 according to the present invention will be described.
An example of the manufacturing method of No. 0 will be described in the order of steps with reference to the drawings.

【0018】図1及び図2には、電子部品搭載用凹部2
0に2つの電極23を有する電子部品搭載用基板100
を製造する方法が示してある。
FIGS. 1 and 2 show an electronic component mounting recess 2.
Electronic component mounting substrate 100 having two electrodes 23 at zero
Is shown.

【0019】先ず、図1(a)及び図2(a)に示すよ
うに、2.0φmmのエンドミルにより、基材10に深
さ1.1mm、長さ3mmの長穴状の一次凹部21を1
mmの間隔をおいて2箇所形成すると共に、その基材1
0上に必要な導体回路30を形成する。
First, as shown in FIGS. 1 (a) and 2 (a), an elongated primary recess 21 having a depth of 1.1 mm and a length of 3 mm is formed in a base material 10 by an end mill of 2.0 mm. 1
mm at two places with an interval of
The necessary conductor circuit 30 is formed on the zero.

【0020】次いで、図1(b)及び図2(b)に示す
ように、この一次凹部21の側面及び底面並びに導体回
路30の表面に、厚さ15μmの銅メッキ22を施す。
Next, as shown in FIGS. 1 (b) and 2 (b), a 15 μm thick copper plating 22 is applied to the side and bottom surfaces of the primary recess 21 and the surface of the conductor circuit 30.

【0021】最後に、図1(c)及び図2(c)に示す
ように、両一次凹部21の間に残された基材10を、こ
れら両一次凹部21の側面に施された内方の銅メッキ2
2と共に、2.0φmmのエンドミルによる深さ1.0
5mmの座ぐり加工により除去し、互いに独立していた
2つの一次凹部21を一体化して電子部品搭載用凹部2
0を形成すると共に、この電子部品搭載用凹部20に2
つの電極23を形成する。
Finally, as shown in FIGS. 1 (c) and 2 (c), the base material 10 left between the two primary concave portions 21 is covered with the inner side provided on the side surfaces of the two primary concave portions 21. Copper plating 2
2 and a depth of 1.0 by a 2.0 mm end mill.
The two primary recesses 21 which were removed by counterbore processing of 5 mm and were independent from each other were integrated to form the electronic component mounting recess 2.
0, and 2 in this electronic component mounting concave portion 20.
One electrode 23 is formed.

【0022】このように製造された電子部品搭載用基板
100は、図1(d)及び図2(d)に示すように、一
次凹部21の側面に残された銅メッキ22により電子部
品を実装した際の半田付が強固に行われ、また、電子部
品は、電子部品搭載用凹部20に収納されるため、その
位置合わせが容易であると共に、いわゆるツームストー
ン現象が生じにくくなるのである。
As shown in FIGS. 1D and 2D, the electronic component mounting board 100 manufactured as described above is mounted with the electronic component by the copper plating 22 left on the side surface of the primary concave portion 21. In this case, the soldering is performed firmly, and the electronic component is stored in the electronic component mounting concave portion 20, so that the alignment is easy and the so-called tombstone phenomenon is less likely to occur.

【0023】なお、本発明は、電子部品搭載用凹部20
に2つ以上の電極23を形成する場合にも容易に適用す
ることができ、例えば、3つの電極23を形成する場合
には、図3(a)及び(b)に示すように、3つの一次
凹部21を予め形成し、これに前述と同様のメッキ22
を施し、そして各一次凹部21の基材10を前述と同様
の座ぐり加工により除去することによって、容易に製造
することができるのである。
It should be noted that the present invention is directed to the electronic component mounting recess 20.
This can be easily applied to the case where two or more electrodes 23 are formed. For example, when three electrodes 23 are formed, as shown in FIGS. A primary recess 21 is formed in advance, and a plating 22
, And the base material 10 of each primary recess 21 is removed by spot facing in the same manner as described above, thereby making it easy to manufacture.

【0024】[0024]

【発明の効果】以上、詳述したように、本発明に係る電
子部品搭載用基板の製造方法は、「基材上に形成された
電子部品搭載用凹部に電子部品を実装するための互いに
電気的に独立した2以上の電極を有する電子部品搭載用
基板を、次の各工程を含んで製造することを特徴とする
電子部品搭載用基板の製造方法; (イ)基材上に互いに独立した一次凹部を少なくとも前
記電極の数だけ形成する工程; (ロ)前記各一次凹部の側面及び底面にメッキを施す工
程; (ハ)互いに隣接する前記一次凹部の間の基材を前記側
面のメッキと共に除去する工程」をその構成上の特徴と
している。
As described above in detail, the method for manufacturing an electronic component mounting board according to the present invention is described as follows. A method for manufacturing an electronic component mounting substrate, comprising: manufacturing an electronic component mounting substrate having two or more electrically independent electrodes including the following steps; (B) plating the side and bottom surfaces of each of the primary recesses; and (c) forming a base material between the adjacent primary recesses together with the plating of the side surfaces. The "removing step" is a feature of the configuration.

【0025】従って、この製造方法によれば、各電極の
絶縁性が確実に確保されると共に、電極が欠けたり、シ
ョートしたりすることがないため、薄くてかつ高密度実
装が可能な信頼性の高い電子部品搭載用基板を容易に製
造することができる。
Therefore, according to this manufacturing method, the insulation of each electrode is reliably ensured, and the electrodes are not chipped or short-circuited. Electronic component mounting substrate with high reliability can be easily manufactured.

【0026】また、一次凹部を極小に形成することによ
って、極めて小さな電極をも容易に形成することができ
るため、小型チップ部品の搭載が可能な電子部品搭載用
基板を容易に製造することができる。
Further, by forming the primary concave portion to be extremely small, an extremely small electrode can be easily formed, so that an electronic component mounting substrate on which a small chip component can be mounted can be easily manufactured. .

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る製造方法の一実施例を工程順に示
す各平面図である。
FIG. 1 is a plan view showing one embodiment of a manufacturing method according to the present invention in the order of steps.

【図2】図1に示した製造方法の各横断面図である。FIG. 2 is a cross-sectional view of each of the manufacturing methods shown in FIG.

【図3】本発明に係る製造方法の別の実施例を部分的に
示す各平面図である。
FIG. 3 is a plan view partially showing another embodiment of the manufacturing method according to the present invention.

【図4】従来の電子部品の実装形式を示す断面図であ
る。
FIG. 4 is a cross-sectional view showing a mounting format of a conventional electronic component.

【図5】電子部品搭載用凹部に2以上の電極を有する電
子部品搭載用基板の一例を示す断面図である。
FIG. 5 is a cross-sectional view illustrating an example of an electronic component mounting board having two or more electrodes in an electronic component mounting recess.

【図6】図5に示した電子部品搭載用基板を製造する従
来の方法を工程順に示す各断面図である。
6 is a cross-sectional view showing a conventional method for manufacturing the electronic component mounting board shown in FIG. 5 in the order of steps.

【符号の説明】[Explanation of symbols]

100 電子部品搭載用基板 10 基材 20 電子部品搭載用凹部 21 一次凹部 22 メッキ 23 電極 23a ベタパターン 30 導体回路 以 上 REFERENCE SIGNS LIST 100 substrate for mounting electronic component 10 base material 20 concave portion for mounting electronic component 21 primary concave portion 22 plating 23 electrode 23a solid pattern 30 conductive circuit

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 基材上に形成された電子部品搭載用凹部
に電子部品を実装するための互いに電気的に独立した2
以上の電極を有する電子部品搭載用基板を、次の各工程
を含んで製造することを特徴とする電子部品搭載用基板
の製造方法; (イ)基材上に互いに独立した一次凹部を少なくとも前
記電極の数だけ形成する工程; (ロ)前記各一次凹部の側面及び底面にメッキを施す工
程; (ハ)互いに隣接する前記一次凹部の間の基材を前記側
面のメッキと共に除去する工程。
An electronic component mounting device for mounting an electronic component in an electronic component mounting recess formed on a substrate.
A method for manufacturing an electronic component mounting substrate, comprising: manufacturing an electronic component mounting substrate having the above-described electrodes, including the following steps: (a) forming at least primary recesses independent from each other on a base material; (B) plating the side and bottom surfaces of each of the primary recesses; (c) removing the base material between the adjacent primary recesses together with the plating on the side surfaces.
JP5654291A 1991-03-20 1991-03-20 Manufacturing method of electronic component mounting board Expired - Fee Related JP2739123B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5654291A JP2739123B2 (en) 1991-03-20 1991-03-20 Manufacturing method of electronic component mounting board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5654291A JP2739123B2 (en) 1991-03-20 1991-03-20 Manufacturing method of electronic component mounting board

Publications (2)

Publication Number Publication Date
JPH04291788A JPH04291788A (en) 1992-10-15
JP2739123B2 true JP2739123B2 (en) 1998-04-08

Family

ID=13029975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5654291A Expired - Fee Related JP2739123B2 (en) 1991-03-20 1991-03-20 Manufacturing method of electronic component mounting board

Country Status (1)

Country Link
JP (1) JP2739123B2 (en)

Also Published As

Publication number Publication date
JPH04291788A (en) 1992-10-15

Similar Documents

Publication Publication Date Title
US7145238B1 (en) Semiconductor package and substrate having multi-level vias
JPH08321671A (en) Bump electrode structure and manufacture thereof
US6548766B2 (en) Printed wiring board for attachment to a socket connector, having recesses and conductive tabs
US20020096750A1 (en) Package for semiconductor chip having thin recess portion and thick plane portion
JPH01261849A (en) Semiconductor device
KR100326834B1 (en) Wire-bonded semiconductor device and semiconductor package
EP1197128B1 (en) Thermal vias arranged in a printed circuit board to conduct heat away from surface mounted components through the board
US6278185B1 (en) Semi-additive process (SAP) architecture for organic leadless grid array packages
KR100346899B1 (en) A Semiconductor device and a method of making the same
JPH10313157A (en) Printed board
JP2739123B2 (en) Manufacturing method of electronic component mounting board
JP3914458B2 (en) Method for manufacturing circuit board having heat sink
JP2001358257A (en) Method for manufacturing substrate for semiconductor device
JPS6150350A (en) Hybrid integrated circuit substrate
JP2000243869A (en) Wiring board
JP2784523B2 (en) Substrate for mounting electronic components
JPH1051094A (en) Printed wiring board, and its manufacture
JPS6350862B2 (en)
KR100243023B1 (en) Semiconductor package and method of manufacturing and laminating it
JPH07122831A (en) Circuit board and manufacture thereof
JP2755255B2 (en) Semiconductor mounting substrate
JPH10163002A (en) Chip electronic component and its manufacture
JP2753713B2 (en) Lead frame assembly sheet
JPH08236659A (en) Leadless chip carrier and printed board for mounting it
JP2743524B2 (en) Hybrid integrated circuit device

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080123

Year of fee payment: 10

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090123

Year of fee payment: 11

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 11

Free format text: PAYMENT UNTIL: 20090123

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 12

Free format text: PAYMENT UNTIL: 20100123

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100123

Year of fee payment: 12

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110123

Year of fee payment: 13

LAPS Cancellation because of no payment of annual fees