JP2000243869A - Wiring board - Google Patents

Wiring board

Info

Publication number
JP2000243869A
JP2000243869A JP11039607A JP3960799A JP2000243869A JP 2000243869 A JP2000243869 A JP 2000243869A JP 11039607 A JP11039607 A JP 11039607A JP 3960799 A JP3960799 A JP 3960799A JP 2000243869 A JP2000243869 A JP 2000243869A
Authority
JP
Japan
Prior art keywords
stiffener
wiring board
electronic component
opening
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11039607A
Other languages
Japanese (ja)
Inventor
Koju Ogawa
幸樹 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Niterra Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to JP11039607A priority Critical patent/JP2000243869A/en
Publication of JP2000243869A publication Critical patent/JP2000243869A/en
Pending legal-status Critical Current

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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board with a stiffener made of metal which does not obstruct mounting of an electronic component and can be miniaturized. SOLUTION: In a wiring board 1 where an electronic component 105 different from a semiconductor element 100 is mounted on a part position of an aperture 26 of a hole or a notch formed in a stiffener 21 made of metal, an insulating layer 31 is formed on a wall surface 26a of the aperture 26. Since the insulating layer 31 is formed on the wall surface 26a, possibility of shortcircutting is excluded, so that the aperture 26 can be miniaturized to the limit size capable of insertion of the electronic component 105. Thereby strength of the stiffener 21 can be increased as completely as possible, and the wiring board 1 can be miniaturized.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、MPUなどの半導
体素子(半導体集積回路素子)等の電子部品の実装(封
止)に用いられる配線基板(ICパッケージ)に関し、
詳しくは基板に金属製スティフナが接合され、その金属
製スティフナに形成された穴若しくは切欠き等の開口の
部位に、半導体素子とは別の電子部品(電子素子)が実
装される半導体素子実装用の配線基板に関する。
The present invention relates to a wiring board (IC package) used for mounting (sealing) electronic components such as a semiconductor device (semiconductor integrated circuit device) such as an MPU.
More specifically, a metal stiffener is bonded to a substrate, and an electronic component (electronic element) different from the semiconductor element is mounted on an opening such as a hole or a notch formed in the metal stiffener. Related to a wiring board.

【0002】[0002]

【従来の技術】金属製スティフナ(補強板)の接合され
た配線基板に、半導体素子(以下ICチップともいう)
に加えて別の電子部品を実装する構造としては次のよう
なものがある。例えば、図5に示した配線基板111の
ように金属製スティフナ121のICチップ実装用の矩
形の開口(開口)125の部位を全体的に大きくし、実
装されるICチップ100の周囲(外側)に、間隔を保
持して電子部品105を実装するというものである。ま
た、図6に示した配線基板112のように金属製スティ
フナ121にICチップ実装用の開口125とは別個独
立の電子部品105専用の開口(穴)126を設け、そ
の専用の開口126の部位に電子部品105を実装する
というものである。さらには図7に示した配線基板11
3のようにICチップ100の実装用の開口125を局
所的に切り広げて切欠き(凹部)126を設け、その切
欠き126の部位に電子部品105を実装するというも
のである。
2. Description of the Related Art A semiconductor element (hereinafter also referred to as an IC chip) is mounted on a wiring board to which a metal stiffener (reinforcement plate) is joined.
In addition to the above, there is the following structure for mounting another electronic component. For example, as in the case of the wiring board 111 shown in FIG. 5, the area of the rectangular opening (opening) 125 for mounting the IC chip of the metal stiffener 121 is enlarged as a whole, and the periphery (outside) of the mounted IC chip 100. Then, the electronic component 105 is mounted while maintaining the interval. Further, like the wiring board 112 shown in FIG. 6, an opening (hole) 126 dedicated to the electronic component 105 independent of the IC chip mounting opening 125 is provided in the metal stiffener 121, and a portion of the dedicated opening 126 is provided. The electronic component 105 is mounted on the device. Further, the wiring board 11 shown in FIG.
As shown in FIG. 3, a notch (recess) 126 is provided by locally opening and widening the mounting opening 125 of the IC chip 100, and the electronic component 105 is mounted in the notch 126.

【0003】このような配線基板をなす金属製スティフ
ナ121の補強材としての役割上からは電子部品が実装
される開口の部位をなるべく小さくし、残存するスティ
フナの幅を大きく確保するのが好ましい。しかしなが
ら、図5に示した配線基板111のようにICチップ実
装用の開口(開口)125の全体を広げ、ICチップ1
00の周囲(外側)に電子部品105を実装するように
したものでは、その開口125を小さくするほど実装時
に電子部品105がICチップ100に接触する危険性
が高くなる。
In view of the role of the metal stiffener 121 constituting such a wiring board as a reinforcing material, it is preferable to make the opening where the electronic component is mounted as small as possible and to secure a large width of the remaining stiffener. However, the entirety of the opening (opening) 125 for mounting the IC chip as in the wiring board 111 shown in FIG.
In the case where the electronic component 105 is mounted around (outside) 00, the risk that the electronic component 105 comes into contact with the IC chip 100 during mounting increases as the opening 125 becomes smaller.

【0004】一方、図6や図7に示した配線基板11
2、113のように独立状や切欠き状の開口126を設
けたものでは、ICチップ100との接触の問題はな
い。しかし、これらのものではスティフナ121に設け
られた開口126の壁面との絶縁確保のため、その壁面
と電子部品105との間に確実に間隙を設ける必要があ
る。このため、従来は適度の間隙ができるように開口1
26を大きめに形成していた。さらに図8に示したよう
に、電子部品105の実装時には開口126の壁面12
6aに沿ってガイド(冶具)108を挿入し、そのガイ
ド108に沿わせて電子部品105を落とし込んで位置
決めする。そして、その下で電子部品105を基板11
0面に形成された端子にハンダ付けし、溶融ハンダがス
ティフナ121の開口126における壁面126a例え
ば銅合金製のスティフナではその表面にかけられた金メ
ッキ面に濡れ広がるのを防止していた。
On the other hand, the wiring board 11 shown in FIGS.
In the case where the independent or notched openings 126 are provided as in 2, 113, there is no problem of contact with the IC chip 100. However, in these devices, it is necessary to reliably provide a gap between the wall surface and the electronic component 105 in order to ensure insulation from the wall surface of the opening 126 provided in the stiffener 121. For this reason, conventionally, the opening 1 is formed so that an appropriate gap is formed.
26 was formed larger. Further, as shown in FIG. 8, when the electronic component 105 is mounted,
A guide (jig) 108 is inserted along 6a, and the electronic component 105 is dropped and positioned along the guide 108. Then, the electronic component 105 is placed under the substrate 11.
Solder was applied to the terminal formed on the surface 0 to prevent molten solder from spreading on the gold-plated surface applied to the wall surface 126a of the opening 126 of the stiffener 121, for example, a copper alloy stiffener.

【0005】[0005]

【発明が解決しようとする課題】上記したように図5に
示した配線基板111では、スティフナ121の強度を
高めようとすれば開口125を小さくする必要があり、
電子部品105の実装においてICチップ100への接
触の危険性が高くなる。一方、開口125を大きくし、
かつ強度を低下させないためにはスティフナ121さら
には配線基板111の平面形状を大きくする必要があ
り、半導体装置の小型化の要請に応えられない。そして
このような問題は実装すべき電子部品の数が増えるほど
顕著となる。このために場合によっては、電子部品のみ
ICチップと分離してマザーボードに設置することもあ
る。しかし、これではICチップとの配線距離が長くな
り、信号遅延の原因にもなるなど電気的特性上好ましく
ない。
As described above, in the wiring board 111 shown in FIG. 5, it is necessary to reduce the size of the opening 125 in order to increase the strength of the stiffener 121.
The risk of contact with the IC chip 100 in mounting the electronic component 105 increases. On the other hand, the opening 125 is enlarged,
In addition, in order not to reduce the strength, it is necessary to increase the planar shape of the stiffener 121 and the wiring substrate 111, and it is not possible to meet the demand for miniaturization of the semiconductor device. Such a problem becomes more remarkable as the number of electronic components to be mounted increases. For this reason, in some cases, only the electronic components may be separated from the IC chip and installed on the motherboard. However, this is not preferable in terms of electrical characteristics, such as increasing the wiring distance to the IC chip and causing signal delay.

【0006】さらに、図6、7に示した構造のものでは
図8に示したように、電子部品105を実装する際に、
ガイド108を開口126の壁面に沿って挿入し、これ
にてガイドさせながら落し込み状にセットすることで位
置決め、実装していたため、このようなガイド108を
要するなど作業効率が悪かった。本発明は、電子部品の
実装に支障なく、小型化を達成できる金属製スティフナ
付きの配線基板を提供することにある。
Further, in the case of the structure shown in FIGS. 6 and 7, as shown in FIG.
Since the guide 108 is inserted along the wall surface of the opening 126 and is positioned and mounted by being set in a recessed shape while being guided by this, the work efficiency is poor, such as the need for such a guide 108. An object of the present invention is to provide a wiring board with a metal stiffener that can achieve downsizing without hindering mounting of electronic components.

【0007】[0007]

【課題を解決するための手段】前記の目的を達成するた
めに本発明は、基板に金属製スティフナが接合され、そ
の金属製スティフナに形成された穴若しくは切欠き等の
開口の部位に、半導体素子とは別の電子部品が実装され
る半導体素子実装用の配線基板において、前記開口の壁
面に絶縁層を形成したことを特徴とする。
SUMMARY OF THE INVENTION In order to achieve the above object, the present invention relates to a method of manufacturing a semiconductor device, comprising the steps of: joining a metal stiffener to a substrate; and forming a semiconductor device in a hole or a notch formed in the metal stiffener. In a wiring board for mounting a semiconductor element on which an electronic component different from the element is mounted, an insulating layer is formed on a wall surface of the opening.

【0008】前記の手段においては、前記開口の壁面
に、絶縁層が形成されているため短絡の問題がないこと
から、金属製スティフナに形成する開口は電子部品の挿
入可能のぎりぎりの大きさまで小さくすることができ
る。すなわち、本発明によれば、電子部品の実装におい
て短絡の危険もなく、したがってスティフナの可及的な
強度アップを図ることができると共に、スティフナさら
には配線基板の小型化を図ることができる。
In the above means, since the insulating layer is formed on the wall surface of the opening, there is no problem of short-circuiting. Therefore, the opening formed in the metal stiffener is as small as possible to insert electronic components. can do. That is, according to the present invention, there is no danger of a short circuit in the mounting of the electronic component. Therefore, the strength of the stiffener can be increased as much as possible, and the size of the stiffener and the wiring board can be reduced.

【0009】さらに、このように開口を電子部品の挿入
可能のぎりぎりの大きさとすれば、開口の壁面を挿入時
のガイドとすることができるので、従来のように実装用
のガイド(治具)を要することなく電子部品を落とし込
むだけで、短絡の心配もなく端子同士の位置決め、実装
ができる。したがつて、電子部品の実装作業の効率化を
図ることができ、作業効率の大幅な向上が期待される。
Furthermore, if the opening is formed to the size just enough to allow the insertion of an electronic component, the wall surface of the opening can be used as a guide at the time of insertion, so that a mounting guide (jig) as in the prior art is used. By simply dropping electronic components without the need for mounting, positioning and mounting of terminals can be performed without fear of short-circuiting. Therefore, the efficiency of the mounting work of the electronic components can be improved, and a significant improvement in the working efficiency is expected.

【0010】なお前記手段において、前記絶縁層は樹脂
やセラミックなどの適宜の素材(絶縁材)で形成すれば
よい。因みにスティフナを形成する材質は強度、熱伝達
率より、銅若しくは銅合金で形成するのが好ましい。
In the above means, the insulating layer may be formed of an appropriate material (insulating material) such as resin or ceramic. Incidentally, the material for forming the stiffener is preferably formed of copper or a copper alloy in view of strength and heat transfer coefficient.

【0011】[0011]

【発明の実施の形態】本発明の実施の形態を図1〜3を
参照しながら詳細に説明する。図1は、本形態の配線基
板1を示す断面図、図2はその要部Aの拡大図、図3は
図1の平面図である。この配線基板1は積層されたオー
ガニック基板2と銅製スティフナ21とを主体としLG
A(ランドグリッドアレイ)タイプをなすように次のよ
うに構成されている。すなわち、基板2は、所定の配線
層(図示せず)を備え、平面視、略矩形の平板形状に形
成されてなるもので、上面3には実装するICチップや
電子部品の電極と接続される端子5やダイアタッチ部6
が形成されている。そして基板2の図示下面4には端子
7が多数配置されており、これらの端子等には、Niメ
ッキ及び金メッキがかけられている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to FIGS. FIG. 1 is a sectional view showing a wiring board 1 of the present embodiment, FIG. 2 is an enlarged view of a main part A thereof, and FIG. 3 is a plan view of FIG. This wiring substrate 1 is mainly composed of a laminated organic substrate 2 and a copper stiffener 21 and has an LG
A (land grid array) type is configured as follows. That is, the substrate 2 is provided with a predetermined wiring layer (not shown) and is formed in a substantially rectangular plate shape in plan view. The upper surface 3 is connected to electrodes of IC chips and electronic components to be mounted. Terminal 5 and die attach part 6
Are formed. A large number of terminals 7 are arranged on the illustrated lower surface 4 of the substrate 2, and these terminals and the like are plated with Ni and gold.

【0012】そしてこのような基板2の上面3には、本
例では銅製のスティフナ21が熱硬化性の接着(樹脂)
シート9を介して例えば175℃で2時間圧着されて接
着されている。このスティフナ21にはICチップ10
0の実装部位をなす開口25に加えて電子部品105の
実装部位をなす複数の開口26が設けられている。そし
て、中央のICチップ実装用の開口25は平面視矩形と
され、電子部品105の実装部位をなす複数の開口26
はその外側に窓状に開口している。なお本形態では、ス
ティフナ21にはその全面に図示はしないがニッケルメ
ッキ層及び最表面に金メッキ層が形成されている。そし
て、スティフナ21の開口25、26の壁面25a、2
6aに絶縁層31が例えば10〜30μm厚さの形成さ
れ、電子部品の実装部を形成している。
A stiffener 21 made of copper in this embodiment is bonded to the upper surface 3 of the substrate 2 by thermosetting adhesive (resin).
For example, it is pressed and bonded at 175 ° C. for 2 hours via the sheet 9. This stiffener 21 has an IC chip 10
In addition to the opening 25 that forms the mounting part of the electronic component 105, a plurality of openings 26 that form the mounting part of the electronic component 105 are provided. The opening 25 for mounting the IC chip at the center is rectangular in a plan view, and the plurality of openings 26 forming the mounting portion of the electronic component 105 are formed.
Is opened like a window on the outside. In this embodiment, a stiffener 21 is formed with a nickel plating layer and a gold plating layer on the outermost surface (not shown). Then, the wall surfaces 25a of the openings 25, 26 of the stiffener 21 and 2
An insulating layer 31 having a thickness of, for example, 10 to 30 μm is formed on 6a to form a mounting portion of an electronic component.

【0013】このような絶縁層31は、例えばスティフ
ナ21の形成後、基板2への接着前に、壁面25a、2
6aに熱硬化性のエポキシ樹脂層(ペースト)をスクリ
ーン印刷し、150℃で2時間程度熱硬化してなるもの
である。なおスティフナ21は、切削やプレスによる打
ち抜き等の機械加工、レーザー加工、放電加工等により
開口25、26を形成した後、メッキをかけて形成され
る。
For example, after the formation of the stiffener 21 and before the adhesion to the substrate 2, the insulating layer 31 is formed on the wall surfaces 25 a, 2
A thermosetting epoxy resin layer (paste) is screen-printed on 6a and thermoset at 150 ° C. for about 2 hours. The stiffener 21 is formed by forming openings 25 and 26 by machining such as cutting or punching by pressing, laser machining, electric discharge machining or the like, and then plating.

【0014】このような本例のスティフナ付き配線基板
1においては、その開口25、26に、ICチップ10
0や他の電子部品105がハンダ付けにより実装される
が、その実装において、前記開口26の壁面26aに絶
縁層31が形成されているため短絡の問題がない。した
がって、金属製スティフナ21に形成する開口26は電
子部品105の挿入可能のぎりぎりの大きさまで小さく
することができる。本形態によれば、電子部品105の
実装において短絡の危険もなく、スティフナ21の可及
的な強度アップを図ることができ、しかもスティフナ2
1さらには配線基板1の小型化を図ることができる。
In the wiring board 1 with the stiffener of the present embodiment, the IC chips 10 are provided in the openings 25 and 26 thereof.
0 and other electronic components 105 are mounted by soldering, but there is no short-circuit problem in the mounting because the insulating layer 31 is formed on the wall surface 26a of the opening 26. Therefore, the opening 26 formed in the metal stiffener 21 can be reduced to a size as small as the size at which the electronic component 105 can be inserted. According to the present embodiment, there is no danger of a short circuit in mounting the electronic component 105, and the strength of the stiffener 21 can be increased as much as possible.
1 and the size of the wiring board 1 can be reduced.

【0015】しかもこのように開口26を電子部品10
5の挿入可能のぎりぎりの大きさとすれば壁面26aを
挿入時のガイドとすることができるので、従来のように
実装用のガイド(治具)を別途に要することなく電子部
品105を落とし込むだけで、短絡の心配もなく端子同
士の位置決めもできる。したがつて、電子部品105の
実装作業の効率化を図ることができ、作業効率の大幅な
向上が期待される。なおこのようなガイドの作用をさせ
るためには、電子部品105と壁面26aとの間隙が例
えば0.5mm以下となるように、好ましくは0.1〜
0.5mmとなるように開口26の大きさを設定すると
よい。
In addition, as described above, the opening 26 is formed in the electronic component 10.
5, the wall 26a can be used as a guide at the time of insertion, so that only the electronic component 105 is dropped without a separate mounting guide (jig) as in the related art. In addition, the terminals can be positioned without fear of a short circuit. Therefore, the efficiency of the mounting work of the electronic component 105 can be improved, and a significant improvement in the working efficiency is expected. In order to perform such a guide function, it is preferable that the gap between the electronic component 105 and the wall surface 26a is, for example, 0.5 mm or less.
The size of the opening 26 may be set to be 0.5 mm.

【0016】本発明において絶縁層は、スティフナの開
口の壁面にのみ形成してあればよいが、その主面23、
24を含む全体に形成してあってもよい。ただし、その
場合には、スティフナ21の両主面23、24と壁面2
5a、26aとのなす交差稜には、アール又は傾斜状な
どの面取りを付けておくとよい。交差稜にはスティフナ
21の製造上バリができ易く、このような場合には絶縁
層31はそのバリの部位で一定厚さに保持されにくい
が、面取りが付けられていれば一定厚さに保持されやす
いためである。もっとも、開口の壁面のみに絶縁層を設
ける場合でも壁面と主面とのなす交差稜にはアール又は
傾斜状などの面取りを付けておくのが好ましい。前記形
態のように樹脂のペーストを印刷して絶縁層を形成する
場合には、交差稜に面取りがないと、余分に印刷(塗
布)された同ペーストが壁面をそのまま垂れ下がってし
まうため、それが硬化してバリとなる。しかし、面取り
が付けてあれば、同ペーストが垂れ下がってもその面取
り部に沿って流動するためにバリとなりにくいためであ
る。
In the present invention, the insulating layer may be formed only on the wall surface of the opening of the stiffener.
24 may be formed as a whole. However, in that case, both main surfaces 23 and 24 of the stiffener 21 and the wall surface 2
The intersection ridges formed with 5a and 26a may be chamfered in a round or inclined shape. Burrs are likely to be formed on the intersection ridges due to the manufacture of the stiffener 21. In such a case, the insulating layer 31 is hard to be maintained at a constant thickness at the burrs, but is maintained at a constant thickness if chamfered. Because it is easy to be done. However, even when the insulating layer is provided only on the wall surface of the opening, it is preferable that the intersection ridge formed between the wall surface and the main surface be chamfered in a round or inclined shape. In the case where the insulating layer is formed by printing a resin paste as in the above-described embodiment, if there is no chamfer at the intersection ridge, the excessively printed (coated) paste hangs down the wall surface as it is. It hardens and becomes burrs. However, if the chamfer is provided, even if the paste hangs down, the paste flows along the chamfered portion, so that the paste hardly forms burrs.

【0017】また、前記形態では絶縁層31を熱硬化性
樹脂とし、スクリーン印刷法により形成したが、形成手
法はこれに限定されるものではなく、樹脂製シートを接
着してもよい。さらに、セラミック等の絶縁物質の溶
射、スパッタリング、CVD或いはPVDによって形成
することもできる。なお絶縁層は、スティフナを基板へ
接合した後に形成することもできる。
In the above embodiment, the insulating layer 31 is made of a thermosetting resin and is formed by a screen printing method. However, the forming method is not limited to this, and a resin sheet may be bonded. Further, it can be formed by spraying, sputtering, CVD or PVD of an insulating material such as ceramic. Note that the insulating layer can be formed after the stiffener is bonded to the substrate.

【0018】本発明は前記の形態のものに限定されるも
のではなく、種々設計変更して具体化できる。図4は本
発明の別の実施形態を示したものである。この配線基板
51は、電子部品105の実装用の開口26を独立の穴
(開口)ではなく、中央のICチップ100の実装用の
開口25に連なる切欠き状とし、その壁面26aに絶縁
層(図示せず)を形成したものであるが、前記形態と本
質的相違はないことから、同一部位には同一の符号を付
すに止め、その説明を省略する。なお、いずれの形態に
おいてもその開口26の数、配置は設計に応じて適宜に
設定すればよい。
The present invention is not limited to the above-described embodiment, but can be embodied with various design changes. FIG. 4 shows another embodiment of the present invention. In the wiring board 51, the opening 26 for mounting the electronic component 105 is not an independent hole (opening) but a cutout continuous with the mounting opening 25 for the central IC chip 100, and an insulating layer ( (Not shown), but since there is no essential difference from the above-described embodiment, the same portions will be denoted by the same reference numerals and description thereof will be omitted. In any case, the number and arrangement of the openings 26 may be appropriately set according to the design.

【0019】前記形態では、LGA(ランドグリッドア
レイ)タイプの配線基板において具体化したが、BGA
(ボールグリッドアレイ)タイプ、PGA(ピングリッ
ドアレイ)タイプなど、プリント基板(外部回路基板)
との接続方式にかかわらず、スティフナが接合され、該
スティフナに形成された開口の部位に電子部品が実装さ
れる各種の配線基板において広く適用できる。なおステ
ィフナは銅や銅合金のみならずステンレス合金から形成
してもよい。
In the above embodiment, the present invention is embodied in an LGA (land grid array) type wiring board.
Printed circuit board (external circuit board) such as (ball grid array) type and PGA (pin grid array) type
Regardless of the connection method, the present invention can be widely applied to various wiring boards in which a stiffener is joined and an electronic component is mounted on an opening formed in the stiffener. The stiffener may be made of not only copper and copper alloy but also stainless steel.

【0020】[0020]

【発明の効果】以上の説明より明らかなように、本発明
のスティフナ付き配線基板によれば、開口の壁面に絶縁
層が形成されているため短絡の問題がない。したがっ
て、金属製スティフナに形成する開口は電子部品の挿入
可能のぎりぎりの大きさまで小さくすることができる。
すなわち、本発明によれば、電子部品の実装において短
絡の危険もなく、したがってスティフナの可及的な強度
アップおよび配線基板の小型化を図ることができる。
As is clear from the above description, according to the wiring board with the stiffener of the present invention, since the insulating layer is formed on the wall surface of the opening, there is no short circuit problem. Therefore, the opening formed in the metal stiffener can be reduced to a size as small as possible to insert an electronic component.
That is, according to the present invention, there is no danger of a short circuit in the mounting of the electronic component, so that the strength of the stiffener can be increased as much as possible and the size of the wiring board can be reduced.

【0021】さらに、このように開口を電子部品の挿入
可能のぎりぎりの大きさとすれば、開口の壁面を挿入時
のガイドとすることができるので、従来のように実装用
のガイド(治具)を要することなく電子部品を落とし込
むだけで、短絡の心配もなく端子同士の位置決め、実装
ができる。したがつて、電子部品の実装作業の効率化を
図ることができる。
Furthermore, if the opening has a size just enough to allow the insertion of an electronic component, the wall surface of the opening can be used as a guide at the time of insertion, so that a mounting guide (jig) as in the prior art is used. By simply dropping electronic components without the need for mounting, positioning and mounting of terminals can be performed without fear of short-circuiting. Therefore, the efficiency of the mounting operation of the electronic component can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る配線基板の実施形態例の断面図。FIG. 1 is a sectional view of an embodiment of a wiring board according to the present invention.

【図2】図1の要部Aの拡大図。FIG. 2 is an enlarged view of a main part A of FIG.

【図3】図1の配線基板の平面図。FIG. 3 is a plan view of the wiring board of FIG. 1;

【図4】本発明に係る配線基板の別の実施形態例の平面
図。
FIG. 4 is a plan view of another embodiment of the wiring board according to the present invention.

【図5】従来の金属製スティフナ付き配線基板の平面
図。
FIG. 5 is a plan view of a conventional wiring board with a metal stiffener.

【図6】従来の金属製スティフナ付き配線基板の平面
図。
FIG. 6 is a plan view of a conventional wiring board with a metal stiffener.

【図7】従来の金属製スティフナ付き配線基板の平面
図。
FIG. 7 is a plan view of a conventional wiring board with a metal stiffener.

【図8】図6の配線基板の開口に電子部品を実装する説
明用断面図。
FIG. 8 is an exemplary sectional view for mounting an electronic component in an opening of the wiring board in FIG. 6;

【符号の説明】[Explanation of symbols]

1 配線基板 2 基板 21 金属製スティフナ 26 開口 26a 開口の壁面 31 絶縁層 100 半導体素子 105 電子部品 DESCRIPTION OF SYMBOLS 1 Wiring board 2 Substrate 21 Metal stiffener 26 Opening 26a Opening wall surface 31 Insulating layer 100 Semiconductor element 105 Electronic component

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板に金属製スティフナが接合され、そ
の金属製スティフナに形成された穴若しくは切欠き等の
開口の部位に、半導体素子とは別の電子部品が実装され
る半導体素子実装用の配線基板において、前記開口の壁
面に絶縁層を形成したことを特徴とする配線基板。
A metal stiffener is bonded to a substrate, and an electronic component different from the semiconductor element is mounted on an opening such as a hole or a notch formed in the metal stiffener. A wiring board, wherein an insulating layer is formed on a wall surface of the opening.
【請求項2】 前記絶縁層が樹脂からなることを特徴と
する請求項1に記載の配線基板。
2. The wiring board according to claim 1, wherein the insulating layer is made of a resin.
JP11039607A 1999-02-18 1999-02-18 Wiring board Pending JP2000243869A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11039607A JP2000243869A (en) 1999-02-18 1999-02-18 Wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11039607A JP2000243869A (en) 1999-02-18 1999-02-18 Wiring board

Publications (1)

Publication Number Publication Date
JP2000243869A true JP2000243869A (en) 2000-09-08

Family

ID=12557811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11039607A Pending JP2000243869A (en) 1999-02-18 1999-02-18 Wiring board

Country Status (1)

Country Link
JP (1) JP2000243869A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008096450A1 (en) * 2007-02-09 2008-08-14 Panasonic Corporation Circuit board, multilayer circuit board, and electronic device
US8119929B2 (en) 2007-11-08 2012-02-21 Shinko Electric Industries Co., Ltd. Wiring board and method for manufacturing the same
JP2012104557A (en) * 2010-11-08 2012-05-31 Ngk Spark Plug Co Ltd Wiring board with electronic component and manufacturing method of the same
JP2013102143A (en) * 2011-10-13 2013-05-23 Sumitomo Bakelite Co Ltd Semiconductor package and semiconductor device
US8479385B2 (en) 2010-09-24 2013-07-09 Shinko Electric Industries Co., Ltd. Method of producing wiring substrate
JPWO2016189609A1 (en) * 2015-05-25 2018-03-15 オリンパス株式会社 3D wiring board and 3D wiring board manufacturing method

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008096450A1 (en) * 2007-02-09 2008-08-14 Panasonic Corporation Circuit board, multilayer circuit board, and electronic device
EP2129195A1 (en) * 2007-02-09 2009-12-02 Panasonic Corporation Circuit board, multilayer circuit board, and electronic device
JPWO2008096450A1 (en) * 2007-02-09 2010-05-20 パナソニック株式会社 Circuit board, laminated circuit board, and electronic equipment
EP2129195A4 (en) * 2007-02-09 2011-06-15 Panasonic Corp Circuit board, multilayer circuit board, and electronic device
US8119929B2 (en) 2007-11-08 2012-02-21 Shinko Electric Industries Co., Ltd. Wiring board and method for manufacturing the same
US8479385B2 (en) 2010-09-24 2013-07-09 Shinko Electric Industries Co., Ltd. Method of producing wiring substrate
JP2012104557A (en) * 2010-11-08 2012-05-31 Ngk Spark Plug Co Ltd Wiring board with electronic component and manufacturing method of the same
JP2013102143A (en) * 2011-10-13 2013-05-23 Sumitomo Bakelite Co Ltd Semiconductor package and semiconductor device
JPWO2016189609A1 (en) * 2015-05-25 2018-03-15 オリンパス株式会社 3D wiring board and 3D wiring board manufacturing method

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