US20020096750A1 - Package for semiconductor chip having thin recess portion and thick plane portion - Google Patents

Package for semiconductor chip having thin recess portion and thick plane portion Download PDF

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Publication number
US20020096750A1
US20020096750A1 US10/102,901 US10290102A US2002096750A1 US 20020096750 A1 US20020096750 A1 US 20020096750A1 US 10290102 A US10290102 A US 10290102A US 2002096750 A1 US2002096750 A1 US 2002096750A1
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Prior art keywords
layer
metal
pattern layer
metal plate
package
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Abandoned
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US10/102,901
Inventor
Katsunobu Suzuki
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NEC Electronics Corp
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Katsunobu Suzuki
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Priority to US10/102,901 priority Critical patent/US20020096750A1/en
Publication of US20020096750A1 publication Critical patent/US20020096750A1/en
Assigned to NEC ELECTRONICS CORPORATION reassignment NEC ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NEC CORPORATION
Abandoned legal-status Critical Current

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01065—Terbium [Tb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Dispersion Chemistry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

In a package for mounting including a metal plate having a recess portion for mounting a semiconductor chip and a plane portion for mounting a metal pattern layer, the recess portion is thinner than the plane portion.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to a package for a semiconductor chip, and more particularly, to a package having a recess portion for mounting a semiconductor chip and a plane portion for mounting a metal pattern layer. [0002]
  • 2. Description of the Related Art [0003]
  • A prior art package includes a heat spreader (metal plate) having a recess portion for mounting a semiconductor chip and a plane portion for mounting a metal pattern layer. The metal plate has a uniform thickness, and a recess having a predetermined depth is formed in the metal plate by a pressing process using metal molds (see Ashtok Domadia et al., TBGA Bond Process for Ground and Power Plane Connections”, IEEE 1996 Electronic Components and Technology Conference, pp. 707-712). This will be explained later in detail. [0004]
  • In the above-described prior art package, since the recess is formed in the metal plate by a pressing process, it is impossible to remarkably increase the thickness of the metal plate. Even in this case, the thickness of the metal plate is increased by a moderate value to increase the rigidity of the plane portion thereof. This is advantageous in terms of the handling of the package and forming solder balls. Simultaneously, the rigidity of the metal plate around the recess is increased. Therefore, strain generated in the metal plate around the semiconductor chip due to the heating thereof is hardly leaked through the metal plate around the recess thereof, so that large stress is applied to the back surface of the semiconductor chip. Thus, the semiconductor chip is easily peeled from the metal plate, which deteriorates the reliability of the package. [0005]
    • SUMMARY OF THE INVENTION
  • It is an object of the present invention to provide a package for a semiconductor chip capable of decreasing the manufacturing cost. [0006]
  • Another object is to improve the reliability of a package for a semiconductor chip. [0007]
  • According to the present invention, in a package for mounting including a metal plate having a recess portion for mounting a semiconductor chip and a plane portion for mounting a metal pattern layer, the recess portion is thinner than the plane portion. [0008]
  • Also, in a method for manufacturing a package including a metal plate including a recess portion for mounting a semiconductor chip and a plane portion for mounting a metal pattern layer, a photoresist pattern layer is formed to cover the plane portion of the metal plate, and the metal plate is etched by using the photoresist pattern layer as a mask.[0009]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The present invention will be more clearly understood from the description set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein: [0010]
  • FIG. 1 is a cross-sectional view illustrating a prior art package; [0011]
  • FIG. 2 is a cross-sectional view illustrating a first embodiment of the package according to the present invention; [0012]
  • FIG. 3 is a partial perspective view of the package of FIG. 2; [0013]
  • FIGS. 4A through 4H are cross-sectional views for explaining the method for manufacturing the package of FIGS. 2 and 3. [0014]
  • FIG. 5 is a cross-sectional view illustrating a second embodiment of the package according to the present invention; and [0015]
  • FIGS. 6A through 6H are cross-sectional views for explaining the method for manufacturing the package of FIG. 5.[0016]
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Before the description of the preferred embodiments, a prior art package with be explained with reference to FIG. 1 (see: Ashtok Domadia et al., “TBGA Bond Process for Ground and Power Plane Connections”, IEEE [0017] 1996 Electronic Components and Technology Conference, pp.707-712).
  • In FIG. 1, which illustrates a prior art one-connection-layer type ball grid array (BGA) type package, a [0018] heat spreader 101 made of metal has a uniform thickness, and a recess 101 a having a predetermined depth is formed in the heat spreader 101 by a pressing process using metal molds. Note that the heat spreader 101 also serves as a ground plane layer.
  • A power [0019] supply plane layer 102 is adhered by an adhesive layer 103 on a plane portion 101 b of the heat spreader 101. Also, an organic insulating pattern layer 103 is adhered by an adhesive layer 105 on the power supply plane layer 102.
  • On the other hand, a [0020] semiconductor chip 106 is mounted in the recess 101 a of the heat spreader 101 by a mount material layer 108 made of Ag paste.
  • [0021] Electrodes 106 a of the semiconductor chip 106, the heat spreader 101, the power supply plane layer 102 and the like are electrically connected by copper foil connection lines 108 using a tape automated bonding (TAB) process.
  • The [0022] semiconductor chip 106 is sealed by a thermosetting resin layer 109.
  • [0023] Solder balls 110 as external electrodes are formed on the copper foil connection lines 108.
  • In the package of FIG. 1, since the recess [0024] 101 a is formed in the heat spreader 101 by a pressing process, it is impossible to remarkably increase the thickness of the heat spreader 101. Even in this case, the thickness of the heat spreader 101 is increased by a moderate value to increase the rigidity of the plane portion 101 b of the heat spreader 101. This is advantageous in terms of the handling of the package and forming the solder balls 110. Simultaneously, the rigidity of the heat spreader 101 around the recess 101 a thereof as indicated by X in FIG. 1 is increased. Therefore, strain generated in the heat spreader 101 around the semiconductor chip 106 due to the heating thereof is hardly leaked through the heat spreader 101 around the recess 101 a thereof, so that large stress is applied to the back surface of the semiconductor chip 106 and the mount material layer 107. Thus, the semiconductor chip 106 is easily peeled from the heat spreader 101, which deteriorates the reliability of the package.
  • Note that, if the [0025] heat spreader 101 is constructed in advance so that the center portion is thin to decrease the rigidity thereof and the peripheral portion is thick, to increase the rigidity thereof, the above-mentioned disadvantages are dissolved. However, in this case, the manufacturing steps become complex, which increases the manufacturing cost.
  • In FIG. 2, which illustrates a first embodiment of the package according to the present invention, a heat spreader I made of copper or aluminum has a thin recess portion la and a [0026] thick plane portion 1 b. Note that the heat spreader 1 also serves as a ground plane layer.
  • An organic [0027] insulating pattern layer 2 made of polyimide is formed on the plane portion 1 b of the heat spreader 1, and a metal pattern layer 3 made of copper foil is formed on the organic insulating pattern layer 2.
  • On the other hand, a [0028] semiconductor chip 4 is mounted on the recess portion 1 a of the heat spreader 1 by a mount material layer 6 made of Ag paste.
  • [0029] Electrodes 4 a of the semiconductor chip 4, the heat spreader 1 and the metal pattern layer 3 are electrically connected by bonding wire 6 made of Au.
  • The [0030] semiconductor chip 4 is sealed by a thermosetting resin layer 7. In this case, a dam 8 is provided to prevent the thermosetting resin layer 7 from being leaked into the plane portion 1 b of the heat spreader 1.
  • [0031] Solder balls 9 as external electrodes are formed on the metal pattern layer 3. In this case, each of the solder balls 9 is connected via the metal pattern layer 3 at throughholes 2 a of the organic insulating pattern layer 2 to land patterns 10. Note that the land patterns 10 are formed by etching the heat spreader 1.
  • In FIG. 3, which is a partial perspective view of the package of FIG. 2, the [0032] recess portion 1 a of the heat spreader 1 has a thickness Ta and the plane portion 1 b of the heat spreader 1 has a thickness Tb (>Ta). For example,
  • T b=0.20˜0.50 mm (preferably, about 0.20 mm)
  • T a =T b−about 20 to 50 μm
  • Also, the organic [0033] insulating pattern layer 2 has a thickness T2 of about 25 to 60 μm, preferably about 50 μm.
  • Further, the [0034] metal pattern layer 3 has a thickness T3of about 18 to 35 μm, preferably about 20 μm.
  • In the package of FIGS. 2 and 3, since the [0035] recess portion 1 a is formed in the heat spreader 1 by an etching process as will be explained later, it is possible to remarkably increase the thickness of the heat spreader 1. As a result, the rigidity of the plane portion 1 b of the heat spreader 1 can be sufficiently increased. This is advantageous in terms of the handling of the package and forming the solder balls 9. Simultaneously, the rigidity of the heat spreader 1 around the recess portion la thereof as indicated by Y in FIGS. 2 and 3 can be decreased. Therefore, strain generated in the heat spreader 1 around the semiconductor chip 4 due to the heating thereof is easily leaked through the heat spreader 1 around the recess portion 1 a thereof, so that large stress is hardly applied to the back surface of the semiconductor chip 4 and the mount material layer 5. Thus, the semiconductor chip 4 is hardly peeled from the heat spreader 1, which improves the reliability of the package.
  • The method for manufacturing the package of FIGS. 2 and 3 will be explained with reference to FIGS. 4A through 4H. [0036]
  • First, referring to FIG. 4A, an about 50 μm thick organic insulating [0037] layer 20 made of polyimide is coated on an about 0.2 mm thick metal plate (heat spreader) 1 of copper or aluminum. Then, a metal layer 30-a made of copper is deposited on the organic insulating layer 20. Then, a photoresist pattern layer 401 is formed by a photolithography process.
  • Next, referring to FIG. 4B, the metal layer [0038] 30-a is etched by using the photoresist pattern layer 31 as a mask, to form a metal pattern layer 3-a. In this case, a throughhole 2 a having a diameter of about 0.1 mm is perforated in the metal pattern layer 3-a. Then, the photoresist pattern layer 401 is removed.
  • Next, referring to FIG. 4C, the organic insulated [0039] layer 20 is etched by using the metal pattern layer 3-a as a mask, to form an organic insulating pattern layer 2. Note that the through hole 2 a is further deepened.
  • Next, referring to FIG. 4D, an about 25 μm thick metal layer [0040] 30-b made of copper is plated on the entire surface.
  • Next, referring to FIG. 4E, a [0041] photoresist pattern layer 402 for covering a plane portion of the metal plate 1 is formed by a photolithography process.
  • Next, referring to FIG. 4F, the metal layer [0042] 30-b is etched by using the photoresist pattern layer 402 as a mask, to form a metal pattern layer 3-b. The metal pattern layers 3-a and 3-b form a metal pattern layer 3. In this case, the metal plate 1 is also etched, so that the metal plate 1 is divided into a thin portion, i.e., a recess portion 1 a and a thick portion, i.e., a plane portion 1 b. Then, the photoresist pattern layer 402 is removed.
  • Next, referring to FIG. 4G, the [0043] plane portion 1 b of the metal plate 1 is etched to form a landpattern 10.
  • Next, referring to FIG. 4H, a pressing process using metal molds is performed upon the [0044] recess portion 1 a of the metal plate 1, to form a recess therein.
  • Finally, a semiconductor chip (not shown) is mounted on the [0045] recess portion 1 a of the heat spreader 1 by a mount material layer (not shown) made of Ag paste. Then, electrodes of the semiconductor chip, the metal plate 1 and the metal pattern layer 3 are electrically connected by bonding wire not shown) made of Au. Then the semiconductor chip is sealed by a thermosetting resin layer (not shown). Also, solder balls (not shown) as external electrodes are formed on the metal pattern layer 3. In this case, each of the solder balls 9 is connected via the metal pattern layer 3 at throughholes 2 a of the organic insulating pattern layer 2 to the land patterns 10. Thus, the package of FIGS. 2 and 3 is completed.
  • In the method as illustrated in FIGS. 4A through 4H, since the process of etching the [0046] metal plate 1 for the recess portion 1 a thereof is carried out simultaneously with the process of etching the metal layer 30-b for the metal pattern layer 3, the manufacturing steps can be simplified, which decreases the manufacturing cost. In addition, since the TAB process and the process using the adhesive layers 103 and 105 as in the prior art package of FIG. 1 are unnecessary, the manufacturing steps can be further simplified, which also decreases the manufacturing cost.
  • In FIG. 5, which illustrates a second embodiment of the package according to the present invention, a plurality of pedestal type protrusions It having a height of about 5 to 10 μm are provided on the recess portion la of the [0047] metal plate 1. As a result, the contact surface of the mount material layer 5 in contact with the metal plate 1 is increased, so that the tight contact characteristics of the semiconductor chip 1 to the metal plate 1 are improved, which improves the reliability of the package.
  • The method for manufacturing the package of FIG. 5 will be explained next with reference to FIGS. 6A through 6H. [0048]
  • First, referring to FIG. 6A, in the same way as in FIG. 4A, an about 50 μm thick organic insulating [0049] layer 20 made of polyimide is coated on an about 0.2 mm thick metal plate (heat spreader) 1 of copper or aluminum. Then, a metal layer 30-a made of copper is deposited on the organic insulating layer 20. Then, a photoresist pattern layer 401 is formed by a photolithography process.
  • Next, referring to FIG. 6B, in the same way as in FIG. 4B, the metal layer [0050] 30-a is etched by using the photoresist pattern layer 401 as a mask, to form a metal pattern layer 3-a. In this case, a throughhole 2 a having a diameter of about 0.1 mm is perforated in the metal pattern layer 3-a. Then, the photoresist pattern layer 401 is removed.
  • Next, referring to FIG. 6C, in the same way as in FIG. 4C, the organic insulated [0051] layer 20 is etched by using the metal pattern layer 3-a as a mask, to form an organic insulating pattern layer 2. Note that the throughhole 2 a is further deepened.
  • Next, referring to FIG. 6D, in the same way as in FIG. 4D, an about 25 μm thick metal layer [0052] 30-b made of copper is plated on the entire surface.
  • Next, referring to FIG. 6E, in a similar way to FIG. 4E, a [0053] photoresist pattern layer 402′ for covering a plane portion of the metal plate 1 is formed by a photolithography process. In this case, the photoresist pattern layer 402′ has a grid shape pattern including rectangles of about 50 to 100 μm in a recess portion of the metal plate 1.
  • Next, referring to FIG. 6F, in the same way as in FIG. 4F, the metal layer [0054] 30-b is etched by using the photoresist pattern layer 402 as a mask, to form a metal pattern layer 3-b. The metal pattern layers 3-a and 3-b form a metal pattern layer 3. In this case, the metal plate 1 is also etched, so that the metal plate 1 is divided into a thin portion, i.e., a recess portion la and a thick portion, i.e., a plane portion 1 b. Also, a plurality of pedestal type protrusions 11 having a height of about 5 to 10 μm are formed in the recess portion 1 a. Then, the photoresist pattern layer 402′ is removed.
  • Next, referring to FIG. 6G, in the same way as in FIG. 4G, the [0055] plane portion 1 b of the metal plate 1 is etched to form a landpattern 10.
  • Next, referring to FIG. 6H, in the same way in FIG. 4H, a pressing process using metal molds is performed upon the [0056] recess portion 1 a of the metal plate 1, to form a recess therein. In this case, one of the metal molds abutting the protrusions It is adjusted so that the clearance theretween is about several μm.
  • Finally, in the same way as in the method for the first embodiment, a semiconductor chip (not shown) is mounted on the [0057] recess portion 1 a of the heat spreader 1 by a mount material layer (not shown) made of Ag paste. Then, electrodes of the semiconductor chip, the metal plate 1 and the metal pattern layer 3 are electrically connected by bonding wire (not shown) made of Au. Then the semiconductor chip is sealed by a thermosetting resin layer (not shown). Also, solder balls (not shown) as external electrodes are formed on the metal pattern layer 3. In this case, each of the solder balls 9 is connected via the metal pattern layer 3 at throughholes 2 a of the organic insulating pattern layer 2 to the land patterns 10. Thus, the package of FIG. 5 is completed.
  • Note that when the package of FIGS. 2 and 5 is mounted on a printed circuit board, the package is faced down, so that the [0058] solder balls 9 are in contact with the printed circuit board. Also, the land patterns 10 are used for testing the electrical contact of solder balls 9 to the metal pattern layer 3.
  • Although the above-described embodiments relate to a BGA type package, the present invention can be applied to other types of packages. [0059]
  • As explained hereinabove, according to the present invention, the manufacturing steps can be simplified to decrease the manufacturing cost. In addition, the reliability can be improved. [0060]

Claims (8)

1. A package comprising a metal plate including a recess portion for mounting a semiconductor chip and a plane potion for mounting a metal pattern layer,
said recess portion being thinner than said plane portion.
2. The package as set forth in claim 1, wherein said recess portion has a plurality of protrusions for facing said semiconductor chip.
3. A method for manufacturing package including a metal plate including a recess portion for mounting a semiconductor chip and a plane portion for mounting a metal pattern layer, comprising the steps of:
forming a photoresist pattern layer for covering said plane portion of said metal plate; and
etching said metal plate by using said photoresist pattern layer as a mask.
4. The method as set forth in claim 3, wherein said photoresist pattern layer has a plurality of patterns on said recess portion of said metal plate, so that a plurality of protrusions are formed on said recess portion of said metal plate.
5. A method for manufacturing a package for mounting including a metal plate including a recess portion for mounting a semiconductor chip and a plane portion for mounting a metal pattern layer, comprising the steps of:
forming an insulating layer on a metal plate;
forming a first metal layer on said insulating layer;
forming a first photoresist pattern layer on said first metal layer above said plane portion of said metal plate;
etching said first metal layer by using said first photoresist pattern layer as a mask;
removing said first photoresist pattern layer after said first metal layer is etched;
etching said insulating layer by using said first metal layer as a mask after said first photoresist pattern layer is removed;
forming a second metal layer on said metal plate and said first metal layer after said insulating layer is etched; and
forming a second photoresist pattern layer on said second metal layer above said plane portion of said metal plate;
etching said second metal layer and said recess portion of said metal plate by using said second photoresist pattern.
6. The method as set forth in claim 5, wherein said second photoresist pattern layer has a plurality of patterns on said recess portion of said metal layer.
7. The method as set forth in claim 5, wherein said first photoresist pattern layer has a throughhole on said plane portion of said metal plate.
8. The method as set forth in claim 5, wherein said second metal layer forming step forms said second metal layer by using a plating process.
US10/102,901 1998-04-17 2002-03-22 Package for semiconductor chip having thin recess portion and thick plane portion Abandoned US20020096750A1 (en)

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US10/102,901 US20020096750A1 (en) 1998-04-17 2002-03-22 Package for semiconductor chip having thin recess portion and thick plane portion

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US20070007644A1 (en) * 2000-12-22 2007-01-11 Broadcom Corporation Ball grid array package enhanced with a thermal and electrical connector
US20070045824A1 (en) * 2000-12-22 2007-03-01 Broadcom Corporation Methods of making a die-up ball grid array package with printed circuit board attachable heat spreader
US7893546B2 (en) 2000-12-22 2011-02-22 Broadcom Corporation Ball grid array package enhanced with a thermal and electrical connector
US20110140272A1 (en) * 2000-12-22 2011-06-16 Broadcom Corporation Ball Grid Array Package Enhanced With a Thermal and Electrical Connector
US8310067B2 (en) 2000-12-22 2012-11-13 Broadcom Corporation Ball grid array package enhanced with a thermal and electrical connector
US20030146509A1 (en) * 2002-02-01 2003-08-07 Broadcom Corporation Ball grid array package with separated stiffener layer
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US8829557B2 (en) * 2011-04-08 2014-09-09 Lg Innotek Co., Ltd. Light emitting device module and lighting system including the same

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US6379996B1 (en) 2002-04-30
JP3097653B2 (en) 2000-10-10
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KR19990083251A (en) 1999-11-25

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