WO2022041010A1 - Chip packaging structure and electronic device - Google Patents

Abstract

The embodiments of the present application relate to the technical field of chip packaging and provide a chip packaging structure and an electronic device, which are used to improve the reliability of thermal contact between a heat conduction interface material and a chip as well as a heat dissipation cover. The chip packaging structure comprises a packaging substrate, at least one chip, at least one internal heat conduction interface layer, and a heat dissipation cover. The heat dissipation cover comprises an upper cover and a plurality of sidewalls. The upper cover comprises at least one boss structure and a first connecting structure. A boss structure contacts at least one internal heat conduction interface layer and is connected to a sidewall by means of the first connecting structure. The maximum thickness of the boss structure is greater than the maximum thickness of the first connecting structure. Furthermore, the boss structure is away from the surface of the chip and protrudes from the surface of the first connecting structure away from the chip. The boss structure can reduce the gap between the heat dissipation cover and a heat dissipation device, such that the heat dissipation device can effectively press the boss structure to reduce the probability of delamination occurring between the internal heat conduction interface layer and the chip(s).

Description

A chip packaging structure and electronic equipment technical field

The present application relates to the technical field of chip packaging, and in particular, to a chip packaging structure and an electronic device.

Background technique

With the continuous development of semiconductor technology, electronic devices are developing in the direction of multi-function, and chip bandwidth and computing power are continuously improved, which makes the package size of the chip larger and larger. Based on this, the chip will experience large temperature changes during packaging, installing heat sinks and working, so that the larger package substrate has a coefficient of thermal expansion (CTE) due to the coefficient of thermal expansion (CTE) between the materials of different layers inside. ) is different, and warpage deformation occurs. In this way, in the operating temperature range, the above-mentioned warping phenomenon will increase the probability of separation between the thermal interface material (TIM) on the chip surface and the chip, and reduce the thermal conductivity between the thermal interface material and the chip and the heat dissipation cover, respectively. Contact reliability, resulting in reduced heat dissipation.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a chip packaging structure and an electronic device, which are used to improve the thermal contact reliability between the thermally conductive interface material, the chip, and the heat dissipation cover, respectively.

To achieve the above object, the application adopts the following technical solutions:

In one aspect of the embodiments of the present application, a chip packaging structure is provided. The chip package structure includes a package substrate, at least one chip, at least one inner thermal interface layer and a heat dissipation cover. Wherein, the package substrate has a first surface. The chip is disposed on the first surface of the package substrate. The at least one inner thermal interface layer respectively covers the surface of the at least one chip on the side away from the package substrate. The heat dissipation cover includes an upper cover and a plurality of side walls. A plurality of side walls are arranged end to end in sequence around the circumference of the upper cover, and are connected with the first surface. An accommodating cavity for accommodating at least one chip is formed between the heat dissipation cover and the package substrate. Wherein, the upper cover includes at least one boss structure and a first engaging structure. Each of the above at least one boss structure is in contact with at least one of the above-mentioned inner thermally conductive interface layers. Moreover, each of the at least one boss structure is connected to the side wall through the first connecting structure. The maximum thickness D1_max of the boss structure is greater than the maximum thickness D2_max of the first connecting structure, and the boss structure is away from the surface of the chip and protrudes from the surface of the first connecting structure away from the chip. In the embodiments of the present application, the direction of the thickness is perpendicular to the direction of the first surface. Based on this, during the service process of the chip package structure, the package substrate is warped due to the temperature increase. The warping phenomenon tends to increase the gap between the heat dissipation cover and the heat dissipation device. But because the heat dissipation cover has a boss structure. The maximum thickness D1_max of the boss structure is greater than the maximum thickness D2_max of the first connecting structure, and the boss structure is far away from the surface of the chip and protrudes from the surface of the first connecting structure far away from the chip. Therefore, the above boss structure can reduce the heat dissipation cover. clearance from the heat sink. In this way, the gap between the heat dissipation cover and the heat dissipation device can be prevented from being greatly changed due to the deformation of the external thermal interface layer, so that the heat dissipation device fixed on the circuit board can still be effectively pressed against the boss structure. It can reduce the probability of delamination between the cured internal thermal interface layer and the chip, and improve the thermal contact reliability between the internal thermal interface layer and the chip and the heat dissipation cover, thereby reducing the high temperature power failure of the chip packaging structure. the probability of the phenomenon.

Optionally, the boss structure is close to the surface of the chip, and protrudes from the surface of the first connecting structure close to the chip. In this way, both the upper and lower surfaces of the boss structure protrude from the first connecting structure, which is beneficial to increase the thickness and rigidity of the boss structure, so that the heat dissipation device can more effectively apply pressure to the boss structure in the heat dissipation cover. pressure, reducing the probability of delamination of the inner thermal interface layer.

Optionally, the surface of the boss structure close to the chip is flush with the surface of the first connecting structure close to the chip. In this way, the surface of the upper cover in the heat dissipation cover close to the chip can have a higher flatness, so as to achieve the purpose of simplifying the structure of the mold for manufacturing the heat dissipation cover.

Optionally, along the direction from the boss structure to the side wall, the thickness of the first connecting structure gradually decreases. In this way, the rigidity of the end of the first connecting structure close to the side wall can be reduced, so that when the heat dissipation device presses the heat dissipation cover, the end of the first connecting structure close to the side wall is easily deformed. As a result, when the heat dissipation device presses the heat dissipation cover, the pressure is more concentrated on the boss structure with greater thickness and rigidity, and then transmitted to the chip through the boss structure in the heat dissipation cover, reducing the appearance of the internal thermal interface layer. probability of layers.

Optionally, the surface of the first connecting structure close to the chip is flat. In this case, in order to ensure that the thickness of the first connecting structure gradually decreases along the direction from the boss structure to the sidewall, the first connecting structure is close to the surface of the chip. Bevel or arc surface. Alternatively, the surface of the first connecting structure away from the chip is flat. In this case, in order to ensure that the thickness of the first connecting structure is gradually reduced along the direction from the boss structure to the sidewall, the surface of the first connecting structure away from the chip is an inclined surface or a circular arc surface.

Optionally, the side surface of the side wall away from the packaging substrate is the upper reference surface, and the surface of the inner thermal interface layer away from the packaging substrate is the lower reference surface. There is a reference thickness D0 between the upper reference plane and the lower reference plane. The minimum thickness D2_min of the first connecting structure is smaller than the reference thickness D0. In this way, the purpose of reducing the rigidity of the first connecting structure can be achieved by reducing the thickness of the first connecting structure. Therefore, when the heat dissipation device presses the heat dissipation cover, the pressure exerted by the heat dissipation device on the heat dissipation cover can be more concentrated on the boss structure, thereby reducing the probability of delamination of the inner thermal interface layer.

Optionally, 20%×D0≤D2_min≤80%×D0. When the minimum thickness D2_min of the first connecting structure is less than 20%×D0, the thickness of the first connecting structure 311 is too thin, so that the rigidity of the first connecting structure is too small, which reduces the resistance of the heat dissipation cover to the warping of the package substrate 102 control ability. In addition, when the minimum thickness D2_min of the first connecting structure is greater than 80%×D0, the thickness of the first connecting structure is too large and the rigidity is too strong, so that when the heat dissipation device presses the heat dissipation cover, it is not conducive to the heat dissipation device to the heat dissipation cover. The applied pressure is transmitted to the chip.

Optionally, there is a maximum distance L_max between the surface of the boss structure away from the chip and the upper reference surface. L_max<D0. In this way, the part of the boss structure located in the accommodating cavity, that is, the part of the boss structure where the reference thickness D0 is located, can be made thicker, while the part of the boss structure located outside the accommodating cavity, that is, the largest part of the boss structure The thickness of the part where the distance L_max is located is smaller. Therefore, when the maximum thickness D1_max of the boss structure meets the design requirements, the maximum distance L_max of the boss structure does not need to be too large, which is beneficial to improve the filling degree of the external thermal interface layer between the heat dissipation device and the heat dissipation cover 103 .

Optional, 0.01mm≤L_max≤0.2mm. When the maximum distance L_max is less than 0.01mm, the protruding degree of the boss structure is small, the effect of the boss structure on reducing the distance between the heat dissipation cover and the heat dissipation device is not obvious, and it cannot effectively improve the pressure of the heat dissipation device on the boss structure. pressure effect. When L_max is greater than 0.02mm, the protruding size of the boss structure is too large, so that the gap between the boss structure and the heat sink is too small, and the effective coverage area of the outer thermal interface layer on the upper surface of the heat dissipation cover is small, thereby reducing the The filling amount of the outer thermal interface layer between the heat dissipation device and the heat dissipation cover is determined. In addition, the thickness of the outer thermally conductive interface layer cannot absorb the thickness of the boss structure well, so that the contact flatness with the surface of the heat dissipation device facing the package substrate is reduced.

Optionally, a surface of the boss structure away from the chip is a first arc surface, and a portion of the surface of the first connecting structure away from the chip that is close to the first arc surface is a second arc surface. Wherein, the curvature of the second arc surface is the same as that of the first arc surface, and the second arc surface is connected with the first arc surface. In addition, the vertical projection of the chip corresponding to the boss structure on the first surface is located, and the first arc surface and the second arc surface are within the range of the vertical projection of the first surface. In this way, not only the boss structure in the upper cover is raised away from the surface of the chip, but also the surface of the first connecting structure away from the chip will be raised at the position of the second arc surface, so that the distance between the upper cover and the upper cover can be appropriately increased. The size of the raised portion of the chip's surface. Therefore, when the pressure applied by the heat dissipation device to the heat dissipation cover, the pressure can be more effectively applied to the pressure on the raised portion of the upper cover and transmitted to the chip, so that the thermal interface layer and the chip are more closely attached. On this basis, the vertical projection of the side of the second arc surface away from the first arc surface on the first surface has a first contour. The vertical projection of the chip corresponding to the boss structure on the first surface has a second contour. Wherein, the maximum distance Hmax between the first contour and the second contour satisfies: Hmax≤2mm. When Hmax>2mm, the size of the raised part of the surface of the upper cover away from the chip is too large, so that the gap between the upper cover and the heat sink is too small, and the external thermal interface layer can only cover the area where the boss structure is located in the upper cover. Therefore, the filling amount of the outer thermal interface layer between the heat dissipation device and the heat dissipation cover is reduced.

Optionally, at least a part of the surface of the boss structure away from the chip is a third arc surface. The vertical projection of the third arc surface on the first surface is located within the range of the vertical projection of the chip corresponding to the boss structure on the first surface. On this basis, the vertical projection of the third arc surface on the first surface has a third contour. The vertical projection of the chip corresponding to the boss structure on the first surface has a second contour. Wherein, the maximum distance Hmax between the third contour and the second contour satisfies: Hmax≤2mm. When Hmax>2mm, the size of the boss structure is too small. When the heat dissipation device exerts pressure on the heat dissipation cover, the area of the active surface of the heat dissipation cover acting on the chip is too small, which is not conducive to the heat dissipation device to effectively apply pressure to the chip. .

Optionally, the surface of the boss structure away from the chip is the first arc surface. The vertical projection of the first arc surface on the first surface completely overlaps the vertical projection of the chip corresponding to the boss structure on the first surface. In this way, the boss structure can completely cover the chip, so that when the heat dissipation device presses the heat dissipation cover, the force acting on the boss structure can be more effectively transmitted to the chip.

Optionally, the vertical projection of the contact surface between the boss structure and the inner thermal conductive interface layer on the first surface completely overlaps with the vertical projection of the chip connected to the boss structure on the first surface. In this way, the contact surface between the boss structure and the inner thermal interface layer can completely cover the chip, so that when the heat dissipation device presses the heat dissipation cover, the force acting on the boss structure can be more effectively transmitted to the chip.

Optionally, the upper cover further includes at least one first groove, and the first groove is opened on one side surface of the first connecting structure close to the chip. The first groove is located at one end of the first engaging structure away from the boss structure. In this way, by arranging the first groove at the end of the first connecting structure away from the boss structure, the rigidity of the first connecting structure close to the side wall can be further reduced, which is beneficial to concentrate the pressure exerted by the heat sink on the heat dissipation cover. Act on the boss structure.

Optionally, the first groove is an annular groove surrounding the circumference of at least one chip, so that the rigidity of the first engaging structures located at the periphery of the boss structure is reduced.

Optionally, the depth S1 of the first groove satisfies: 20%×D2_max≤S1≤80%×D2_max; the groove width L1 of the first groove satisfies: 0.1mm≤L1≤20mm. When the depth S1 of the first groove is less than 20%×D2_max and the width L1 is less than 0.1 mm, the requirements for the manufacturing accuracy of the first groove are high, which is not conducive to reducing the manufacturing cost. In addition, the size of the first groove is too small, and the effect of reducing the rigidity of the first connecting structure is not obvious. In addition, when the depth S1 of the first groove is greater than 80%×D2_max and the width L1 is greater than 20 mm, the size of the first groove is too large, which results in the first connecting structure being too small, reducing the effect of the heat dissipation cover on the warping of the package substrate. control ability.

Optionally, the at least one chip includes a first chip and a second chip. The at least one inner thermally conductive interface layer includes a first inner thermally conductive interface layer covering the first chip and a second inner thermally conductive interface layer covering the second chip. The surface of the first inner thermal interface layer away from the package substrate is flush with the surface of the second inner thermal interface layer away from the package substrate. In addition, the at least one boss structure includes a first boss structure and a second boss structure, the first boss structure is in contact with the first inner thermally conductive interface layer, and the second boss structure is in contact with the second inner thermally conductive interface layer . The upper cover further includes a second engaging structure, the second engaging structure is located between the first boss structure and the second boss structure, and is connected with the first boss structure and the second boss structure. In this case, the above-mentioned chip package structure is a multi-chip package structure.

Optionally, the upper cover further includes at least one second groove, and the second groove is opened on a side surface of the second connecting structure close to the package substrate. The setting method of the size of the second groove may be the same as the setting method of the first groove, which will not be repeated here. In addition, in the case where the above-mentioned packaging substrate is a redistribution layer, the packaging substrate is easily deformed in the process of temperature change. At this time, when the second groove and the first groove on the upper cover of the heat dissipation cover can weaken the rigidity of the upper cover, so that when the package substrate is deformed, there is a certain gap between the movement of the package substrate and the movement of the heat dissipation cover. The decoupling effect reduces the restraint when the chip moves with the package substrate. Thus, cracking of the molding layer between two adjacent chips can be reduced.

Optionally, the at least one chip includes a first chip and a second chip. The at least one inner thermally conductive interface layer includes a first inner thermally conductive interface layer covering the first chip and a second inner thermally conductive interface layer covering the second chip. The surface of the first inner thermal interface layer away from the package substrate is flush with the surface of the second inner thermal interface layer away from the package substrate. A boss structure is in contact with the first inner thermally conductive interface layer and the second inner thermally conductive interface layer. In this case, the above-mentioned chip package structure is a multi-chip package structure. When the heat dissipation device presses the heat dissipation cover, the pressure can be transmitted to the first chip and the second chip through the same boss structure, so that the structure of the heat dissipation cover can be simplified.

In another aspect of the embodiments of the present application, an electronic device is provided, including a heat dissipation device, an external thermally conductive interface layer, a circuit board, and any one of the above-mentioned chip packaging structures disposed on the circuit board. The outer thermal conductive interface layer is located between the heat dissipation device and the heat dissipation cover in the chip package structure, and is connected with the heat dissipation device and the heat dissipation cover. The heat sink is also connected to the circuit board. The electronic device has the same technical effect as the chip packaging structure provided by the foregoing embodiments, and details are not described herein again.

Description of drawings

1 is a schematic structural diagram of a part of an electronic device provided by an embodiment of the present application;

Fig. 2a is a kind of structural schematic diagram of the chip packaging structure in Fig. 1;

FIG. 2b is a schematic structural diagram of the side wall of the heat dissipation cover in FIG. 2a;

Fig. 3a is another structural schematic diagram of the chip packaging structure in Fig. 1;

Fig. 3b is another structural schematic diagram of the chip packaging structure in Fig. 1;

FIG. 4 is a schematic diagram of a warping of the chip package structure provided by the embodiment of the present application;

FIG. 5 is a schematic structural diagram of a chip packaging structure connected to a heat sink provided by an embodiment of the present application;

FIG. 6a is another structural schematic diagram of the chip packaging structure in FIG. 1;

Fig. 6b is another structural schematic diagram of the chip packaging structure in Fig. 1;

FIG. 7a is another schematic structural diagram of the chip packaging structure in FIG. 1;

FIG. 7b is another schematic structural diagram of the chip packaging structure in FIG. 1;

FIG. 8 is another structural schematic diagram of the chip packaging structure in FIG. 1;

Fig. 9a is another structural schematic diagram of the chip packaging structure in Fig. 1;

FIG. 9b is a schematic top view outline of the boss structure and the chip in FIG. 9a;

Fig. 9c is another structural schematic diagram of the chip packaging structure in Fig. 1;

FIG. 9d is a schematic top view outline of the boss structure and the chip in FIG. 9c;

Fig. 9e is another structural schematic diagram of the chip packaging structure in Fig. 1;

FIG. 10 is another structural schematic diagram of the chip packaging structure in FIG. 1;

11a is a schematic structural diagram of a heat dissipation cover provided by an embodiment of the present application;

11b is a schematic structural diagram of another heat dissipation cover provided by an embodiment of the present application;

12a is a schematic diagram of a multi-chip packaged chip package structure provided by an embodiment of the present application;

FIG. 12b is a schematic diagram of another multi-chip packaged chip package structure according to an embodiment of the present application;

12c is a schematic diagram of another multi-chip packaged chip package structure provided by an embodiment of the present application;

FIG. 13 is a schematic diagram of another multi-chip packaged chip package structure according to an embodiment of the present application.

Reference number:

01-electronic equipment; 10-chip package structure; 11-heat dissipation device; 12-PCB; 13-solder ball array; 101-chip; 102-package substrate; 103-heat dissipation cover; 110-inner thermal interface layer; 120-outer Thermal interface layer; 20-accommodating cavity; 31-upper cover; 310-boss structure; 311-first connecting structure; 32-side wall; 40-adhesive layer; 312-first groove; 313-second connecting 314-the second groove; 101a-the first chip; 101b-the second chip; 110a-the first inner thermal interface layer; 110b-the second inner thermal interface layer; 310a-the first boss structure; 310b-the first Two boss structure; 400 - molding material.

detailed description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

Hereinafter, the terms "first", "second", etc. are only used for descriptive purposes, and should not be understood as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as "first", "second", etc., may expressly or implicitly include one or more of that feature.

In addition, in this application, orientation terms such as "upper" and "lower" are defined relative to the orientation in which the components in the drawings are schematically placed. It should be understood that these directional terms are relative concepts, and they are used for relative In the description and clarification of the drawings, it may change correspondingly according to the change of the orientation in which the components are placed in the drawings.

In this application, unless otherwise expressly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" may be a fixed connection, a detachable connection, or an integrated body; it may be directly connected, or Can be indirectly connected through an intermediary. In addition, the term "electrical connection" may be a direct electrical connection or an indirect electrical connection through an intermediate medium.

Embodiments of the present application provide an electronic device. The electronic device can include mobile phone (mobile phone), tablet computer (pad), smart wearable products (for example, smart watch, smart bracelet), virtual reality (virtual reality, VR) terminal equipment, augmented reality (augmented reality AR) Terminal equipment and other equipment. The above-mentioned electronic devices may also be electronic devices such as electric vehicles, small household appliances (such as soymilk machines, sweeping robots), unmanned aerial vehicles, or electronic devices applied in a pan-network. The embodiments of the present application do not specifically limit the specific form of the above electronic device.

The above-mentioned electronic device 01, as shown in FIG. 1 , may include a chip package structure 10 and a printed circuit board (PCB) 12 . The chip package structure 10 may be electrically connected to the PCB 12 through a ball grid array (BGA) 13 or a land grid array (LGA).

The above-mentioned chip package structure 10 may include at least one chip 101 and a package substrate 102 . The package substrate 102 has a first surface A1 and a second surface A2 disposed opposite to each other. The chip 101 is disposed on the first surface A1 of the package substrate 102 , and the solder ball array 13 is disposed on the second surface A2 of the package substrate 102 . The chip 101 may implement signal transmission through the packaging substrate 102 , the solder ball array 13 and other chips or chip packaging structures on the PCB 12 .

The above-mentioned chip 101 will generate heat during operation. In order to diffuse the above-mentioned heat, the performance of the chip 101 is avoided to be affected. As shown in FIG. 1 , the chip package structure 10 further includes at least one inner thermal interface layer 110 and a heat dissipation lid 103 . The at least one inner thermal interface layer 110 respectively covers the surface of the at least one chip 101 on the side away from the package substrate 102 . The heat dissipation cover 103 is connected with the inner thermal conductive interface layer 110 and the package substrate 102 , and a accommodating cavity 20 for accommodating the at least one chip 101 is formed between the heat dissipation cover 103 and the package substrate 102 .

It should be noted that, FIG. 1 is described by taking an example in which one chip 101 is packaged in the chip packaging structure 10 . In other embodiments of the present application, the above-mentioned chip package structure 10 may also be a multi-chip package structure (multi chip module, MCM). In this case, the above-mentioned chip packaging structure 10 may be packaged with at least two chips 101 . At this time, a surface of each chip 101 on one side away from the packaging substrate 102 may be covered with an inner thermal interface layer 110 .

In some embodiments of the present application, the above-mentioned chip 101 may be a single die. Alternatively, in other embodiments, the above-mentioned chip 101 may be a structure in which a bare chip is disposed on an interposer using a chip on wafer on substrate (COWOS) technology including a silicon substrate. Alternatively, in other embodiments, the above-mentioned chip 101 may be a structure in which a bare chip is disposed on a redistribution layer (RDL) using a fan out package (FOP) technology.

In addition, as shown in FIG. 1 , the above-mentioned electronic device 01 further includes a heat dissipation device 11 and an outer thermally conductive interface layer 120 . The outer thermal interface layer 120 is connected with the heat dissipation device 11 and the heat dissipation cover 103 in the chip package structure 10 . The above-mentioned heat dissipation device 11 can also be connected to the PCB 12 through screws.

In some embodiments of the present application, the above-mentioned heat dissipation device 11 may be a radiator or a liquid cooling plate. In this case, the heat generated by the chip 101 during operation as a heat source can be transferred to the heat dissipation cover 103 as a heat dissipation device through the inner thermal conductive interface layer 110 . The inner thermal interface layer 110 can reduce the contact thermal resistance between the chip 101 and the heat dissipation cover 103 , so as to improve the heat dissipation performance of the heat dissipation cover 103 . Next, the heat dissipation cover 103 is used as a heat source, and the heat on the heat dissipation cover 103 can be transferred to the heat dissipation device 11 as a heat dissipation device through the outer thermal conductive interface layer 120 to dissipate heat through the heat dissipation device 11 . The outer thermal interface layer 120 is used to reduce the contact thermal resistance between the heat dissipation device 11 and the heat dissipation cover 103 , so as to improve the heat dissipation performance of the heat dissipation device 11 .

Based on this, the materials of the inner thermally conductive interface layer 110 and the outer thermally conductive interface layer 120 may include thermally conductive silica gel. It can be seen from the above that the thermal contact resistance generated between the surface of the heat source and the heat sink can be reduced by the above-mentioned inner thermal interface layer 110 and outer thermal interface layer 120 . In addition, the inner thermal interface layer 110 and the outer thermal interface layer 120 can also well fill the gap between the heat source and the heat sink, and squeeze out the air between the above two, so as to prevent the air as a poor thermal conductor from hindering the heat The transfer between the heat source and the heat sink. Moreover, the inner thermal interface layer 110 and the outer thermal interface layer 120 can also make the contact between the heat source and the heat sink more sufficient, and have the function of bonding the heat source and the heat sink. In addition, the material constituting the heat dissipation cover 103 can be a metal material with good thermal conductivity, such as copper, aluminum, and the like.

On this basis, in some embodiments of the present application, as shown in FIG. 2 a , the heat dissipation cover 103 may include an upper cover 31 and a plurality of side walls 32 . A plurality of side walls 32 are disposed around the circumference of the upper cover 31 and may be connected to the first surface A1 of the package substrate 102 through an adhesive layer 40 . The bonding position between the sidewall 32 and the package substrate 102 may be referred to as a footprint. In the case where a plurality of side walls 32 are arranged around the circumference of the upper cover 31, as shown in FIG. 2b, the plurality of side walls 32 are connected end to end to form a frame structure, and the hollow part of the frame structure is where the above-mentioned accommodating cavity 20 is located. area.

It should be noted that, the embodiment of the present application is described by taking the heat dissipation cover 103 including four side walls 32 as an example, and the frame structure formed by the four side walls 32 being connected end to end is a rectangle as an example. The present application does not limit the number of the side walls 32 in the heat dissipation cover 103 and the shape of the frame structure formed by connecting the plurality of side walls 32 end to end, which will not be repeated here.

In addition, as shown in FIG. 2 a , the above-mentioned upper cover 31 may include at least one boss structure 310 and a first engaging structure 311 . Each of the at least one boss structure 310 described above may be in contact with the at least one inner thermally conductive interface layer 110 . For example, as shown in FIG. 2 a , when the top cover 31 has a boss structure 310 and the chip package structure 10 includes an inner thermal interface layer 110 , the boss structure 310 is in contact with the inner thermal interface layer 110 . Alternatively, when the top cover 31 has a boss structure 310 and the chip package structure 10 includes a plurality of inner thermally conductive interface layers 110 , the bossed structure 310 can be in contact with the above-mentioned plurality of inner thermally conductive interface layers 110 at the same time. Alternatively, when the upper cover 31 has a plurality of boss structures 310 and the chip package structure 10 includes a plurality of inner thermally conductive interface layers 110 , each boss structure 310 in the plurality of boss structures 310 may be respectively associated with an inner thermally conductive interface layer 110 . The interface layers 110 are in contact.

Moreover, each of the at least one boss structure 310 may be connected to the side wall 32 through the first connecting structure 311 . In this case, the part of the upper cover 31 used for contacting the inner thermal interface layer 110 is the above-mentioned boss structure 310 , and the part of the upper cover 31 used to connect the boss structure 310 with the side wall 32 is the above-mentioned first connecting structure 311 .

It should be noted that, the boss structure 310 and the first connecting structure 311 in the upper cover 31 can be made of the same material and are an integral structure. In the process of manufacturing the heat dissipation cover 103 , the above-mentioned four side walls 32 , the boss structure 310 and the first connecting structure 311 in the upper cover 31 can be simultaneously prepared through the same process. In addition, since the boss structure 310 and the first connecting structure 311 are integrated structures, the following embodiments distinguish the boss structure 310 and the first connecting structure 311 for the convenience of description. In the vertical projection of a surface A1 , the portion corresponding to the vertical projection of the at least one chip 101 on the first surface A is the boss structure 310 . For example, as shown in FIG. 2a , when the upper cover 31 has a boss structure 310 and the chip package structure 10 is packaged with a chip 101 , the vertical projection of the boss structure 310 on the first surface A1 can be the same as the chip 101 . The vertical projections on the first surface A1 completely overlap. Alternatively, when the upper cover 31 has a boss structure 310 and the chip packaging structure 10 is packaged with a plurality of chips 101, the vertical projections of the above-mentioned plurality of chips 101 on the first surface A1 may all be located on the first surface A1 of the boss structure 310. within the range of the vertical projection on a surface A1. Alternatively, when the upper cover 31 has a plurality of boss structures 310 and the chip packaging structure 10 is packaged with a plurality of chips 101 , the vertical projection of each boss structure 310 on the first surface A1 may be the same as that of one chip 101 . The vertical projections on the first surface A1 completely overlap. In addition, in the vertical projection of the upper cover 31 on the first surface A, the part located outside the vertical projection of the chip 101 on the first surface A is the above-mentioned first connecting structure 311 .

In addition, the maximum thickness D1_max of the boss structure 310 is greater than the maximum thickness D2_max of the first connecting structure 311 , and the boss structure 310 is away from the surface of the chip 101 and protrudes from the surface of the first connecting structure 311 away from the chip 101 . 2a is an example for illustrating that the surface of the boss structure 310 away from the chip 101 is stepped. In other embodiments of the present application, as shown in FIG. 3 a , the surface of the boss structure 310 away from the chip 101 may be a convex arc surface in a direction away from the package substrate 102 .

It should be noted that the maximum thickness D1_max of the boss structure 310 refers to, along the direction perpendicular to the first surface A1 , the part with the largest thickness in the boss structure 310 . Similarly, the maximum thickness D2_max of the first connecting structure 311 refers to, along the direction perpendicular to the first surface A1 , the part with the largest thickness in the first connecting structure 311 .

FIG. 3 a illustrates the structure of the side wall 32 by taking the example that the side wall 32 of the heat dissipation cover 103 is perpendicular to the first surface A1 of the package substrate 102 . In other embodiments of the present application, as shown in FIG. 3 b , the sidewall 32 of the heat dissipation cover 103 may have an acute angle α with the package substrate 102 . Compared with the solution shown in FIG. 3b , in the solution shown in FIG. 3 a , since the side wall 32 is arranged perpendicular to the first surface A1 of the package substrate 102 , the distribution of the entire heat dissipation cover 103 on the package substrate 102 can be reduced. The component area is beneficial to save the component space on the package substrate 102 , so that more chips 101 or other electronic components can be arranged on the package substrate 102 .

It should be noted that, in the implementation of the present application, the thickness of any one of the thickness of the boss structure 310 and the thickness of the first connecting structure 311 is perpendicular to the direction of the first surface A1, that is, along the Y direction shown in FIG. 3a . In this case, the maximum thickness D1_max of the boss structure 310 refers to the maximum distance between the opposite upper and lower surfaces of the boss structure 310 along the Y direction. The maximum thickness D2_max of the first connecting structure 311 refers to the maximum distance between the opposite upper and lower surfaces of the first connecting structure 311 along the Y direction.

As can be seen from the above, the chip package structure 10 with the heat dissipation cover 103 can be arranged on the PCB 12, the outer thermal interface layer 120 is formed on the upper surface of the heat dissipation cover 103, and the heat dissipation device 11 is disposed on the side of the heat dissipation cover 103 away from the PCB12. on the surface. Then, the four corners of the heat dissipation device 11 are fixed on the PCB 12 by means of screw connections, such as screws.

Based on this, on the one hand, in the chip package structure 10, when the chip 101 is in service (ie, working), the package substrate 102 is warped as shown in FIG. 4 due to the temperature rise. The warpage phenomenon may cause the gap between the heat dissipation cover 103 and the heat dissipation device 11 to increase. However, since the heat dissipation cover 103 has the boss structure 310 . The maximum thickness D1_max of the boss structure 310 is greater than the maximum thickness D2_max of the first connecting structure 311 , and the boss structure 310 is far away from the surface of the chip 101 and protrudes from the surface of the first connecting structure 311 away from the chip 101 . Therefore, the above boss The structure 310 can reduce the gap between the heat dissipation cover 103 and the heat dissipation device 11 .

In this way, the gap between the heat dissipation cover 103 and the heat dissipation device 11 can be prevented from being greatly changed due to the deformation of the outer thermal interface layer 120 , so that the heat dissipation device 11 fixed on the PCB 12 can still be effectively pressed against On the boss structure 310, the probability of delamination between the cured inner thermal interface layer 110 and the chip 101 is reduced, and the thermal contact reliability between the inner thermal interface layer 110 and the chip 101 and the heat dissipation cover 103 is improved, thereby The probability of the chip package structure 10 being powered down at high temperature can be reduced.

On this basis, it can be seen from FIG. 4 that when the packaging substrate 102 in the chip packaging structure 10 is deformed, the area of the packaging substrate 102 corresponding to the center position of the chip 101 is greatly deformed, which is easy to cause internal damage. The thermally conductive interface layer 110 is easily delaminated at the portion in contact with the center position of the chip 101 . In order to solve the above problem, the portion of the boss structure 310 of the heat dissipation cover 103 having the maximum thickness D1_max can be located at the center of the chip 101 .

In this way, most of the pressure applied by the heat sink 11 to the chip 101 through the boss structure 310 can be applied to the center of the chip 101 , so as to prevent the pressure applied by the heat sink 11 to the chip 101 from being offset and reduce the internal thermal interface layer 110 The probability of occurrence of delamination at the portion in contact with the center position of the chip 101 .

On the other hand, when the upper surface of the heat dissipation cover 103 is flat, at the service temperature or higher, the surface will be concave to show a "smiley face" state, which makes it difficult for the external force to be effectively transmitted to the chip 101 through the heat dissipation cover 103 . In the embodiment of the present application, since the heat dissipation cover 103 has the above-mentioned boss structure 310 , it is better in contact with the outer thermal interface layer 120 , so that the heat dissipation device 11 can more effectively apply pressure to the chip 101 .

On the other hand, in the embodiment of the present application, the boss structure 310 is used as a part of the heat dissipation cover 103 , and the preparation of the boss structure 310 can be completed when the heat dissipation cover 103 is fabricated. The current mass production process can achieve that the tolerance of the heat dissipation cover 103 is far smaller than the machine-level tolerance of the heat dissipation component 11 . Therefore, compared with the solution in which the boss structure 310 is fabricated on the heat dissipation device 11 , the boss structure 310 is used as a part of the heat dissipation cover 103 , and the thickness of the boss structure 310 does not need to be large, which is conducive to the absorption of the external thermal interface layer 120 The thickness of the boss structure 310 can avoid that the thickness of the boss structure 310 is too large, so that the outer thermal interface layer 120 can only cover the area where the boss structure 310 is located in the upper cover 31 , thereby increasing the external surface between the heat dissipation device 11 and the heat dissipation cover 103 . The filling degree of the thermally conductive interface layer 120 .

In some embodiments of the present application, as shown in FIG. 5 , the side surface of the side wall 32 of the heat dissipation cover 103 away from the package substrate 102 can be used as the upper reference plane B1 . In order to keep the boss structure 310 away from the surface of the chip 101, the boss structure 310 protrudes from the surface of the first connecting structure 311 away from the chip 101, as shown in FIG. B1, and there is a maximum distance L_max between the surface of the boss structure 310 away from the chip 101 and the upper reference plane B1. Exemplarily, 0.01mm≤L_max≤0.2mm.

It should be noted that, in the embodiment of the present application, the side surface of the side wall 32 of the heat dissipation cover 103 away from the packaging substrate 102 can be used as the upper reference plane B1 when the side wall 32 of the heat dissipation cover 103 is at least one side of the surface away from the packaging substrate 102 When a part is flat, this part can be used as the above-mentioned upper reference plane B1.

In this case, when the maximum distance L_max is less than 0.01 mm, the protruding degree of the boss structure 310 is small, the effect of the boss structure 310 on reducing the distance between the heat dissipation cover 103 and the heat dissipation device 11 is not obvious, and cannot be effectively The pressure effect of the heat dissipation device 11 on the boss structure 310 is improved. When L_max is greater than 0.2 mm, the protruding size of the boss structure 310 is too large, so that the gap between the boss structure 310 and the heat sink 11 is too small, and the outer thermal interface layer 120 can only cover the boss structure in the upper cover 31 310 is located, thereby reducing the filling amount of the external thermal interface layer 120 between the heat dissipation device 11 and the heat dissipation cover 103 . In addition, the thickness of the outer thermal interface layer 120 (eg, 0.12 mm˜0.3 mm) cannot absorb the thickness of the boss structure 310 well, so that the contact flatness with the surface of the heat sink 11 facing the package substrate 102 is reduced.

Therefore, when the maximum distance L_max satisfies 0.01mm≤L_max≤0.2mm, the surface of the outer thermal interface layer 120 in contact with the heat dissipation device 11 can be flat, which is beneficial to improve the contact performance between the outer heat conductive interface layer 120 and the heat dissipation device 11 . In addition, the filling degree of the outer thermal interface layer 120 between the heat dissipation device 11 and the heat dissipation cover 103 can also meet the requirements, so that the temperature uniformity of the heat dissipation cover 103 and the heat dissipation device 11 can be maintained. For example, the above-mentioned maximum distance L_max may be 0.05mm, 0.06mm, 0.08mm, 0.10mm, 0.15mm.

In addition, when the surface mounted technology (SMT) process is performed, since the tolerance level of the heat dissipation cover 103 is much higher than that of the SMT nozzle, although the boss structure 310 is far away from the surface of the chip 101, it protrudes from the surface of the chip 101. The first connecting structure 311 is away from the surface of the chip 101 , but the protruding portion of the surface of the boss structure 310 away from the chip 101 can be regarded as a smooth transition in macroscopic view. In this way, the SMT nozzle can be tightly attached to the heat dissipation cover 103 when sucking the chip package structure 10 .

Hereinafter, other setting manners of the boss structure 310 will be illustrated by way of example.

In some embodiments of the present application, as shown in FIG. 6 a , the maximum thickness D1_max of the boss structure 310 is greater than the maximum thickness D2_max of the first connecting structure 311 , and the boss structure 310 is away from the surface (upper surface) of the chip 101 and protrudes The first connecting structure 311 is away from the surface of the chip 101 . In addition, the boss structure 310 is close to the surface (lower surface) of the chip 101 and protrudes from the surface of the first connecting structure 311 close to the chip 101 .

In this way, both the upper and lower surfaces of the boss structure 310 protrude from the first connecting structure 311 , which is beneficial to increase the thickness and rigidity of the boss structure 310 , so that the heat dissipation device 11 can be more effectively inserted into the heat dissipation cover 103 The boss structure 310 exerts pressure to reduce the probability of delamination of the inner thermally conductive interface layer 110 .

In addition, since the boss structure 310 is close to the surface (lower surface) of the chip 101 and protrudes from the surface of the first connecting structure 311 close to the chip 101 , when the maximum thickness D1_max of the boss structure 310 meets the design requirements, the boss structure 310 The maximum distance L_max between the surface (upper surface) far away from the chip 101 and the upper reference plane B1 may not be too large, for example, L_max=0.06mm. Therefore, the thickness of the outer thermal interface layer 120 (for example, 0.12 mm˜0.3 mm) covering the upper surface of the boss structure 310 can be well absorbed by the thickness of the boss structure 310 , which is beneficial to improve the relationship between the heat dissipation device 11 and the heat dissipation cover 103 . The filling degree of the external thermal interface layer 120 .

In addition, as shown in FIG. 6a, along the direction from the boss structure 310 to the sidewall 32 (X direction in FIG. 6a), the thickness D2 of the first connecting structure 311 gradually decreases. In this way, the rigidity of the end of the first connecting structure 311 close to the side wall 32 can be reduced, so that when the heat dissipation device 11 presses the heat dissipation cover 103 , the end of the first connecting structure 311 close to the side wall 32 is easily deformed. Therefore, when the heat dissipation device 11 presses the heat dissipation cover 103 , the first connecting structure 311 can more easily move with the downward pressing direction of the heat dissipation device 11 , so that the pressure exerted by the heat dissipation device 11 on the heat dissipation cover 103 is more concentrated on the thickness and stiffness. On the larger boss structure 310, the pressure of the heat dissipation device 11 can be more effectively transmitted to the chip structure 101 through the boss structure 310 in the heat dissipation cover 103, and the probability of delamination of the inner thermal interface layer 110 is reduced. .

It should be noted that, FIG. 6 a illustrates the structure of the side wall 32 by taking the example that the side wall 32 of the heat dissipation cover 103 is perpendicular to the package substrate 102 . In other embodiments of the present application, as shown in FIG. 6 b , the sidewall 32 of the heat dissipation cover 103 may have an acute angle α with the package substrate 102 .

In addition, in the case where the thickness D2 of the first connecting structure 311 gradually decreases along the direction from the boss structure 310 to the sidewall 32 (X direction in FIG. 6a ), FIG. 6a and FIG. 6b show that the boss structure 310 is far away from the The surface (upper surface) of the chip 101 and the surface (lower surface) close to the chip 101, and the surface (upper surface) of the first connecting structure 311 away from the chip 101 and the surface (lower surface) close to the chip 101 are protruding outward A non-planar example of .

In other embodiments of the present application, as shown in FIG. 7 a , the surface (upper surface) of the first connecting structure 311 away from the chip 101 is flat. At this time, in order to ensure the direction from the boss structure 310 to the sidewall 32 (X direction in FIG. 7 a ), the thickness D2 of the first connecting structure 311 is gradually reduced, and the first connecting structure 311 is close to the surface (the lower surface of the chip 101 ) ), which is an inclined surface or an arc surface.

Alternatively, in other embodiments of the present application, as shown in FIG. 7b , the surface (lower surface) of the first connecting structure 311 close to the chip 101 is flat. In this case, the surface (lower surface) of the boss structure 310 close to the chip 101 may be flush with the surface (lower surface) of the first connecting structure 311 close to the chip 101 . In this way, the surface of the upper cover 31 of the heat dissipation cover 103 close to the chip 101 can have a higher flatness, so as to simplify the structure of the mold for manufacturing the heat dissipation cover 103 .

In addition, in order to ensure that the thickness D2 of the first connecting structure 311 is gradually reduced along the direction from the boss structure 310 to the sidewall 32 (X direction in FIG. 7 b ), the first connecting structure 311 is far away from the surface (upper surface) of the chip 101 . , which is an inclined surface or an arc surface. In this case, when the surface (upper surface) of the boss structure 310 and the first connecting structure 311 away from the chip 101 are all arc surfaces, the surface (the upper surface) of the boss structure 310 and the first connecting structure 311 away from the chip 101 ) can have the same curvature. In this way, the structure of the mold for manufacturing the heat dissipation cover 103 can be simplified, and the manufacturing process can be simplified.

Similarly, in FIGS. 7 a and 7 b , the sidewall 32 of the heat dissipation cover 103 may have an acute angle α with the package substrate 102 , which will not be described in detail here. For the convenience of description below, the description is given by taking an example that the side wall 32 of the heat dissipation cover 103 is perpendicular to the first surface A1 of the package substrate 102 .

In addition, in the case where the thickness D2 of the first connecting structure 311 gradually decreases along the direction from the boss structure 310 to the side wall 32, in some embodiments of the present application, as shown in FIG. 8, the side wall 32 is far away from One surface (upper surface) of the package substrate 102 is the upper reference plane B1, and the side surface (upper surface) of the inner thermal interface layer 110 away from the package substrate 102 is the lower reference plane B2. Based on this, there is a reference thickness D0 between the upper reference plane B1 and the lower reference plane B2. The minimum thickness D2_min of the first engagement structure 311 may be smaller than the reference thickness D0.

In this way, the purpose of reducing the rigidity of the first connecting structure 311 can be achieved by reducing the thickness of the first connecting structure 311 . Therefore, when the heat dissipation device 11 presses the heat dissipation cover 103, the first connecting structure 311 can more easily move with the pressing direction of the heat dissipation device 11, so that the pressure exerted by the heat dissipation device 11 on the heat dissipation cover 103 is more concentrated on the boss structure. In step 310, the probability of delamination of the inner thermally conductive interface layer 110 is reduced.

It should be noted that, as can be seen from the above, the thickness D2 of the first connecting structure 311 gradually decreases along the direction from the boss structure 310 to the side wall 32 , so the minimum thickness D2_min of the first connecting structure 311 is the first connecting structure 311 The thickness of one end near side wall 32 (or the aforementioned footprint).

For example, the minimum thickness D2_min of the first connecting structure 311 and the reference thickness D0 may satisfy: 20%×D0≤D2_min≤80%×D0. For example, the minimum thickness D2_min of the first bridging structure 311 may be 25%×D0, 30%×D0, 35%×D0, 40%×D0, 45%×D0, 50%×D0, 60%×D0, or 70% ×D0. Wherein, in some embodiments of the present application, the above-mentioned reference thickness D0 may be in the range of 1 mm˜2 mm. For example, when D0=1mm, the range of the minimum thickness D2_min is 0.2mm≤D2_min≤0.8mm.

When the minimum thickness D2_min of the first connecting structure 311 is less than 20%×D0, the thickness of the first connecting structure 311 is too thin, so that the rigidity of the first connecting structure 311 is too small, which reduces the impact of the heat dissipation cover 103 on the package substrate 102 Warp control. In addition, when the minimum thickness D2_min of the first connecting structure 311 is greater than 80%×D0, the thickness of the first connecting structure 311 is too large and the rigidity is too strong. 311 is not easy to move with the downward pressing direction of the heat dissipation device 11 , so that it is not conducive to concentrate the pressure exerted by the heat dissipation device 11 on the heat dissipation cover 103 on the boss structure 310 .

On this basis, it can be seen from the above that there is a maximum distance L_max between the surface (upper surface) of the boss structure 310 away from the chip 101 and the upper reference plane B1 . In some embodiments of the present application, L_max<D0. In this way, the part of the boss structure 310 located in the accommodating cavity 20, that is, the part of the boss structure 310 where the reference thickness D0 is located, can be made thicker, while the part of the boss structure 310 located outside the accommodating cavity 20, that is The thickness of the portion of the boss structure 310 where the maximum distance L_max is located is relatively small. Therefore, when the maximum thickness D1_max of the boss structure 310 meets the design requirements, the maximum distance L_max of the boss structure 310 does not need to be too large, which is beneficial to improve the filling degree of the external thermal interface layer 120 between the heat dissipation device 11 and the heat dissipation cover 103 .

In addition, in some embodiments of the present application, as shown in FIG. 9a, the surface of the boss structure 310 away from the chip 101 is the first arc surface S1, and the surface of the first connecting structure 311 away from the chip 101 is close to the first arc surface The part of S1 is the second arc surface S2. The curvature of the second arc surface S1 and the first arc surface S2 are the same, and the second arc surface S2 is connected with the first arc surface S1. In addition, the vertical projection of the chip 101 corresponding to the boss structure 310 on the first surface A1 is located, and the first arc surface S1 and the second arc surface S2 are within the range of the vertical projection of the first surface A1. In this way, not only the boss structure 310 is raised from the surface of the upper cover 31 away from the chip 101 , but the surface of the first connecting structure 311 away from the chip 101 will also be raised at the position of the second arc surface S2 , so that it can be The size of the raised portion of the surface of the upper cover 31 away from the chip 101 is appropriately increased. Therefore, when the heat dissipation device 11 exerts the pressure on the heat dissipation cover 103, the pressure can be more effectively applied to the pressure of the convex portion of the upper cover 31 and transferred to the chip 101, so that the thermal interface layer 110 and the chip 101 can be more closely attached .

On this basis, the vertical projection of the side of the second arc surface S2 away from the first arc surface S1 on the first surface A1 has a first contour T1 as shown in Figure 9b (a top view taken along the arrow Y direction in Figure 9a ) . The vertical projection of the chip 101 corresponding to the boss structure 310 on the first surface A1 has a second contour T2. Wherein, the maximum distance Hmax between the first contour T1 and the second contour T2 satisfies: Hmax≤2mm. When Hmax>2mm, the size of the convex part of the upper cover 31 away from the chip 101 is too large, so that the gap between the upper cover 31 and the heat sink 11 is too small, and the outer thermal interface layer 120 can only cover the convex part of the upper cover 31 The area where the mesa structure 310 is located reduces the filling amount of the external thermal interface layer 120 between the heat dissipation device 11 and the heat dissipation cover 103 .

It should be noted that, in the embodiment of the present application, the chip 101 corresponding to the boss structure 310 refers to the chip 101 connected to the boss structure 310 through the inner thermal interface layer 110 .

Alternatively, in other embodiments of the present application, as shown in FIG. 9 c , at least a part of the surface of the boss structure 310 away from the chip 101 is the third arc surface S3 . The vertical projection of the third arc surface S3 on the first surface A1 is located within the range of the vertical projection of the first surface A1 of the chip 101 corresponding to the boss structure 310 . On this basis, the vertical projection of the third arc surface S3 on the first surface A1 has a third contour T3 as shown in FIG. 9d (a top view taken along the arrow Y direction in FIG. 9c ). The vertical projection of the chip 101 corresponding to the boss structure 310 on the first surface A1 has a second contour T2. Wherein, the maximum distance Hmax between the third contour T3 and the second contour T2 satisfies: Hmax≤2mm. When Hmax>2mm, the size of the boss structure 310 is too small. When the heat dissipation device 11 exerts pressure on the heat dissipation cover 103, the area of the working surface of the heat dissipation cover 103 acting on the chip 101 is too small, which is not conducive to the effective effect of the heat dissipation device 11. of applying pressure to the chip 101 .

Alternatively, in other embodiments of the present application, as shown in FIG. 9e , the surface of the boss structure 310 away from the chip 101 is the first arc surface S1 . The vertical projection of the first arc surface S1 on the first surface A1 completely overlaps with the vertical projection of the chip 101 corresponding to the boss structure 310 on the first surface A1. In this way, the boss structure 310 can completely cover the chip 101 , so that when the heat dissipation device 11 presses the heat dissipation cover 103 , the force acting on the boss structure 310 can be more effectively transmitted to the chip 101 .

In addition, in order to further reduce the thickness D2 of the first engaging structure 311 in the upper cover 31 of the heat dissipation cover 103 , as shown in FIG. 10 , the upper cover 31 may further include at least one first groove 312 . The first groove 312 is formed on a side surface of the first connecting structure 311 close to the chip 101 . The first groove 312 may be located at one end of the first engaging structure 311 away from the boss structure 310 . In this way, by arranging the first groove 312 at the end of the first engaging structure 311 away from the boss structure 310, the rigidity of the first engaging structure 311 close to the side wall 32 (or the above-mentioned footprint) can be further reduced, which is beneficial to the The pressure exerted by the heat dissipation device 11 on the heat dissipation cover 103 is concentrated on the boss structure 310 .

In some embodiments of the present application, as shown in FIG. 10 , the depth S1 of the first groove 312 may satisfy: 20%×D2_max≤S1≤80%×D2_max. The groove width L1 of the first groove 312 may satisfy: 0.1 mm≤L1≤20 mm. When the depth S1 of the first groove 312 is less than 20%×D2_max (for example, when the maximum thickness D2_max of the first engaging structure 311 is 1 mm, S1 is less than 0.2 mm) and the width L1 is less than 0.1 mm, the first groove 312 The requirements of the production accuracy are relatively high, which is not conducive to reducing the production cost. In addition, the size of the first groove 312 is too small, and the effect of reducing the rigidity of the first engaging structure 311 is not obvious. In addition, when the depth S1 of the first groove 312 is greater than 80%×D2_max (for example, when the maximum thickness D2_max of the first engaging structure 311 is 2.7 mm, S1 is greater than 2.1 mm), and when the width L1 is greater than 20 mm, the first groove The size of 312 is too large, so that the first connecting structure 311 is too small, which reduces the ability of the heat dissipation cover 103 to control the warpage of the package substrate 102 .

For example, the depth S1 of the first groove 312 may be 0.5 mm, 0.8 mm, 1.0 mm or 1.5 mm. The width L1 of the first groove 312 may be 0.5 mm, 1 mm, 2 mm, 4 mm, 8 mm, 15 mm or 18 mm. In this way, on the basis of reducing the rigidity of the first connecting structure 311 , it is possible to avoid affecting the ability of the heat dissipation cover 103 to control the warpage of the package substrate 102 .

On this basis, in some embodiments of the present application, as shown in FIG. 11a (the side surface of the heat dissipation cover 103 close to the chip 101 ), the above-mentioned first groove 312 may surround at least one chip 101 (the chip in FIG. 11a ). The position is indicated by a dotted line) around the annular groove, so that the rigidity of the first connecting structure located around the boss structure 310 is reduced to some extent.

Alternatively, in other embodiments of the present application, taking the chip 101 as a rectangle as an example, the upper cover 31 may include four first grooves as shown in FIG. are the first groove 312a, the first groove 312b, the first groove 312c and the first groove 312d, respectively. The first groove 312a and the first groove 312b are located on opposite sides of the chip 101, respectively. The first groove 312c and the first groove 312d are respectively located on two opposite sides of the chip 101 . In this case, the bottom of any one of the first groove 312 a , the first groove 312 b , the first groove 312 c , and the first groove 312 d can penetrate through the first engaging structure 311 .

The above description is based on an example where one chip 101 is provided in one chip package structure 10 , and the following describes the structure of the heat dissipation cover 103 by using an example where two chips are provided in one chip package structure 10 .

In some embodiments of the present application, as shown in FIG. 12a, at least one chip in the chip package structure 10 may include a first chip 101a and a second chip 101b. In this case, in order to make the surface of each chip 101a on the side away from the packaging substrate 102 covered with an inner thermally conductive interface layer, the at least one inner thermally conductive interface layer may include a first inner thermally conductive interface layer 110a covering the first chip 101a and The second inner thermal interface layer 110b covers the second chip 101b.

In order to smoothly bond the heat dissipation cover 103 to the first chip 101a and the second chip 101b, the surface of the first inner thermal interface layer 110a away from the package substrate 102 is flush with the surface of the second inner thermal interface layer 110b away from the package substrate 102. In this case, as shown in FIG. 12a, when the first chip 101a and the second chip 101b are chips with different functions or types, and their thicknesses may be different, the first inner thermal interface layer 110a and the second inner thermal interface layer 110a The thicknesses of 110b may be different, so that the thickness difference between the first chip 101a and the second chip 101b can be compensated for by the difference in thickness between the first inner thermal interface layer 110a and the second inner thermal interface layer 110b.

On this basis, when the heat dissipation device 11 presses the heat dissipation cover 103, the pressure exerted by the heat dissipation device 11 on the heat dissipation cover 103 effectively acts on the first chip 101a and the second chip 101b, as shown in FIG. 12a, At least one boss structure in the upper cover 31 may include a first boss structure 310a and a second boss structure 310b. The first boss structure 310a is in contact with the first inner thermal interface layer 110a, and the second boss structure 310b is in contact with the second inner thermal interface layer 110b.

The above-mentioned first and second boss structures 310a and 310b are arranged in the same manner as described above. For example, as shown in FIG. surface) may protrude from the surface of the first connecting structure 311 away from the chip 101 . Surfaces (lower surfaces) of the first boss structure 310a and the second boss structure 310b close to the package substrate 102 may be flat. In this case, as shown in FIG. 12a, the contact surface of the first boss structure 310a and the first inner thermally conductive interface layer 110a may completely cover the first chip 101a. Similarly, the contact surface of the second boss structure 310b and the second inner thermally conductive interface layer 110b may completely cover the second chip 101b.

Or, for another example, as shown in FIG. 12 b , the surfaces (upper surfaces) of the first and second boss structures 310 a and 310 b away from the package substrate 102 may protrude from the surface of the first connecting structure 311 away from the chip 101 . In addition, the first boss structure 310 a and the second boss structure 310 b are close to the surface (lower surface) of the chip 101 and protrude from the surface of the first connecting structure 311 close to the chip 101 . In this case, as shown in FIG. 12 b , the vertical projection of the contact surface of the first boss structure 310 a and the first inner thermal interface layer 110 a on the packaging substrate 102 may be located at the vertical projection of the first chip 101 a on the packaging substrate 102 within the projection range. Similarly, the vertical projection of the contact surface of the second boss structure 310b and the second inner thermal interface layer 110b on the packaging substrate 102 may be within the range of the vertical projection of the second chip 101b on the packaging substrate 102 .

On this basis, the above-mentioned upper cover 31 may further include a second engaging structure 313 as shown in FIG. 12a or FIG. 12b. The second engaging structure 313 is located between the first boss structure 310a and the second boss structure 310b, and is connected with the first boss structure 310a and the second boss structure 310b.

Based on this, when the heat dissipation device 11 presses the heat dissipation cover 103 , the pressure exerted by the heat dissipation device 11 on the heat dissipation cover 103 effectively acts on the first boss structure 310 a and the second boss structure 310 b , the upper cover 31 At least one second groove 314 is also included, and the second groove 314 is formed on one side surface of the second connecting structure 313 close to the package substrate 102 . The setting method of the size of the second groove 314 can be the same as that of the first groove 312 , which is not repeated here.

In addition, in the case where the package substrate 102 is the redistribution layer, the package substrate 102 is easily deformed during a temperature change. At this time, when the first groove 312 and the second groove 314 are provided on the upper cover 31 of the heat dissipation cover 103, the rigidity of the upper cover 31 is weakened, so that the package substrate 102 can be moved when the package substrate 102 is deformed. There is a certain decoupling effect with the movement of the heat dissipation cover 103 , which reduces the restraint of the chip when it follows the movement of the package substrate 102 . Therefore, cracks in the molding material 400 shown in FIG. 12c between two adjacent chips, for example, the first chip 101a and the second chip 101b described above, can be reduced. In the embodiments of the present application, the molding material 400 in some drawings is not shown.

In addition, in other embodiments of the present application, when the chip package structure 10 includes the first chip 101a and the second chip 101b, as shown in FIG. 13 , the first chip 101a and the second chip 101b can pass through the An inner thermally conductive interface layer 110a and a second inner thermally conductive interface layer 110b are connected to the same boss structure 310 . The boss structure 310 is in contact with both the first inner thermally conductive interface layer 110a and the second inner thermally conductive interface layer 110b. The arrangement of the boss structure 310 is the same as described above, and will not be repeated here. When the heat dissipation device 11 presses the heat dissipation cover 103, the pressure can be transmitted to the first chip 101a and the second chip 101b through the same boss structure 310, so that the structure of the heat dissipation cover 103 can be simplified.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited to this. should be covered within the scope of protection of this application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims (19)

1. A chip packaging structure, characterized in that it includes:

   a package substrate having a first surface;

   at least one chip, disposed on the first surface of the package substrate;

   at least one inner thermal interface layer; the at least one inner thermal interface layer respectively covers the surface of the at least one chip on the side away from the package substrate;

   a heat dissipation cover, including an upper cover and a plurality of side walls; the plurality of side walls are arranged end to end in sequence around the circumference of the upper cover, and are connected with the first surface; the heat dissipation cover is connected to the packaging substrate A accommodating cavity for accommodating the at least one chip is formed therebetween;

   Wherein, the upper cover includes at least one boss structure and a first connecting structure; each boss structure in the at least one boss structure is in contact with at least one of the inner thermally conductive interface layers, and the at least one boss structure Each boss structure in the platform structure is connected with the side wall through the first connecting structure; the maximum thickness D1_max of the boss structure is greater than the maximum thickness D2_max of the first connecting structure, and the boss structure is The structure is away from the surface of the chip, and protrudes from the surface of the first connecting structure away from the chip; the direction of the thickness is perpendicular to the direction of the first surface.
2. The chip package structure according to claim 1, wherein the boss structure is close to the surface of the chip, and protrudes from the surface of the first connecting structure close to the chip.
3. The chip package structure according to claim 1, wherein a surface of the boss structure close to the chip is flush with a surface of the first connecting structure close to the chip.
4. The chip package structure according to any one of claims 1-3, characterized in that, along the direction from the boss structure to the sidewall, the thickness D2 of the first connecting structure gradually decreases.
5. The chip packaging structure according to claim 4, wherein the first connecting structure is close to the surface of the chip, or the surface far from the chip is flat.
6. The chip packaging structure according to claim 4, wherein,

   A surface of the side wall away from the packaging substrate is an upper reference surface, and a surface of the inner thermal interface layer away from the packaging substrate is a lower reference surface;

   There is a reference thickness D0 between the upper reference plane and the lower reference plane; the minimum thickness D2_min of the first connecting structure is smaller than the reference thickness D0.
7. The chip package structure according to claim 6, wherein 20%×D0≤D2_min≤80%×D0.
8. The chip packaging structure according to claim 6 or 7, wherein,

   There is a maximum distance L_max between the surface of the boss structure away from the chip and the upper reference plane; L_max<D0.
9. The chip package structure according to claim 8, wherein 0.01mm≤L_max≤0.2mm.
10. The chip packaging structure according to claim 4, wherein,

    The surface of the boss structure away from the chip is a first arc surface;

    In the surface of the first connecting structure away from the chip, the part close to the first arc surface is a second arc surface, the curvature of the second arc surface and the first arc surface is the same, and the first arc surface is the same as the first arc surface. Two arc surfaces are connected to the first arc surface; the vertical projection of the chip corresponding to the boss structure on the first surface is located, and the first arc surface and the second arc surface are located on the first arc surface. within the vertical projection of the surface;

    The vertical projection of the side of the second arc surface away from the first arc surface on the first surface has a first contour; the vertical projection of the chip corresponding to the boss structure on the first surface has a second contour;

    The maximum distance Hmax between the first contour and the second contour satisfies: Hmax≤2mm.
11. The chip packaging structure according to any one of claims 1-9, wherein,

    At least a part of the surface of the boss structure away from the chip is a third arc surface;

    The vertical projection of the third arc surface on the first surface is located, and the chip corresponding to the boss structure is within the range of the vertical projection of the first surface;

    The vertical projection of the third arc surface on the first surface has a third contour; the vertical projection of the chip corresponding to the boss structure on the first surface has a second contour;

    The maximum distance Hmax between the third contour and the second contour satisfies: Hmax≤2mm.
12. The chip packaging structure according to any one of claims 1-9, wherein,

    The surface of the boss structure away from the chip is a first arc surface;

    The vertical projection of the first arc surface on the first surface completely overlaps with the vertical projection of the chip corresponding to the boss structure on the first surface.
13. The chip package structure according to any one of claims 1-12, wherein,

    The upper cover also includes at least one first groove, the first groove is opened on a side surface of the first connecting structure close to the chip; the first groove is located on the first connecting structure one end away from the boss structure.
14. The chip package structure according to claim 13, wherein the first groove is an annular groove surrounding the at least one chip.
15. The chip package structure according to claim 13 or 14, wherein the depth S1 of the first groove satisfies: 20%×D2_max≤S1≤80%×D2_max; the groove width L1 of the first groove Satisfaction: 0.1mm≤L1≤20mm.
16. The chip package structure according to any one of claims 1-15, wherein,

    The at least one chip includes a first chip and a second chip; the at least one inner thermal interface layer includes a first inner thermal interface layer covering the first chip and a second inner thermal interface layer covering the second chip ; the surface of the first inner thermally conductive interface layer away from the packaging substrate is flush with the surface of the second inner thermally conductive interface layer away from the packaging substrate;

    The at least one boss structure includes a first boss structure and a second boss structure, the first boss structure is in contact with the first inner thermally conductive interface layer, and the second boss structure is in contact with the first boss structure. The two inner thermal interface layers are in contact;

    The upper cover further includes a second engagement structure, the second engagement structure is located between the first boss structure and the second boss structure, and is connected with the first boss structure and the second boss structure. The boss structure is connected.
17. The chip package structure according to claim 16, wherein,

    The upper cover further includes at least one second groove, and the second groove is opened on a side surface of the second connecting structure close to the package substrate.
18. The chip package structure according to any one of claims 1-15, wherein,

    The at least one chip includes a first chip and a second chip; the at least one inner thermal interface layer includes a first inner thermal interface layer covering the first chip and a second inner thermal interface layer covering the second chip ; the surface of the first inner thermally conductive interface layer away from the packaging substrate is flush with the surface of the second inner thermally conductive interface layer away from the packaging substrate;

    One of the boss structures is in contact with the first inner thermally conductive interface layer and the second inner thermally conductive interface layer.
19. An electronic device, characterized in that it comprises a heat sink, an external thermally conductive interface layer, a circuit board, and the chip packaging structure according to any one of claims 1-18 disposed on the circuit board;

    The outer thermal interface layer is located between the heat dissipation device and the heat dissipation cover in the chip packaging structure, and is connected with the heat dissipation device and the heat dissipation cover; the heat dissipation device is also connected with the circuit board .

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